CN107230710A - The preparation method of GaN high electron mobility transistor - Google Patents
The preparation method of GaN high electron mobility transistor Download PDFInfo
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- CN107230710A CN107230710A CN201610178227.4A CN201610178227A CN107230710A CN 107230710 A CN107230710 A CN 107230710A CN 201610178227 A CN201610178227 A CN 201610178227A CN 107230710 A CN107230710 A CN 107230710A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 41
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 74
- 230000004888 barrier function Effects 0.000 claims abstract description 55
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 29
- 238000000151 deposition Methods 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
- 238000001556 precipitation Methods 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 73
- 239000002184 metal Substances 0.000 claims description 73
- 238000000034 method Methods 0.000 claims description 29
- 238000001259 photo etching Methods 0.000 claims description 22
- 238000000137 annealing Methods 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 11
- -1 aluminium copper silicon Chemical compound 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 6
- 239000012528 membrane Substances 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical class [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 230000004907 flux Effects 0.000 abstract description 5
- 230000009467 reduction Effects 0.000 abstract description 5
- 230000002401 inhibitory effect Effects 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 8
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The present invention provides a kind of preparation method of GaN high electron mobility transistor, passes through the surface precipitation medium layer in gallium nitride epitaxial slice；It is sequentially prepared the Ohm contact electrode and grid of transistor；The depositing insulating layer on the surface of transistor；Etching insulating layer formation grid field plate hole, deposit forms the grid field plate being connected with grid.So as to effectively transmit and extract electric flux from the surface of grid by dielectric layer, serve the effect of reduction transistor surface electric field, also by setting the grid field plate being connected with grid, realize the inhibitory action to current collapse, the breakdown characteristics of transistor device are improved, are solved in the prior art because insulating barrier is easily punctured so that the problem of transistor device fails in advance.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of GaN high electron mobility crystal
The preparation method of pipe.
Background technology
Gallium nitride is third generation semiconductor material with wide forbidden band, because it has big energy gap, high electronics
The advantages of saturation rate, high breakdown electric field, higher heat-conductivity, corrosion-resistant and radiation resistance, quilt
It is considered the optimal material of making shortwave opto-electronic device and high voltagehigh frequency rate high power device.
Because the gallium nitride based on gallium nitride/aluminum gallium nitride structure has higher electron mobility, nitridation
Gallium/aluminum gallium nitride HEMT (High-Electron-Mobility Transistors,
Abbreviation HEMTs) have become study hotspot.Because at the hetero-junctions of gallium nitride/aluminum gallium nitride
High concentration, the two-dimensional electron gas (2DEG) of high mobility can be formed, while hetero-junctions is to 2DEG
With good adjustment effect.
And due in the two-dimensional electron gas of the hetero-junctions of gallium nitride/aluminum gallium nitride electron concentration it is very high, if
Only grid field plate and undoped with gallium nitride/aluminum gallium nitride, the gate edge electric field density of device is very big,
Can occur insulating barrier breakdown in advance, cause component failure.
The content of the invention
The present invention provides a kind of preparation method of GaN high electron mobility transistor, for solving existing
The gate edge electric field density of the transistor occurred in the preparation of some GaN high electron mobility transistors
Greatly, insulating barrier produces the problem of transistor device fails by breakdown in advance caused by.
The preparation method for the GaN high electron mobility transistor that the present invention is provided, including：
In the surface precipitation medium layer of gallium nitride epitaxial slice；
It is sequentially prepared the Ohm contact electrode and grid of transistor；
The depositing insulating layer on the surface of transistor；
The insulating barrier formation grid field plate hole is etched, deposit forms the grid field plate being connected with the grid.
Further, in above-mentioned preparation method, the etching insulating barrier formation and the grid
The grid field plate hole of contact, deposit forms grid field plate, including：
Dry etching is carried out to the insulating barrier, the grid field plate hole is formed, wherein, the grid field plate
Hole is contacted with the surface of the grid；
With the metal of surface deposition first of the insulating barrier in the grid field plate hole, the first metal is formed
Layer；
Photoetching and etching are carried out to the first metal layer, the grid field plate is formed.
Further, it is described in the grid field plate hole and the insulating barrier in above-mentioned preparation method
The metal of surface deposition first, formed the first metal layer, including：
Using magnetron sputtering membrane process, the surface with the insulating barrier in the grid field plate hole is deposited
Metallic aluminium copper silicon, forms the first metal layer.
Further, in above-mentioned preparation method, the surface precipitation medium in gallium nitride epitaxial slice
Layer, including：
In the surface deposit hafnium oxides of the gallium nitride epitaxial slice, the dielectric layer is formed.
Further, in above-mentioned preparation method, the Ohm contact electrode for preparing transistor, bag
Include：
The dielectric layer is etched, two ohmic contact holes are formed respectively；
In two ohmic contact holes and the surface of the dielectric layer deposits the second metal, and shape
Into second metal layer；
Photoetching, etching and annealing are carried out to the second metal layer, the Ohmic contact electricity is formed
Pole.
Further, in above-mentioned preparation method, the grid for preparing transistor, including：
The barrier layer in the dielectric layer and the part gallium nitride epitaxial slice is etched, grid is formed and connects
Contact hole；
In the gate contact hole, the table of the surface of the Ohm contact electrode and the dielectric layer
Face deposits the 3rd metal, forms the 3rd metal level；
Photoetching and etching are carried out to the 3rd metal level, the grid is formed.
Further, in above-mentioned preparation method, the depth that the barrier layer is etched is the barrier layer
Thickness half.
Further, in above-mentioned preparation method, the depositing insulating layer on the surface of transistor,
Including：
On the surface of the Ohm contact electrode, the surface of the surface of the dielectric layer and the grid
Deposited silicon nitride, forms the insulating barrier.
Further, it is described in two ohmic contact holes and institute in above-mentioned preparation method
The surface for stating dielectric layer deposits the second metal, and is formed before second metal layer, in addition to：
The ohmic contact hole is cleaned.
Further, in above-mentioned preparation method, the annealing is included under conditions of nitrogen,
840 DEG C of annealing temperature is used to carry out annealing process of the annealing time for 30s.
A kind of preparation method for GaN high electron mobility transistor that the present invention is provided passes through in gallium nitride
The surface precipitation medium layer of epitaxial wafer；It is sequentially prepared the Ohm contact electrode and grid of transistor；In crystalline substance
Depositing insulating layer on the surface of body pipe；The insulating barrier formation grid field plate hole is etched, deposit is formed and institute
State the connected grid field plate of grid.So as to effectively transmit and extract electricity from the surface of grid by dielectric layer
Flux, serves the effect of reduction transistor surface electric field, also by setting the grid being connected with grid
Plate, realizes the inhibitory action to current collapse, improves the breakdown characteristics of transistor device, solves existing
Have in technology because insulating barrier is easily punctured so that the problem of transistor device fails in advance.
Brief description of the drawings
Fig. 1 is a kind of preparation side for GaN high electron mobility transistor that the embodiment of the present invention one is provided
The schematic flow sheet of method；
Fig. 2 is a kind of preparation side for nitridation man HEMT that the embodiment of the present invention two is provided
The schematic flow sheet of method；
The section of GaN high electron mobility transistor after steps 201 of the Fig. 3 to perform embodiment two
Structural representation；
The section of GaN high electron mobility transistor after steps 202 of the Fig. 4 to perform embodiment two
Structural representation；
The section of GaN high electron mobility transistor after steps 203 of the Fig. 5 to perform embodiment two
Structural representation；
The section of GaN high electron mobility transistor after steps 204 of the Fig. 6 to perform embodiment two
Structural representation；
The section of GaN high electron mobility transistor after steps 205 of the Fig. 7 to perform embodiment two
Structural representation；
The section of GaN high electron mobility transistor after steps 206 of the Fig. 8 to perform embodiment two
Structural representation；
The section of GaN high electron mobility transistor after steps 207 of the Fig. 9 to perform embodiment two
Structural representation；
Figure 10 cuts open for the GaN high electron mobility transistor after the step 208 of execution embodiment two
Face structural representation；
Figure 11 cuts open for the GaN high electron mobility transistor after the step 209 of execution embodiment two
Face structural representation；
Figure 12 cuts open for the GaN high electron mobility transistor after the step 210 of execution embodiment two
Face structural representation；
The section of GaN high electron mobility transistor after steps 211 of the Figure 13 to perform embodiment two
Structural representation.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with this hair
Accompanying drawing in bright embodiment, the technical scheme in the embodiment of the present invention is clearly and completely described,
Obviously, described embodiment is a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained under the premise of creative work is not made
The every other embodiment obtained, belongs to the scope of protection of the invention.
Fig. 1 is a kind of preparation side for GaN high electron mobility transistor that the embodiment of the present invention one is provided
The schematic flow sheet of method, as shown in figure 1, the preparation method comprises the following steps：
Step 101, the surface precipitation medium layer in gallium nitride epitaxial slice.
It should be noted that gallium nitride epitaxial slice used in various embodiments of the present invention can be by using
Prepared by the technique of deposition, specifically include by lower from the substrate being above sequentially prepared in gallium nitride epitaxial slice, delays
Layer and barrier layer are rushed, wherein, the material of substrate can use element silicon, and its thickness can use 625 microns；
The material of cushion can use compound gallium nitride, and its thickness can use 3 microns；The material of barrier layer
Compound gallium nitride aluminium can be used, its thickness can use 25 microns.
On the surface of the barrier layer of gallium nitride epitaxial slice, dielectric layer is formed by depositing operation.Specifically,
In the surface deposited compound hafnium oxide of gallium nitride epitaxial slice, dielectric layer is formed, for example, using low pressure
Power chemical vapour deposition technique gallium nitride epitaxial slice surface deposit hafnium oxides, so as to form dielectric layer.
Wherein, the thickness of the dielectric layer can use 30 nanometers.
Step 102, the Ohm contact electrode and grid for being sequentially prepared transistor.
After the preparation to dielectric layer is completed, the ohm for being sequentially prepared transistor in dielectric layer surface connects
Touched electrode and grid, the preparation technology to Ohm contact electrode and grid can be using current into shortening
Standby technique, those skilled in the art can voluntarily select according to actual conditions, and the present invention is to this without limit
It is fixed.
Step 103, the depositing insulating layer on the surface of transistor.
The depositing insulating layer on the surface of transistor.Specifically, on the surface of Ohm contact electrode, grid
The surface of pole and the surface of dielectric layer, insulating barrier is formed by depositing operation.For example, using low-pressure
Chemical vapour deposition technique is in the surface of Ohm contact electrode, the surface of grid and the surface deposition of dielectric layer
Compound silicon nitride, forms insulating barrier.Wherein, the thickness of the insulating barrier can use 500 nanometers.
Step 104, etching insulating layer formation grid field plate hole, deposit form the grid field plate being connected with grid.
The insulating barrier obtained by etch step 103, forms grid field plate hole, and deposit is formed and grid phase
Grid field plate even.Specifically, can be performed etching by dry etch process to insulating barrier, grid are formed
Plate hole, wherein, grid field plate hole is contacted with the surface of grid.With the surface of insulating barrier in grid field plate hole
The first metal is deposited, the first metal layer is formed, for example, magnetron sputtering membrane process can be used, in grid
With the surface deposited metal aluminium copper silicon of insulating barrier in field plate hole, the first metal layer is formed.To the first metal
Layer carries out photoetching and etching, forms grid field plate, photoetching process may include gluing, exposed and developed to wait stream
Journey.
A kind of preparation method for GaN high electron mobility transistor that the embodiment of the present invention one is provided, leads to
Cross the surface precipitation medium layer in gallium nitride epitaxial slice；Be sequentially prepared transistor Ohm contact electrode and
Grid；The depositing insulating layer on the surface of transistor；Etching insulating layer formation grid field plate hole, deposits shape
Into the grid field plate being connected with grid.So as to effectively transmit and extract from the surface of grid by dielectric layer
Electric flux, serves the effect of reduction transistor surface electric field, also by setting the grid being connected with grid
Field plate, realizes the inhibitory action to current collapse, improves the breakdown characteristics of transistor device, solves
In the prior art because insulating barrier is easily punctured so that the problem of transistor device fails in advance.
In order to further illustrate the preparation method for the GaN high electron mobility transistor that the present invention is provided,
On the basis of preparation method shown in Fig. 1, Fig. 2 is that a kind of nitridation man that the embodiment of the present invention two is provided is high
The schematic flow sheet of the preparation method of electron mobility transistor, the embodiment two shown in Fig. 2 will be to nitridation
The preparation method of gallium HEMT is described in detail.
Step 201, the surface precipitation medium layer in gallium nitride epitaxial slice.
The section of GaN high electron mobility transistor after steps 201 of the Fig. 3 to perform embodiment two
Structural representation, as shown in figure 3, the gallium nitride epitaxial slice in embodiment two is respectively substrate from bottom to top
11, cushion 12 and barrier layer 13, wherein, the material of substrate can use element silicon, and its thickness can be adopted
With 625 microns；The material of cushion can use compound gallium nitride, and its thickness can use 3 microns；
The material of barrier layer can use compound gallium nitride aluminium, and its thickness can use 25 microns.In gallium nitride
The surface of the barrier layer 13 of epitaxial wafer, is deposited by depositing operation to hafnium oxide, forms medium
Layer 14, the thickness of dielectric layer 14 can use 300 nanometers.In the execution method and Fig. 1 of step 201
Step 101 it is identical, will not be described here.
Step 202, etch media layer, form two ohmic contact holes respectively.
Step 203, in two ohmic contact holes and dielectric layer surface deposit the second metal, and
Form second metal layer.
Step 204, to second metal layer carry out photoetching, etching and make annealing treatment, formed Ohmic contact
Electrode.
The Ohm contact electrode for preparing transistor in step 102 in method shown in above-mentioned Fig. 1, tool
Body may include step 202-204.GaN high electron after steps 202 of the Fig. 4 to perform embodiment two
The cross-sectional view of mobility transistor, as shown in figure 4, by using the technique of dry etching,
In the edge of the dielectric layer 14 of GaN high electron mobility transistor, dielectric layer 14 is carved
Lose and form two centrosymmetric ohmic contact holes 15, and the diameter of each ohmic contact hole 15 can
Using 5 microns.
The section of GaN high electron mobility transistor after steps 203 of the Fig. 5 to perform embodiment two
Structural representation, as shown in figure 5, the table first in two ohmic contact holes 15 with dielectric layer 14
Face deposits the second metal, forms second metal layer 16.Specifically, magnetron sputtering membrane process can be used,
Titanium, metallic aluminium, gold are sequentially depositing with the surface of dielectric layer 14 in two ohmic contact holes 15
Belong to titanium and compound titanium nitride, to form second metal layer 16.
Further, before step 203, in addition to：Ohmic contact hole is cleaned.Specifically
, in two ohmic contact holes 15 and the surface of dielectric layer 14 deposits the second metal, and formed
Before second metal layer 16, also ohmic contact hole 15 is cleaned.Done to dielectric layer 14
Method is etched and formed after ohmic contact hole 15, and the surface in ohmic contact hole 15 with dielectric layer 14 can be deposited
In impurity things such as impurity, particles, it can be achieved to remove on transistor device by the cleaning to transistor device
Impurity thing effect.For example, the impurity in the method that DFF+SC1+SC2 can be used, removal devices
Thing, specifically, carries out first step cleaning, then using dilute by using the hydrofluoric acid solution after dilution
The mixed solution of ammoniacal liquor and hydrogen peroxide after releasing is cleaned again, finally uses the hydrochloric acid after dilution and double
The mixed solution of oxygen water is further cleaned, and then is removed in ohmic contact hole 15 and its dielectric layer 14
Surface present on impurity thing.
The section of GaN high electron mobility transistor after steps 204 of the Fig. 6 to perform embodiment two
Structural representation, as shown in fig. 6, after second metal layer 16 is formed, being adopted to second metal layer 16
With photoetching, the technique of etching and annealing forms Ohm contact electrode 17.Specifically, by right
Second metal layer 16 carries out photoetching and etching, makes in only ohmic contact hole 15 and its marginal portion
Second metal layer 16 is retained, then by being made annealing treatment, and makes to be formed titanium, aluminium and titanium nitride
Alloy, and second metal layer 16 can also be at it after being reacted with the aluminum gallium nitride in barrier layer 13
Alloy is formed on contact surface, so as to obtain the Ohm contact electrode 17 with relatively low ohmic contact resistance.Its
In, the program of photoetching includes gluing, exposed and developed, and making annealing treatment can specifically use in nitrogen
Under the conditions of, use 840 DEG C of annealing temperature to carry out annealing process of the annealing time for 30s.
Barrier layer in step 205, etch media layer and partial nitridation gallium epitaxial wafer, forms grid
Contact hole.
Step 206, in gate contact hole, the surface of Ohm contact electrode and the surface of dielectric layer
The 3rd metal is deposited, the 3rd metal level is formed.
Step 207, photoetching and etching are carried out to the 3rd metal level, form grid.
The grid for preparing transistor in step 102 in method shown in above-mentioned Fig. 1, specifically may include
Step 205-207.GaN high electron mobility after steps 205 of the Fig. 7 to perform embodiment two is brilliant
The cross-sectional view of body pipe, as shown in fig. 7, after the preparation of Ohm contact electrode 17 is completed,
In the center of dielectric layer 14, to the barrier layer in the dielectric layer 14 and partial nitridation gallium epitaxial wafer
13 carry out dry etching, form the gate contact hole 18 for being deep to barrier layer 13.Wherein, the grid connects
The diameter of contact hole 18 can use 2 microns.Further, the depth that barrier layer 13 is etched is potential barrier
The half of the thickness of layer 13.
The section of GaN high electron mobility transistor after steps 206 of the Fig. 8 to perform embodiment two
Structural representation, as shown in figure 8, in gate contact hole 18, the surface of Ohm contact electrode 17
And the surface of dielectric layer 14 deposits the 3rd metal, the 3rd metal level 19 is formed.Specifically, can adopt
With magnetron sputtering membrane process, in gate contact hole 18, the surface of Ohm contact electrode 17 and
The surface of dielectric layer 14 is sequentially depositing metallic nickel and metallic copper, to form the 3rd metal level 19.
The section of GaN high electron mobility transistor after steps 207 of the Fig. 9 to perform embodiment two
Structural representation, as shown in figure 9, carrying out photoetching and etching to the 3rd metal level 19, forms grid 20.
Specifically, to the 3rd metal level 19 using photoetching and the technique of etching, making only to retain positioned at grid
3rd metal level 19 at contact hole 18 and its edge, and form grid 20.It should be noted that
The grid 20 of formation makes transistor device surface with being contacted respectively with barrier layer 13 and dielectric layer 14
Electric flux dielectric layer 14 can be transferred to by grid 20 very well, so as to realize reduction transistors
The effect of part surface field.
Step 208, the depositing insulating layer on the surface of transistor.
Figure 10 cuts open for the GaN high electron mobility transistor after the step 208 of execution embodiment two
Face structural representation, as shown in Figure 10, on the surface of Ohm contact electrode 17, the surface of grid 20
With the surface depositing insulating layer 21 of dielectric layer 14.Specifically, low-pressure chemical vapor deposition can be used
The depositing operation formation insulating barrier 21 of method, the thickness of insulating barrier 21 can use 500 nanometers.Step 208
Execution method it is identical with the step 103 in Fig. 1, will not be described here.
Step 209, dry etching is carried out to insulating barrier, form grid field plate hole, wherein, grid field plate hole
Contacted with the surface of grid.
Step 210, in grid field plate hole and insulating barrier the metal of surface deposition first, formed the first gold medal
Belong to layer.
Step 211, photoetching and etching are carried out to the first metal layer, form grid field plate.
Step 104 in method shown in above-mentioned Fig. 1, specifically may include step 209-211.Figure 11 is
Perform the cross-section structure signal of the GaN high electron mobility transistor after the step 209 of embodiment two
Figure, as shown in figure 11, after insulating barrier 21 is prepared, dry etching, shape is carried out to insulating barrier 21
Into grid field plate hole 22, wherein, grid field plate hole 22 is contacted with the surface of grid 20.Specifically, grid
Plate hole 22 is located at the surface of grid 20, and its grid field plate hole 22 is contacted with the surface of grid 20, grid
The diameter in field plate hole 22 can be identical with the diameter in gate contact hole 18, such as 2 microns.
Figure 12 cuts open for the GaN high electron mobility transistor after the step 210 of execution embodiment two
Face structural representation, as shown in figure 12, in the grid field plate hole 22 and insulating barrier 21 surface deposition the
One metal, forms the first metal layer 23.Specifically, magnetron sputtering membrane process can be used, in grid
With the surface deposited metal aluminium copper silicon of insulating barrier 21 in plate hole 22, the first metal layer 23 is formed.
The section of GaN high electron mobility transistor after steps 211 of the Figure 13 to perform embodiment two
Structural representation, as shown in figure 13, after the first metal layer 23 is formed, to the first metal layer 23
Photoetching and etching are carried out, grid field plate 24 is formed.Specifically, passing through the photoetching to the first metal layer 23
And etching, the first metal layer 23 of in only grid field plate hole 22 and its marginal portion is retained, and
Grid field plate 24 is formed, wherein, the program of photoetching includes gluing, exposed and developed.Need explanation
It is that the bottom surface of grid field plate 24 is contacted with the surface of grid 20, so as to inhibit the electricity of transistor device
Avalanche is flowed, breakdown characteristics are improved, it is to avoid transistor device fails.
A kind of preparation method for GaN high electron mobility transistor that the embodiment of the present invention two is provided, leads to
Cross the surface precipitation medium layer in gallium nitride epitaxial slice；Etch media layer, forms two ohms and connects respectively
Contact hole；In two ohmic contact holes and dielectric layer surface deposit the second metal, and formed second
Metal level；Photoetching, etching and annealing are carried out to second metal layer, Ohm contact electrode is formed；
Barrier layer in etch media layer and partial nitridation gallium epitaxial wafer, forms gate contact hole；In grid
In contact hole, the surface of the surface of Ohm contact electrode and dielectric layer deposits the 3rd metal, forms the
Three metal levels；Photoetching and etching are carried out to the 3rd metal level, grid is formed；On the surface of transistor
Depositing insulating layer；Dry etching is carried out to insulating barrier, grid field plate hole is formed, wherein, grid field plate hole with
The surface contact of grid；With the metal of surface deposition first of insulating barrier in grid field plate hole, first is formed
Metal level；Photoetching and etching are carried out to the first metal layer, grid field plate is formed.Pass through dielectric layer and grid
Contact and the grid contact with grid field plate, on the one hand, enable dielectric layer effectively by crystal
The electric flux of pipe surface is evacuated and turned on, and serves the beneficial effect of electric field near reduction grid,
On the other hand so that grid field plate can suppress the current collapse of transistor device, serve and avoid insulation
The beneficial effect that layer is punctured in advance, and then overcome existing GaN high electron mobility transistor
Preparation method in, easily make transistor device breakdown and cause failure the problem of.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than
It is limited；Although the present invention is described in detail with reference to foregoing embodiments, this area
Those of ordinary skill should be understood：It can still enter to the technical scheme described in foregoing embodiments
Row modification, or equivalent substitution is carried out to which part or all technical characteristic；And these modification or
Person replaces, and the essence of appropriate technical solution is departed from the model of various embodiments of the present invention technical scheme
Enclose.
Claims (10)
1. a kind of preparation method of GaN high electron mobility transistor, it is characterised in that including：
In the surface precipitation medium layer of gallium nitride epitaxial slice；
It is sequentially prepared the Ohm contact electrode of transistor, grid；
The depositing insulating layer on the surface of transistor；
The insulating barrier formation grid field plate hole is etched, deposit forms the grid field plate being connected with the grid.
2. preparation method according to claim 1, it is characterised in that the etching is described absolutely
Edge layer formation and the grid field plate hole of the gate contact, deposit form grid field plate, including：
Dry etching is carried out to the insulating barrier, the grid field plate hole is formed, wherein, the grid field plate
Hole is contacted with the surface of the grid；
With the metal of surface deposition first of the insulating barrier in the grid field plate hole, the first metal is formed
Layer；
Photoetching and etching are carried out to the first metal layer, the grid field plate is formed.
3. preparation method according to claim 2, it is characterised in that described in the grid
With the metal of surface deposition first of the insulating barrier in plate hole, the first metal layer is formed, including：
Using magnetron sputtering membrane process, the surface with the insulating barrier in the grid field plate hole is deposited
Metallic aluminium copper silicon, forms the first metal layer.
4. preparation method according to claim 1, it is characterised in that described in epitaxy of gallium nitride
The surface precipitation medium layer of piece, including：
In the surface deposit hafnium oxides of the gallium nitride epitaxial slice, the dielectric layer is formed.
5. preparation method according to claim 1, it is characterised in that described to prepare transistor
Ohm contact electrode, including：
The dielectric layer is etched, two ohmic contact holes are formed respectively；
In two ohmic contact holes and the surface of the dielectric layer deposits the second metal, and shape
Into second metal layer；
Photoetching, etching and annealing are carried out to the second metal layer, the Ohmic contact electricity is formed
Pole.
6. preparation method according to claim 5, it is characterised in that described to prepare transistor
Grid, including：
The barrier layer in the dielectric layer and the part gallium nitride epitaxial slice is etched, grid is formed and connects
Contact hole；
In the gate contact hole, the table of the surface of the Ohm contact electrode and the dielectric layer
Face deposits the 3rd metal, forms the 3rd metal level；
Photoetching and etching are carried out to the 3rd metal level, the grid is formed.
7. preparation method according to claim 6, it is characterised in that the barrier layer is etched
Depth for the barrier layer thickness half.
8. preparation method according to claim 6, it is characterised in that described in transistor
Depositing insulating layer on surface, including：
On the surface of the Ohm contact electrode, the surface of the surface of the dielectric layer and the grid
Deposited silicon nitride, forms the insulating barrier.
9. the preparation method according to claim any one of 5-8, it is characterised in that described two
In the individual ohmic contact hole and surface of the dielectric layer deposits the second metal, and forms the second gold medal
Before category layer, in addition to：
The ohmic contact hole is cleaned.
10. the preparation method according to claim any one of 5-8, it is characterised in that described to move back
Fire processing is included under conditions of nitrogen, uses 840 DEG C of annealing temperature to carry out annealing time for 30s's
Annealing process.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008306083A (en) * | 2007-06-11 | 2008-12-18 | Nec Corp | Iii-v nitride semiconductor field-effect transistor and its manufacturing method |
| CN104425487A (en) * | 2013-09-10 | 2015-03-18 | 株式会社东芝 | Semiconductor device |
| CN105355659A (en) * | 2015-11-06 | 2016-02-24 | 西安电子科技大学 | Trench-gate AlGaN/GaN HEMT device structure and manufacturing method |
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2016
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008306083A (en) * | 2007-06-11 | 2008-12-18 | Nec Corp | Iii-v nitride semiconductor field-effect transistor and its manufacturing method |
| CN104425487A (en) * | 2013-09-10 | 2015-03-18 | 株式会社东芝 | Semiconductor device |
| CN105355659A (en) * | 2015-11-06 | 2016-02-24 | 西安电子科技大学 | Trench-gate AlGaN/GaN HEMT device structure and manufacturing method |
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Application publication date: 20171003 |