CN107230634A - The preparation method of gallium nitride transistor - Google Patents
The preparation method of gallium nitride transistor Download PDFInfo
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- CN107230634A CN107230634A CN201610178295.0A CN201610178295A CN107230634A CN 107230634 A CN107230634 A CN 107230634A CN 201610178295 A CN201610178295 A CN 201610178295A CN 107230634 A CN107230634 A CN 107230634A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 53
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 14
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 53
- 238000000034 method Methods 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 16
- 238000005036 potential barrier Methods 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 238000001259 photo etching Methods 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 230000000903 blocking effect Effects 0.000 claims description 6
- 229910003978 SiClx Inorganic materials 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 9
- 230000001629 suppression Effects 0.000 abstract description 8
- 238000000151 deposition Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- JZMKGUPOUQRDMD-UHFFFAOYSA-N oxygen(2-) tetraethyl silicate titanium(4+) Chemical compound [O--].[O--].[Ti+4].CCO[Si](OCC)(OCC)OCC JZMKGUPOUQRDMD-UHFFFAOYSA-N 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present invention provides a kind of preparation method of gallium nitride transistor, and this method emits layer, silicon nitride layer and oxide layer by growing GaN successively on the surface of AlGaN potential barrier first；And layer is emitted to the oxide layer under first area, silicon nitride layer and GaN performed etching, form source-drain electrode contact hole；Performed etching again by the metal level being pointed on default second area, form source-drain electrode；And in being formed after source-drain electrode, further by etching technics and depositing technics formation grid, realize suppression device surface charge, control device current collapse phenomenon, the instable purpose of suppression device, it is possible to increase the power output and power efficiency of device.
Description
Technical field
The present invention relates to the manufacturing process technology field of semiconductor devices, more particularly to a kind of gallium nitride are brilliant
The preparation method of body pipe.
Background technology
With the increasingly increase to circuit for power conversion demand, with characteristics such as low-power consumption, high speeds
Power device turns into the focus of this area.Gallium nitride (GaN) is that third generation broad stopband is partly led
Body material, because it has big energy gap, high electron saturation velocities, high breakdown electric field, higher thermal
Conductance, corrosion-resistant and radiation resistance, in high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase environment
Under the conditions of have stronger advantage, it is considered to be shortwave opto-electronic device and the high-power device of high voltagehigh frequency rate
The optimal material of part.Therefore, GaN transistor turns into the study hotspot in power device.But, by
In traditional GaN transistor manufacture craft existing defects, the GaN transistor power efficiency produced and generated
It is relatively low, the development of GaN transistor is seriously constrained, therefore, urgent need is improved to traditional handicraft,
To improve the power efficiency of GaN transistor.
The content of the invention
A kind of preparation method of gallium nitride transistor of present invention offer, traditional manufacture craft to optimize,
Improve the power efficiency of gallium nitride transistor.
The preparation method for the gallium nitride transistor that the present invention is provided, including：
Grow GaN cushions, AlGaN potential barrier successively on the surface of a substrate, and in the AlGaN gesture
GaN is grown on the surface of barrier layer and emits layer；
Deposit silicon nitride layer and oxide layer successively are emitted on the surface of layer in the GaN；
Using etching technics to the oxide layer under default first area, silicon nitride layer and the GaN
Emit layer to perform etching, form source-drain electrode contact hole；
Source-drain electrode metal level is deposited, and is pointed to by photoetching process the source on default second area
Drain metal layer performs etching to form source-drain electrode；
The oxide layer and the silicon nitride layer under default 3rd region are carved by etching technics
Erosion, forms positive contact hole, wherein the 3rd region is contained in the second area；
Gate metal is deposited, and the gate metal is performed etching by photoetching process, grid is formed.
The preparation method for the gallium nitride transistor that the present invention is provided, passes through the table in AlGaN potential barrier first
GaN is grown on face successively and emits layer, silicon nitride layer and oxide layer；And to the oxide layer under first area, nitrogen
SiClx layer and GaN emit layer and performed etching, and form source-drain electrode contact hole；Again by being pointed to default
Source-drain electrode metal level on two regions is performed etching, and forms source-drain electrode；And in being formed after source-drain electrode, enter one
Step realizes suppression device surface charge, control device by etching technics and depositing technics formation grid
Current collapse phenomenon, the instable purpose of suppression device, it is possible to increase the power output and power of device
Efficiency.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be right
The accompanying drawing used required in embodiment or description of the prior art is briefly described, it should be apparent that,
Drawings in the following description are only some embodiments of the present invention, for those of ordinary skill in the art
For, without having to pay creative labor, it can also obtain other according to these accompanying drawings
Accompanying drawing.
The flow signal of the preparation method for the gallium nitride transistor that Fig. 1 provides for one embodiment of the invention
Figure；
Fig. 2 is emitted after layer for generation GaN cushions, AlGaN potential barrier and GaN in method shown in Fig. 1
Structural representation；
Fig. 3 is deposit silicon nitride layer and the structural representation after oxide layer in method shown in Fig. 1；
Fig. 4 is the structural representation after formation source-drain electrode contact hole in method shown in Fig. 1；
Fig. 5 is the structural representation after formation source-drain electrode in method shown in Fig. 1；
Fig. 6 is the structural representation after formation grid in method shown in Fig. 1.
Reference：
1- substrates；2-GaN cushions；3-AlGaN barrier layers；
4-GaN emits layer；5- silicon nitride layers；6- oxide layers；
7- source-drain electrode contact holes；8- source-drain electrode metal levels；9- gate metal layers.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the invention, and
The embodiment being not all of.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing
Go out the every other embodiment obtained under the premise of creative work, belong to the scope of protection of the invention.
The term " comprising " and " having " of description and claims of this specification and their times
What is deformed, it is intended that covering is non-exclusive to be included, for example, containing process or the side of series of steps
It is that method is not necessarily limited to those steps clearly listed but may include not list clearly or for these
Process or the intrinsic other steps of method.
The schematic flow sheet of the preparation method for the gallium nitride transistor that Fig. 1 provides for one embodiment of the invention,
As shown in figure 1, the preparation method for the gallium nitride transistor that the present embodiment is provided comprises the following steps：
Step 101, grow GaN cushions 2, AlGaN potential barrier 3 successively on the surface of substrate 1,
And growth GaN emits layer 4 on the surface of the AlGaN potential barrier 3.
Specifically, in the present embodiment, substrate 1 is preferably silicon substrate.Further, Fig. 2 is Fig. 1 institutes
Show that GaN cushions, AlGaN potential barrier and GaN are generated in method emits the structural representation after layer, such as Fig. 2
It is shown, in the present embodiment, layer 4 is emitted by depositing one layer of GaN in AlGaN potential barrier 3, is realized
Suppression device surface charge, control device current collapse phenomenon, the instable purpose of suppression device is carried
The high power output and power efficiency of device.
Step 102, in the GaN emit on the surface of layer 4 deposit silicon nitride layer 5 and oxide layer 6 successively.
Specifically, Fig. 3 is deposit silicon nitride layer and the structural representation after oxide layer in method shown in Fig. 1,
Wherein, structure shown in Fig. 3 can be obtained by the following method：
First, under conditions of low temperature (temperature is less than 300 degrees Celsius), by depositing technics in GaN
Emit one layer of silicon nitride layer 5 of deposit on the surface of layer 4.
Secondly, after deposit obtains silicon nitride layer 5, it is preferred to use the technique of chemical vapor deposition is in nitrogen
Layer of oxide layer 6 is deposited on the surface of SiClx layer 5.Wherein, in the present embodiment, oxide layer 6 preferably may be used
Think reinforced titanium dioxide tetraethyl orthosilicate (PETEOS) oxide layer of plasma-based.
Step 103, using etching technics to the oxide layer 6 under default first area, silicon nitride layer
The 5 and GaN emits layer 4 and performed etching, and forms source-drain electrode contact hole 7.
Specifically, Fig. 4 is the structural representation after formation source-drain electrode contact hole in method shown in Fig. 1, its
In, structure is obtained in the following manner shown in Fig. 4：
First, on the surface of oxide layer 6, troweling is applied on the region beyond default first area
Photoresist, and in smearing after photoresist, the oxide layer 6 under first area is carried out under the stop of photoresist
Etching, untill silicon nitride layer 5 is exposed, through this etching rear oxidation layer 6 under first area
Oxide layer perforate (the first oxide layer perforate) is formed on region.
After the first oxide layer perforate is formed, continue using etching technics to the nitrogen in the first oxide layer perforate
5 and GaN of SiClx layer emits layer 4 and performed etching, and removes after the completion of etching photoresist.Etch herein
Degree is preferred with exposing AlGaN potential barrier 3, will be located at the surface of AlGaN potential barrier 3 and position
Layer 4 is emitted in the silicon nitride layer 5 and GaN in the first oxide layer perforate to etch away.After this etching, i.e.,
Form the source-drain electrode contact hole 7 being located at below first area.
Step 104, deposit source-drain electrode metal level 8, and default second area is pointed to by photoetching process
On the source-drain electrode metal level 8 perform etching to form source-drain electrode.
Specifically, Fig. 5 is the structural representation after formation source-drain electrode in method shown in Fig. 1, wherein, figure
Structure shown in 5 can be obtained by following technique：
One layer of source and drain is deposited using the technique of vapor deposition (preferably electron beam evaporation) on the surface of the component
Pole metal level 8, and it is located at default second area after source-drain electrode metal level 8 on device surface in generating
Photoresist is smeared on region in addition, and to the source-drain electrode metal under second area under the blocking of photoresist
Layer 8 is performed etching, and degree is etched herein and is preferred with exposing the oxide layer 6 being located under second area, will
Positioned at the surface of oxide layer 6, and untill source-drain electrode metal level 8 under the second area is etched away.
Complete, and removed after photoresist in etching, that is, form structure as shown in Figure 5.
Step 105, by etching technics to the oxide layer 6 and the nitrogen under default 3rd region
SiClx layer 5 is performed etching, and positive contact hole is formed, wherein the 3rd region is contained in secondth area
Domain.
Specifically, smearing photoetching on region first on the surface of the component in addition to default 3rd region
Glue, and being performed etching under the stop of photoresist to the oxide layer 6 under the 3rd region, and in exposing GaN
Stop etching when emitting layer 4, now form the second oxide layer perforate being located under the 3rd region.Wherein, originally
In embodiment, the 3rd region is contained in second area.
Further, after the second oxide layer perforate is formed, continue using etching technics to the second oxide layer
Silicon nitride layer 5 in perforate is performed etching, and emits stopping etching after layer in exposing GaN, is allowed to be formed out
Hole size is less than the perforate of the second oxide layer perforate size.
Step 106, deposit gate metal 9, and the gate metal 9 is performed etching by photoetching process,
Form grid.
Specifically, Fig. 6 is the structural representation after formation grid in method shown in Fig. 1, wherein, Fig. 6
Shown structure can be obtained by following technique：
It is preferred that, using the vapor deposition process of electron beam evaporation to depositing one layer of grid on the surface of device
Metal 9.After generation gate metal 9, photoresist is smeared on default 4th region, and in photoetching
The gate metal 9 under the region in addition to the 4th region is performed etching under the blocking of glue, until will be described
Gate metal 9 under region etch it is clean after stop etching, so after, it is to be formed such as to remove photoresist
Structure shown in Fig. 6.
The preparation method for the gallium nitride transistor that the present embodiment is provided, first by AlGaN potential barrier
GaN is grown on surface successively and emits layer, silicon nitride layer and oxide layer；And to the oxide layer under first area,
Silicon nitride layer and GaN emit layer and performed etching, and form source-drain electrode contact hole；It is default by being pointed to again
Metal level on second area is performed etching, and forms source-drain electrode；And in being formed after source-drain electrode, further lead to
Over etching technique and depositing technics formation grid, realize suppression device surface charge, control device electric current
Avalanche phenomenon, the instable purpose of suppression device, it is possible to increase the power output and power efficiency of device.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than right
It is limited；Although the present invention is described in detail with reference to foregoing embodiments, this area it is common
Technical staff should be understood：It can still modify to the technical scheme described in foregoing embodiments,
Or equivalent substitution is carried out to which part or all technical characteristic；And these modifications or replacement, and
The essence of appropriate technical solution is not set to depart from the scope of various embodiments of the present invention technical scheme.
Claims (7)
1. a kind of preparation method of gallium nitride transistor, it is characterised in that including：
Grow GaN cushions, AlGaN potential barrier successively on the surface of a substrate, and in the AlGaN gesture
GaN is grown on the surface of barrier layer and emits layer；
Deposit silicon nitride layer and oxide layer successively are emitted on the surface of layer in the GaN；
Using etching technics to the oxide layer under default first area, silicon nitride layer and the GaN
Emit layer to perform etching, form source-drain electrode contact hole；
Source-drain electrode metal level is deposited, and is pointed to by photoetching process the source on default second area
Drain metal layer performs etching to form source-drain electrode；
The oxide layer and the silicon nitride layer under default 3rd region are carved by etching technics
Erosion, forms positive contact hole, wherein the 3rd region is contained in the second area；
Gate metal is deposited, and the gate metal is performed etching by photoetching process, grid is formed.
2. according to the method described in claim 1, it is characterised in that the oxide layer is PETEOS oxygen
Change layer, it is described to emit on the surface of layer deposit silicon nitride layer and oxide layer successively in the GaN, including：
It is less than in temperature under conditions of 300 degrees Celsius, is emitted in the GaN and the nitrogen is deposited on the surface of layer
SiClx layer；
The PETEOS oxide layers are deposited on the surface of the silicon nitride layer using the technique of vapor deposition.
3. according to the method described in claim 1, it is characterised in that the use etching technics is to first
The oxide layer, silicon nitride layer and the GaN under region emit layer and performed etching, and form source-drain electrode and connect
Contact hole, including：
On the surface of the oxide layer, one layer of photoetching is smeared on the region beyond the first area
Glue；
The oxide layer is performed etching untill the silicon nitride layer is exposed under the blocking of photoresist,
Form the first oxide layer perforate；
Layer is emitted using etching technics to the silicon nitride layer and GaN in the first oxide layer perforate to carve
Erosion, untill the surface of the AlGaN potential barrier is exposed, forms source-drain electrode contact hole, and remove light
Photoresist.
4. method according to claim 3, it is characterised in that the deposit source-drain electrode metal level,
And the source-drain electrode metal level being pointed to by photoetching process on second area performs etching to form source and drain
Pole, including：
One layer of source-drain electrode metal level is deposited on the surface of transistor by electron beam evaporation process；
One layer of photoresist, and blocking in the photoresist are smeared on the region beyond the second area
Under the source-drain electrode metal level on the second area is performed etching, until exposing the surface of the oxide layer
Untill, source-drain electrode is formed, photoresist is removed.
5. method according to claim 4, it is characterised in that it is described by etching technics to the 3rd
The oxide layer and the silicon nitride layer under region are performed etching, and form positive contact hole, including：
Photoresist is smeared on region on the surface of transistor in addition to the 3rd region, and described
The oxide layer is performed etching under the blocking of photoresist, the second oxide layer perforate is formed；
The silicon nitride layer in the second oxide layer perforate is performed etching using etching technics, until exposing
Untill the GaN emits layer, the perforate that perforate size is less than the second oxide layer perforate size is formed.
6. method according to claim 5, it is characterised in that the deposit gate metal, and lead to
Cross photoetching process to perform etching the gate metal, form grid, including：
One layer of gate metal is deposited on the surface of transistor by electron beam evaporation process；
One layer of photoresist is smeared on the 4th region, wherein, the 4th region is contained in secondth area
Domain, includes the 3rd region；
To the gate metal under the region in addition to the 4th region under the blocking of the photoresist
Perform etching, form source-drain electrode, remove photoresist.
7. according to the method described in claim 1, it is characterised in that the substrate is silicon substrate.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115425041A (en) * | 2022-09-26 | 2022-12-02 | 山西国惠光电科技有限公司 | Preparation method of InGaAs infrared focal plane detector for inhibiting electric crosstalk |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1748320A (en) * | 2002-12-16 | 2006-03-15 | 日本电气株式会社 | Field-effect transistor |
| CN101211969A (en) * | 2006-12-28 | 2008-07-02 | 富士通株式会社 | High speed high power nitride semiconductor device and manufacturing method thereof |
| CN104485357A (en) * | 2014-12-17 | 2015-04-01 | 中国科学院半导体研究所 | HEMT with gallium nitride high-resistivity layer and preparation method |
-
2016
- 2016-03-25 CN CN201610178295.0A patent/CN107230634A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1748320A (en) * | 2002-12-16 | 2006-03-15 | 日本电气株式会社 | Field-effect transistor |
| CN101211969A (en) * | 2006-12-28 | 2008-07-02 | 富士通株式会社 | High speed high power nitride semiconductor device and manufacturing method thereof |
| CN104485357A (en) * | 2014-12-17 | 2015-04-01 | 中国科学院半导体研究所 | HEMT with gallium nitride high-resistivity layer and preparation method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115425041A (en) * | 2022-09-26 | 2022-12-02 | 山西国惠光电科技有限公司 | Preparation method of InGaAs infrared focal plane detector for inhibiting electric crosstalk |
| CN115425041B (en) * | 2022-09-26 | 2024-06-11 | 山西国惠光电科技有限公司 | Preparation method of InGaAs infrared focal plane detector for inhibiting electrical crosstalk |
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