CN107230621A - The manufacture method of gallium nitride transistor - Google Patents
The manufacture method of gallium nitride transistor Download PDFInfo
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- CN107230621A CN107230621A CN201610178146.4A CN201610178146A CN107230621A CN 107230621 A CN107230621 A CN 107230621A CN 201610178146 A CN201610178146 A CN 201610178146A CN 107230621 A CN107230621 A CN 107230621A
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- gallium nitride
- oxide layer
- contact hole
- nitride
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 111
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 95
- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000002161 passivation Methods 0.000 claims abstract description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 25
- 238000000151 deposition Methods 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 150000004767 nitrides Chemical class 0.000 claims abstract description 15
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 14
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 41
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 13
- 239000010936 titanium Substances 0.000 claims description 13
- 229910052719 titanium Inorganic materials 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 239000004411 aluminium Substances 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 230000012010 growth Effects 0.000 claims description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 238000010894 electron beam technology Methods 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 6
- 239000012528 membrane Substances 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000034655 secondary growth Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a kind of manufacture method of gallium nitride transistor, this method includes：Growing aluminum nitride layer, nitride buffer layer, aluminum gallium nitride barrier layer and gallium nitride cap layers successively on a silicon substrate；Silicon nitride passivation and oxide layer are sequentially depositing in gallium nitride cap layers；Manufacture source electrode and the drain electrode of gallium nitride transistor；Manufacture the grid of gallium nitride transistor, it is suppressed that substrate leakage, dead resistance and parasitic capacitance are reduced, so as to reduce the power consumption of device.
Description
Technical field
The present embodiments relate to semiconductor device processing technology field, more particularly to a kind of gallium nitride
The manufacture method of pipe.
Background technology
With the increasingly increase of efficiently complete circuit for power conversion and system requirements, with low-power consumption and height
The power device of fast characteristic has attracted increasing concern.Because gallium nitride has wider energy gap,
High electronics saturation drift velocity, higher disruptive field intensity, good heat endurance, corrosion-resistant and radioresistance
Performance, so gallium nitride is the new wide bandgap compound semiconductor material of extensive concern in the world, its
There is stronger advantage under high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase environmental condition.It is excellent by its
Good material property, gallium nitride transistor is widely used.
But because in the manufacturing process of gallium nitride transistor, the material between substrate and nitride buffer layer is not
Matching, electric current flows through from substrate when causing the device to work, and causes substrate leakage, in substrate leakage,
Make to be formed very big dead resistance and parasitic capacitance between substrate and pin, the power consumption in turn resulting in device increases
Greatly.
The content of the invention
The embodiment of the present invention provides a kind of manufacture method of gallium nitride transistor, it is suppressed that substrate leakage, subtracts
Dead resistance and parasitic capacitance are lacked, so as to reduce the power consumption of device.
The embodiment of the present invention provides a kind of manufacture method of gallium nitride transistor, including：
Growing aluminum nitride layer, nitride buffer layer, aluminum gallium nitride barrier layer and gallium nitride successively on a silicon substrate
Cap layers；
Silicon nitride passivation and oxide layer are sequentially depositing in the gallium nitride cap layers；
Manufacture source electrode and the drain electrode of the gallium nitride transistor；
Manufacture the grid of the gallium nitride transistor.
Further, method as described above, growing aluminum nitride layer, the nitridation successively on a silicon substrate
Gallium cushion, aluminum gallium nitride barrier layer and gallium nitride cap layers are specially：
Using technique growing aluminum nitride layer, nitride buffer layer, the aluminium successively on a silicon substrate of epitaxial growth
Gallium nitrogen barrier layer and gallium nitride cap layers.
Further, method as described above, it is described to be sequentially depositing silicon nitride in the gallium nitride cap layers
Passivation layer and oxide layer are specially：
Using the technique of chemical vapor deposition be sequentially depositing in the gallium nitride cap layers silicon nitride passivation and
Oxide layer.
Further, method as described above, the source electrode of the manufacture gallium nitride transistor and drain electrode
Specifically include：
The oxide layer of left and right sides subregion is etched, the first oxide layer perforate and the second oxidation is formed respectively
Layer perforate, the nitridation is etched in the first oxide layer perforate and the second oxide layer perforate respectively
Silicon passivation layer and the gallium nitride cap layers, form source contact openings and drain contact hole；
In the source contact openings, in the drain contact hole, above the source contact openings, it is described
Drain contact hole top and the oxide layer sedimentary origin drain metal layer；
Metal in the source-drain electrode metal level is evaporated using electron beam technology；
Photoetching is carried out to the source-drain electrode metal level of the oxide layer, etching forms source electrode and drain electrode.
Further, method as described above, the grid of the manufacture gallium nitride transistor is specifically wrapped
Include：
The subregional oxide layer of pars intermedia is etched, the 3rd oxide layer perforate is formed, in the 3rd oxide layer
The etching silicon nitride passivation in perforate, forms gate contact hole；
In the gate contact hole, above the gate contact hole, between the source electrode and the drain electrode
Oxide layer deposition gate metal layer；
Metal in the gate metal layer is evaporated using electron beam technology；
Gate metal layer to the oxide layer carries out photoetching, and etching forms grid.
Further, method as described above, the oxide layer is PETEOS oxide layers.
Further, method as described above, it is described in the source contact openings, the drain contact
In hole, above the source contact openings, above the drain contact hole and the oxide layer sedimentary origin
Drain metal layer is specially：
In the source contact openings, in the drain contact hole, above the source contact openings, it is described
Drain contact hole top and the oxide layer are sequentially depositing titanium layer, aluminium using magnetron sputtering membrane process
Layer, titanium layer and titanium nitride layer, to form source-drain electrode metal level.
Further, method as described above, it is described in the gate contact hole, the gate contact
Oxide layer between hole top, the source electrode and the drain electrode deposits gate metal layer：
In the gate contact hole, above the gate contact hole, between the source electrode and the drain electrode
Oxide layer titanium nitride layer, titanium layer, aluminium lamination, titanium layer are sequentially depositing using magnetron sputtering membrane process
And titanium nitride layer, to form gate metal layer.
The embodiment of the present invention provides a kind of manufacture method of gallium nitride transistor, by a silicon substrate successively
Growing aluminum nitride layer, nitride buffer layer, aluminum gallium nitride barrier layer and gallium nitride cap layers；In gallium nitride cap layers
On be sequentially depositing silicon nitride passivation and oxide layer；Manufacture source electrode and the drain electrode of gallium nitride transistor；Manufacture
The grid of gallium nitride transistor, it is suppressed that substrate leakage, reduces dead resistance and parasitic capacitance, so that
Reduce the power consumption of device.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to reality
The accompanying drawing used required for applying in example or description of the prior art is briefly described, it should be apparent that, under
Accompanying drawing in the description of face is some embodiments of the present invention, for those of ordinary skill in the art,
On the premise of not paying creative labor, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the flow chart of the manufacture method embodiment one of gallium nitride transistor of the present invention；
Fig. 2 be the embodiment of the present invention one provide gallium nitride transistor manufacture method on a silicon substrate according to
Structural representation after secondary growth aln layer, nitride buffer layer, aluminum gallium nitride barrier layer and gallium nitride cap layers
Figure；
In gallium nitride cap layers in the manufacture method for the gallium nitride transistor that Fig. 3 provides for the embodiment of the present invention one
On be sequentially depositing the structural representation after silicon nitride passivation and oxide layer；
Manufacture gallium nitride is brilliant in the manufacture method for the gallium nitride transistor that Fig. 4 provides for the embodiment of the present invention one
The source electrode of body pipe and the flow chart of drain electrode；
Source contact is formed in the manufacture method for the gallium nitride transistor that Fig. 5 provides for the embodiment of the present invention one
Structural representation behind hole and drain contact hole；
In manufacture gallium nitride in the manufacture method for the gallium nitride transistor that Fig. 6 provides for the embodiment of the present invention one
Structural representation after the source electrode of transistor and drain electrode；
Manufacture gallium nitride is brilliant in the manufacture method for the gallium nitride transistor that Fig. 7 provides for the embodiment of the present invention one
The flow chart of the grid of body pipe；
Gate contact is formed in the manufacture method for the gallium nitride transistor that Fig. 8 provides for the embodiment of the present invention one
Structural representation behind hole；
In manufacture gallium nitride in the manufacture method for the gallium nitride transistor that Fig. 9 provides for the embodiment of the present invention one
Structural representation after transistor gate.
Reference：
1- silicon substrate 2- aln layer 3- nitride buffer layers
4- aluminum gallium nitride barrier layer 5- gallium nitride cap layers 6- silicon nitride passivations
7- oxide layer 8- source contact openings 9- drain contact holes
10- source electrodes 11- drain electrode 12- gate contacts hole
13- grids
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with this hair
Accompanying drawing in bright embodiment, the technical scheme in the embodiment of the present invention is clearly and completely described,
Obviously, described embodiment is a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained under the premise of creative work is not made
The every other embodiment obtained, belongs to the scope of protection of the invention.
Fig. 1 is the flow chart of the manufacture method embodiment one of gallium nitride transistor of the present invention, as shown in figure 1,
The manufacture method for the gallium nitride transistor that the present embodiment is provided comprises the following steps.
Step 101, on silicon substrate 1 successively growing aluminum nitride layer 2, nitride buffer layer 3, aluminum gallium nitride
Barrier layer 4 and gallium nitride cap layers 5.
Further, in the present embodiment, growing aluminum nitride layer 2, gallium nitride delay successively on silicon substrate 1
Rushing layer 3, aluminum gallium nitride barrier layer 4 and gallium nitride cap layers 5 is specially：
Using the technique of epitaxial growth on silicon substrate 1 successively growing aluminum nitride layer 2, nitride buffer layer 3,
Aluminum gallium nitride barrier layer 4 and gallium nitride cap layers 5.
Specifically, in silicon in the manufacture method for the gallium nitride transistor that Fig. 2 provides for the embodiment of the present invention one
On substrate successively after growing aluminum nitride layer, nitride buffer layer, aluminum gallium nitride barrier layer and gallium nitride cap layers
Structural representation, as shown in Fig. 2 using epitaxial growth technology growing aluminum nitride on silicon substrate 1 first
Layer 2, secondly uses epitaxial growth technology growing gallium nitride cushion 3 on aln layer 2, uses again
Epitaxial growth technology grows aluminum gallium nitride barrier layer 4 on nitride buffer layer 3, finally using epitaxial growth
Technique growing gallium nitride cap layers 5 in aluminum gallium nitride barrier layer 4.
Step 102, silicon nitride passivation 6 and oxide layer 7 are sequentially depositing in gallium nitride cap layers 5.
Further, in the present embodiment, be sequentially depositing in gallium nitride cap layers 5 silicon nitride passivation 6 and
Oxide layer 7 is specially：
Using the technique of chemical vapor deposition be sequentially depositing in gallium nitride cap layers 5 silicon nitride passivation 6 and
Oxide layer 7.
Specifically, in nitrogen in the manufacture method for the gallium nitride transistor that Fig. 3 provides for the embodiment of the present invention one
Change and be sequentially depositing the structural representation after silicon nitride passivation and oxide layer in gallium cap layers, as shown in figure 3,
First using chemical vapor deposition technique in gallium nitride cap layers 5 deposited silicon nitride passivation layers 6, then
Using the technique of chemical vapor deposition on silicon nitride passivation 6 deposited oxide layer 7.
Further, in the present embodiment, oxide layer 7 can be PETEOS oxide layers.
Step 103, the source electrode 10 of manufacture gallium nitride transistor and drain electrode 11.
Further, made in the manufacture method for the gallium nitride transistor that Fig. 4 provides for the embodiment of the present invention one
The flow chart of the source electrode and drain electrode of gallium nitride transistor is made, as shown in figure 4, in the present embodiment, manufacturing nitrogen
The source electrode 10 and drain electrode 11 for changing gallium transistor particularly may be divided into following steps progress.
Step 103a, etches the oxide layer of left and right sides subregion, forms the first oxide layer perforate respectively
With the second oxide layer perforate, etch silicon nitride is distinguished in the first oxide layer perforate and the second oxide layer perforate
Passivation layer and gallium nitride cap layers, form source contact openings 8 and drain contact hole 9.
Specifically, formed in the manufacture method for the gallium nitride transistor that Fig. 5 provides for the embodiment of the present invention one
Structural representation after source contact openings and drain contact hole, as shown in figure 5, in the present embodiment, by oxygen
It is three regions, respectively left field to change 4 points of layer, right side area and intermediate region.Dry method can be used
Etching technics etches away the oxide layer 7 of left and right sides subregion, and the first oxygen is formed in left part region
Change layer perforate, the second oxide layer perforate is formed in right part region, in the first oxide layer perforate and second
Difference etch silicon nitride passivation layer 6 and gallium nitride cap layers 5 in oxide layer perforate, the first oxide layer perforate
Size can be equal sized with the second oxide layer perforate, the silicon nitride passivation 6 and gallium nitride etched away
Cap layers 5 are located at the underface of the first oxide layer perforate and the second oxide layer perforate, i.e. the first oxide layer perforate
And second oxide layer perforate surrounding size and the silicon nitride passivation 6 that etches away and gallium nitride cap layers 5
Surrounding is equal sized.
Step 103b, in source contact openings 8, in drain contact hole 9, above source contact openings 8,
The top of drain contact hole 9 and the disposed thereon source-drain electrode metal level of oxide layer 7.
Further, in the present embodiment, in the source contact openings 8, in drain contact hole 9, source electrode connects
The top of contact hole 8, the top of drain contact hole 9 and the disposed thereon source-drain electrode metal level of oxide layer 7 are specially：
In source contact openings 8, in drain contact hole 9, above source contact openings 8, drain contact hole
9 tops and the top of oxide layer 7 are sequentially depositing titanium layer, aluminium lamination, titanium layer using magnetron sputtering membrane process
And titanium nitride layer, to form source-drain electrode metal level.
Step 103c, using the metal in electron beam technology evaporation source drain metal layer.
Step 103d, carries out photoetching, etching forms source electrode 10 to the source-drain electrode metal level of oxide layer
And drain electrode 11.
Specifically, in system in the manufacture method for the gallium nitride transistor that Fig. 6 provides for the embodiment of the present invention one
Make gallium nitride transistor source electrode and drain electrode after structural representation, as shown in fig. 6, in oxide layer 7
The source-drain electrode metal level of side carries out photoetching, and etching retains near source contact openings 8 and drain contact hole 9
Source-drain electrode metal level, respectively formed source electrode 10 and drain electrode 11.
In the present embodiment, the source-drain electrode metal level of the top of oxide layer 7 is carried out the process of photoetching include gluing,
Exposed and developed process.
Step 104, the grid 13 of gallium nitride transistor is manufactured.
Further, made in the manufacture method for the gallium nitride transistor that Fig. 7 provides for the embodiment of the present invention one
The flow chart of the grid of gallium nitride transistor is made, as shown in fig. 7, in the present embodiment, manufacture gallium nitride is brilliant
The grid of body pipe specifically includes following steps.
Step 104a, etches the subregional oxide layer of pars intermedia, the 3rd oxide layer perforate is formed, the 3rd
Etch silicon nitride passivation layer in oxide layer perforate, forms gate contact hole 12.
Specifically, formed in the manufacture method for the gallium nitride transistor that Fig. 8 provides for the embodiment of the present invention one
Structural representation behind gate contact hole, as shown in figure 8, in the present embodiment, first using dry etching
Technique etches away the subregional oxide layer of pars intermedia, forms the 3rd oxide layer perforate, is opened in the 3rd oxide layer
Continue to etch away silicon nitride passivation using dry etch process in hole, form gate contact hole 12.
Wherein, the silicon nitride passivation surrounding size etched away using dry etch process is less than the 3rd oxidation
The size of layer perforate.
Step 104b, in the gate contact hole 12, the top of gate contact hole 12, source electrode 10 and drain electrode
Oxide layer deposition gate metal layer between 11.
Further, in the present embodiment, in gate contact hole 12, above gate contact hole 12, source
Oxide layer between pole 10 and drain electrode 11 deposits gate metal layer：
In the gate contact hole 12, the top of gate contact hole 12, the oxygen between source electrode 10 and drain electrode 11
Change uses magnetron sputtering membrane process to be sequentially depositing titanium nitride layer, titanium layer, aluminium lamination, titanium layer and nitrogen above layer
Change titanium layer, to form gate metal layer.
Step 104c, the metal in gate metal layer is evaporated using electron beam technology.
Step 104d, the gate metal layer to the top of oxide layer 7 carries out photoetching, and etching forms grid 13.
Specifically, Fig. 9 be the embodiment of the present invention one provide gallium nitride transistor manufacture method in
The structural representation after gallium nitride tube grid is manufactured, as shown in figure 9, in the present embodiment, to oxygen
The gate metal layer for changing the top of layer 7 carries out photoetching, and etching retains the grid near gate contact hole 12
Metal level, forms grid.
In the present embodiment, after the source electrode, drain and gate in manufacture gallium nitride transistor, in addition to nitrogen
Change other the follow-up operations of gallium transistor, these operations are same as the prior art, and this is no longer going to repeat them.
The manufacture method for the gallium nitride transistor that the present embodiment is provided, including：Given birth to successively on silicon substrate 1
Long aln layer 2, nitride buffer layer 3, aluminum gallium nitride barrier layer 4 and gallium nitride cap layers 5；In gallium nitride
Silicon nitride passivation 6 and oxide layer 7 are sequentially depositing in cap layers 5；Manufacture the source electrode 10 of gallium nitride transistor
With drain electrode 11；The grid 13 of gallium nitride transistor is manufactured, due to grown aln layer on silicon substrate 1
2, aluminium nitride is a kind of dielectric substance, can form good in the contact surface of silicon substrate and nitride buffer layer
Good interface, makes tangent line few, it is suppressed that substrate leakage, in the case where suppressing substrate leakage, reduces
The dead resistance and parasitic capacitance formed between the drain electrode of device and silicon substrate, so as to reduce the work(of device
Consumption.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than right
It is limited；Although the present invention is described in detail with reference to foregoing embodiments, this area it is common
Technical staff should be understood：It can still be repaiied to the technical scheme described in foregoing embodiments
Change, or equivalent substitution is carried out to which part or all technical characteristic；And these are changed or replaced
Change, the essence of appropriate technical solution is departed from the scope of various embodiments of the present invention technical scheme.
Claims (8)
1. a kind of manufacture method of gallium nitride transistor, it is characterised in that including：
Growing aluminum nitride layer, nitride buffer layer, aluminum gallium nitride barrier layer and gallium nitride successively on a silicon substrate
Cap layers；
Silicon nitride passivation and oxide layer are sequentially depositing in the gallium nitride cap layers；
Manufacture source electrode and the drain electrode of the gallium nitride transistor；
Manufacture the grid of the gallium nitride transistor.
2. according to the method described in claim 1, it is characterised in that described to give birth to successively on a silicon substrate
Long aln layer, nitride buffer layer, aluminum gallium nitride barrier layer and gallium nitride cap layers are specially：
Using technique growing aluminum nitride layer, nitride buffer layer, the aluminium successively on a silicon substrate of epitaxial growth
Gallium nitrogen barrier layer and gallium nitride cap layers.
3. method according to claim 1 or 2, it is characterised in that described in the gallium nitride cap
Silicon nitride passivation is sequentially depositing on layer and oxide layer is specially：
Using the technique of chemical vapor deposition be sequentially depositing in the gallium nitride cap layers silicon nitride passivation and
Oxide layer.
4. method according to claim 3, it is characterised in that the manufacture gallium nitride is brilliant
The source electrode of body pipe and drain electrode are specifically included：
The oxide layer of left and right sides subregion is etched, the first oxide layer perforate and the second oxidation is formed respectively
Layer perforate, the nitridation is etched in the first oxide layer perforate and the second oxide layer perforate respectively
Silicon passivation layer and the gallium nitride cap layers, form source contact openings and drain contact hole；
In the source contact openings, in the drain contact hole, above the source contact openings, it is described
Drain contact hole top and the oxide layer sedimentary origin drain metal layer；
Metal in the source-drain electrode metal level is evaporated using electron beam technology；
Photoetching is carried out to the source-drain electrode metal level of the oxide layer, etching forms source electrode and drain electrode.
5. method according to claim 4, it is characterised in that the manufacture gallium nitride is brilliant
The grid of body pipe is specifically included：
The subregional oxide layer of pars intermedia is etched, the 3rd oxide layer perforate is formed, in the 3rd oxide layer
The etching silicon nitride passivation in perforate, forms gate contact hole；
In the gate contact hole, above the gate contact hole, between the source electrode and the drain electrode
Oxide layer deposition gate metal layer；
Metal in the gate metal layer is evaporated using electron beam technology；
Gate metal layer to the oxide layer carries out photoetching, and etching forms grid.
6. method according to claim 5, it is characterised in that the oxide layer is PETEOS
Oxide layer.
7. method according to claim 6, it is characterised in that described in the source contact openings
In interior, described drain contact hole, above the source contact openings, it is above the drain contact hole and described
Oxide layer sedimentary origin drain metal layer is specially：
In the source contact openings, in the drain contact hole, above the source contact openings, it is described
Drain contact hole top and the oxide layer are sequentially depositing titanium layer, aluminium using magnetron sputtering membrane process
Layer, titanium layer and titanium nitride layer, to form source-drain electrode metal level.
8. method according to claim 7, it is characterised in that described in the gate contact hole
Oxide layer deposition grid between interior, described gate contact hole top, the source electrode and the drain electrode
Metal level is specially：
In the gate contact hole, above the gate contact hole, between the source electrode and the drain electrode
Oxide layer titanium nitride layer, titanium layer, aluminium lamination, titanium layer are sequentially depositing using magnetron sputtering membrane process
And titanium nitride layer, to form gate metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610178146.4A CN107230621A (en) | 2016-03-25 | 2016-03-25 | The manufacture method of gallium nitride transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610178146.4A CN107230621A (en) | 2016-03-25 | 2016-03-25 | The manufacture method of gallium nitride transistor |
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| Publication Number | Publication Date |
|---|---|
| CN107230621A true CN107230621A (en) | 2017-10-03 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108695157A (en) * | 2018-04-16 | 2018-10-23 | 厦门市三安集成电路有限公司 | A kind of gallium nitride transistor and production method of the composite passivated medium of air gap type |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100171150A1 (en) * | 2006-01-17 | 2010-07-08 | Cree, Inc. | Methods of fabricating transistors including dielectrically-supported gate electrodes and related devices |
| CN105322009A (en) * | 2015-11-09 | 2016-02-10 | 江西省昌大光电科技有限公司 | Gallium nitride based high electronic mobility transistor epitaxial structure and manufacturing method therefor |
| CN105355659A (en) * | 2015-11-06 | 2016-02-24 | 西安电子科技大学 | Trench-gate AlGaN/GaN HEMT device structure and manufacturing method |
-
2016
- 2016-03-25 CN CN201610178146.4A patent/CN107230621A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100171150A1 (en) * | 2006-01-17 | 2010-07-08 | Cree, Inc. | Methods of fabricating transistors including dielectrically-supported gate electrodes and related devices |
| CN105355659A (en) * | 2015-11-06 | 2016-02-24 | 西安电子科技大学 | Trench-gate AlGaN/GaN HEMT device structure and manufacturing method |
| CN105322009A (en) * | 2015-11-09 | 2016-02-10 | 江西省昌大光电科技有限公司 | Gallium nitride based high electronic mobility transistor epitaxial structure and manufacturing method therefor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108695157A (en) * | 2018-04-16 | 2018-10-23 | 厦门市三安集成电路有限公司 | A kind of gallium nitride transistor and production method of the composite passivated medium of air gap type |
| WO2019201002A1 (en) * | 2018-04-16 | 2019-10-24 | 厦门市三安集成电路有限公司 | Gallium nitride transistor with gap-type composite passivation medium and manufacturing method therefor |
| CN108695157B (en) * | 2018-04-16 | 2020-09-04 | 厦门市三安集成电路有限公司 | Gallium nitride transistor with gap type composite passivation medium and manufacturing method |
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