CN107230619A - The preparation method of enhancement type gallium nitride transistor - Google Patents
The preparation method of enhancement type gallium nitride transistor Download PDFInfo
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- CN107230619A CN107230619A CN201610178136.0A CN201610178136A CN107230619A CN 107230619 A CN107230619 A CN 107230619A CN 201610178136 A CN201610178136 A CN 201610178136A CN 107230619 A CN107230619 A CN 107230619A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 61
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 46
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 49
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 18
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 18
- 239000011574 phosphorus Substances 0.000 claims abstract description 18
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 15
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 12
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 12
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 12
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004411 aluminium Substances 0.000 claims abstract description 9
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 5
- 239000000956 alloy Substances 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000004026 adhesive bonding Methods 0.000 claims description 2
- 238000011161 development Methods 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
-
- H01L29/66462—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H01L29/0623—
-
- H01L29/42372—
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The embodiment of the present invention provides a kind of preparation method of enhancement type gallium nitride transistor.This method includes：Grow the GaN dielectric layers, aluminium gallium nitride alloy AlGaN dielectric layers and silicon nitride Si3N4 dielectric layers of phosphorus doping successively on the surface of silicon substrate；Si3N4 dielectric layers are performed etching；In the AlGaN dielectric layers exposed and remaining Si3N4 dielectric layers upper surface deposited metal layer；Dry etching is carried out downwards along the presumptive area on the surface of the Si3N4 dielectric layers exposed；SiO2 dielectric layers are deposited in gate contact hole and are used as gate medium.The GaN dielectric layers of phosphorus doping on the surface of silicon substrate of the embodiment of the present invention, reduce the surface field of enhancement type gallium nitride transistor, improve pressure-resistant, in addition, the grid doping of enhancement type gallium nitride transistor has phosphorus, have the compound of electronics and hole so that conducting resistance is reduced, and realizes the smaller and pressure-resistant larger technological requirement of conducting resistance of gallium nitride transistor.
Description
Technical field
The present embodiments relate to semiconductor applications, more particularly to a kind of system of enhancement type gallium nitride transistor
Make method.
Background technology
With the increasingly increase of efficiently complete circuit for power conversion and system requirements, with low-power consumption and height
The power device of fast characteristic has attracted many concerns recently.Gallium nitride GaN is third generation wide bandgap semiconductor
Material, because it has big energy gap (3.4eV), high electron saturation velocities (2e7cm/s), height
Breakdown electric field (1e10--3e10V/cm), higher heat-conductivity, corrosion-resistant and radiation resistance, high pressure,
There is stronger advantage, it is considered to be research is short under high frequency, high temperature, high-power and Flouride-resistani acid phesphatase environmental condition
The optimal material of wavelength optoelectronic and high voltagehigh frequency rate high power device.
At present, aluminium gallium nitride alloy/GaN high electron mobility transistor (AlGaN/GaN High Electron
Mobility Transistor, abbreviation AlGaN/GaN HEMT) it is study hotspot in power device,
Because AlGaN/GaN suppresses to form high concentration, the two-dimensional electron gas (2DEG) of high mobility at knot,
Hetero-junctions has good adjustment effect to 2DEG simultaneously.
The conducting resistance of gallium nitride transistor is bigger, and its is pressure-resistant also bigger, but generally those skilled in the art
Wish that the conducting resistance of gallium nitride transistor is smaller, it is as far as possible big that its is pressure-resistant, and existing manufacture craft is difficult
The conducting resistance for meeting gallium nitride transistor is smaller and pressure-resistant larger.
The content of the invention
The embodiment of the present invention provides a kind of preparation method of enhancement type gallium nitride transistor, with the conducting of reduction
Resistance.
The one side of the embodiment of the present invention is to provide a kind of preparation method of enhancement type gallium nitride transistor,
Including：
The GaN dielectric layers of phosphorus doping, aluminium gallium nitride alloy AlGaN is grown successively on the surface of silicon substrate to be situated between
Matter layer and silicon nitride Si3N4 dielectric layers；
The first area and second area of the Si3N4 dielectric layers are performed etching, to expose described first
Region and the second area distinguish corresponding AlGaN dielectric layers；
In the AlGaN dielectric layers and the remaining Si3N4 dielectric layers upper surface deposited metal exposed
Layer；
Photoetching, etching are carried out to the metal level, is connect with exposing the Si3N4 dielectric layers and forming ohm
Touched electrode；
Dry etching is carried out downwards along the presumptive area on the surface of the Si3N4 dielectric layers exposed, directly
To the AlGaN dielectric layers of etch away sections, the Si3N4 dielectric layers being etched away and part institute
State AlGaN dielectric layers formation gate contact hole；
Silica SiO2 dielectric layers are deposited in the gate contact hole as gate medium, and the grid to be situated between
The surface of matter is less than surface where the aperture in the gate contact hole；
Adulterated in the upper surface deposit polycrystalline silicon PolySi of the SiO2 dielectric layers, and in the PolySi
Phosphorus formation grid, to complete the making of the enhancement type gallium nitride transistor.
The preparation method of enhancement type gallium nitride transistor provided in an embodiment of the present invention, on the surface of silicon substrate
The GaN dielectric layers of upper phosphorus doping, reduce the surface field of enhancement type gallium nitride transistor, improve increasing
Strong type gallium nitride transistor it is pressure-resistant, in addition, the grid doping of enhancement type gallium nitride transistor has phosphorus, meeting
There is the compound of electronics and hole so that conducting resistance is reduced, and realizes the conducting resistance of gallium nitride transistor
Smaller and pressure-resistant larger technological requirement.
Brief description of the drawings
Fig. 1 is the preparation method flow chart of enhancement type gallium nitride transistor provided in an embodiment of the present invention；
Fig. 2 illustrates to perform the section of enhancement type gallium nitride transistor in manufacturing process of the embodiment of the present invention
Figure；
Fig. 3 illustrates to perform the section of enhancement type gallium nitride transistor in manufacturing process of the embodiment of the present invention
Figure；
Fig. 4 illustrates to perform the section of enhancement type gallium nitride transistor in manufacturing process of the embodiment of the present invention
Figure；
Fig. 5 illustrates to perform the section of enhancement type gallium nitride transistor in manufacturing process of the embodiment of the present invention
Figure；
Fig. 6 illustrates to perform the section of enhancement type gallium nitride transistor in manufacturing process of the embodiment of the present invention
Figure；
Fig. 7 illustrates to perform the section of enhancement type gallium nitride transistor in manufacturing process of the embodiment of the present invention
Figure；
Fig. 8 illustrates to perform the section of enhancement type gallium nitride transistor in manufacturing process of the embodiment of the present invention
Figure.
Embodiment
Fig. 1 is the preparation method flow chart of enhancement type gallium nitride transistor provided in an embodiment of the present invention.For
To the method in the present embodiment understand the description of system, Fig. 2-Fig. 8 is performs the embodiment of the present invention
The diagrammatic cross-section of enhancement type gallium nitride transistor in procedure, as shown in figure 1, methods described includes：
Step S101, GaN dielectric layers, the aluminium gallium nitride alloy for growing on the surface of silicon substrate phosphorus doping successively
AlGaN dielectric layers and silicon nitride Si3N4 dielectric layers；
As shown in Fig. 2 growing GaN dielectric layers, the aluminium nitride of phosphorus doping successively on the surface of silicon substrate
Gallium AlGaN dielectric layers and silicon nitride Si3N4 dielectric layers, perform the diagrammatic cross-section after step S101
As shown in Fig. 2 wherein, silicon substrate is represented with 20, the GaN dielectric layers of phosphorus doping are represented with 21, AlGaN
Dielectric layer represents that silicon nitride Si3N4 dielectric layers are represented with 23 with 22.
Step S102, the first area to the Si3N4 dielectric layers and second area are performed etching, to reveal
Go out the first area and the second area distinguishes corresponding AlGaN dielectric layers；
On the basis of Fig. 2, first area and second area to Si3N4 dielectric layers carry out dry etching,
The Si3N4 dielectric layers in first area and second area are etched away by dry etching, and etch away
Source contact hole is formed after Si3N4 dielectric layers in one region, the Si3N4 etched away in second area is situated between
Drain terminal contact hole is formed after matter layer.
The diagrammatic cross-section after step S102 is performed as shown in figure 3, wherein, etching away in first area
Si3N4 dielectric layers after the source contact hole that is formed represented with 24, etch away the Si3N4 in second area
The drain terminal contact hole formed after dielectric layer is represented with 25.
Step S103, in the AlGaN dielectric layers and the remaining Si3N4 dielectric layers upper table exposed
Face deposited metal layer；
Specifically, in the AlGaN dielectric layers 22 and the remaining Si3N4 dielectric layers 23 exposed
Upper surface deposited metal layer, performs the diagrammatic cross-section after step S103 as shown in figure 4, wherein, sinking
Long-pending metal level is represented with 26.
In embodiments of the present invention, it is described in the AlGaN dielectric layers exposed and remaining described
Before the deposited metal layer of Si3N4 dielectric layers upper surface, in addition to：The AlGaN exposed is situated between
Matter layer and the remaining Si3N4 dielectric layers upper surface are cleaned.
Specifically, in the AlGaN dielectric layers and the remaining Si3N4 dielectric layers upper surface that expose
Before deposited metal layer, using DHF+SC1+SC2 methods to the AlGaN dielectric layers that expose and surplus
The remaining Si3N4 dielectric layers upper surface is cleaned, wherein, DHF expressions are cleaned with dilute hydrogen fluoride acid,
SC1 represents standardization first step cleaning, and SC2 represents standardization second step cleaning, the time of three cleanings
It is 60s.
It is preferred that, the metal level is Ohmic electrode metal, and the Ohmic electrode metal includes two layer medium,
The two layer medium is followed successively by titanium and aluminium according to order from top to bottom.
Specifically, using magnetron sputtering membrane process deposited metal layer, metal level is Ohmic electrode metal,
Ohmic electrode metal includes two layers, and first layer is titanium, and the second layer is aluminium, and the deposition of first layer titanium is
The deposition of second layer aluminium isAnd order and enhancement type gallium nitride from first layer to the second layer
Sequence consensus in the diagrammatic cross-section of transistor from top to bottom.
Step S104, to the metal level carry out photoetching, etching, to expose the Si3N4 dielectric layers simultaneously
Form Ohm contact electrode；
A part to metal level 26 carries out photoetching, etching, to expose the Si3N4 dielectric layers, does not carve
The metal level 26 of eating away respectively constitutes Ohm contact electrode, and the Ohm contact electrode includes source electrode and drain electrode,
The diagrammatic cross-section after step S104 is performed as shown in figure 5, wherein, source electrode is represented with 27, is drained
Represented with 28.
It is described that photoetching, etching are carried out to the metal level, to expose the Si3N4 dielectric layers and form Europe
After nurse contact electrode, in addition to：Under conditions of 600 DEG C, annealed 10 minutes in N2 atmosphere,
To form the metal electrode of good Ohmic contact.
It is described to the metal level carry out photoetching, including：The metal level is carried out successively gluing, exposure,
Development.
Step S105, done downwards along the presumptive area on the surface of the Si3N4 dielectric layers exposed
Method is etched, until the AlGaN dielectric layers of etch away sections, the Si3N4 media being etched away
Layer and part the AlGaN dielectric layers formation gate contact hole；
On the basis of Fig. 5, along the surface of the Si3N4 dielectric layers 23 exposed presumptive area to
Lower carry out dry etching, until the AlGaN dielectric layers 22 of etch away sections, the presumptive area is less than
The surface region of the Si3N4 dielectric layers 23 exposed, the Si3N4 dielectric layers 23 being etched away,
With the part AlGaN dielectric layers 22 formation gate contact hole, perform the section after step S105 and show
It is intended to as shown in fig. 6, wherein, gate contact hole is represented with 29.
Step S106, in the gate contact hole deposit silica SiO2 dielectric layers as gate medium,
And the surface of the gate medium is less than surface where the aperture in the gate contact hole；
On the basis of Fig. 6, the SiO2 dielectric layers are deposited in gate contact hole 29 as gate medium,
The diagrammatic cross-section after step S106 is performed as shown in fig. 7, gate medium is represented with 30, and gate medium
30 surface is less than in Fig. 6 surface, i.e. gate medium 30 where the aperture in gate contact hole 29 not by grid
Pole contact hole 29 is filled up.
The silica SiO2 dielectric layers that deposited in the gate contact hole are and described as gate medium
Before the surface of gate medium is less than surface where the aperture in the gate contact hole, in addition to：Using HCL
Clean the gate contact hole.
Step S107, the upper surface deposit polycrystalline silicon PolySi in the SiO2 dielectric layers, and described
Adulterate phosphorus formation grid in PolySi, to complete the making of the enhancement type gallium nitride transistor.
On the basis of Fig. 7, in surface deposit polycrystalline silicon PolySi, the PolySi of gate medium 30, and
Adulterate phosphorus formation grid in the PolySi, perform the diagrammatic cross-section after step S107 as shown in figure 8,
Grid represents with 31, and structure as shown in Figure 8 is cuing open for the enhancement type gallium nitride transistor that is finally fabricated to
Face schematic diagram.
The GaN dielectric layers of phosphorus doping on the surface of silicon substrate of the embodiment of the present invention, reduce enhanced nitrogen
Change the surface field of gallium transistor, the pressure-resistant of enhancement type gallium nitride transistor is improved, in addition, enhanced
The grid doping of gallium nitride transistor has phosphorus, has the compound of electronics and hole so that conducting resistance is reduced,
Realize the smaller and pressure-resistant larger technological requirement of conducting resistance of gallium nitride transistor.
In summary, the GaN dielectric layers of phosphorus doping on the surface of silicon substrate of the embodiment of the present invention, reduce
The surface field of enhancement type gallium nitride transistor, improves the pressure-resistant of enhancement type gallium nitride transistor, separately
Outside, the grid doping of enhancement type gallium nitride transistor has phosphorus, has the compound of electronics and hole so that lead
Be powered resistance reduction, realizes the smaller and pressure-resistant larger technological requirement of conducting resistance of gallium nitride transistor.
In several embodiments provided by the present invention, it should be understood that disclosed apparatus and method,
It can realize by another way.For example, device embodiment described above is only schematical,
For example, the division of the unit, only a kind of division of logic function, can have in addition when actually realizing
Dividing mode, such as multiple units or component can combine or be desirably integrated into another system, or
Some features can be ignored, or not perform.It is another, shown or discussed coupling each other or
Direct-coupling or communication connection can be the INDIRECT COUPLING or communication link of device or unit by some interfaces
Connect, can be electrical, machinery or other forms.
The unit illustrated as separating component can be or may not be it is physically separate, make
It can be for the part that unit is shown or may not be physical location, you can with positioned at a place,
Or can also be distributed on multiple NEs.Can select according to the actual needs part therein or
Person's whole units realize the purpose of this embodiment scheme.
In addition, each functional unit in each embodiment of the invention can be integrated in a processing unit,
Can also be that unit is individually physically present, can also two or more units be integrated in a list
In member.Above-mentioned integrated unit can both be realized in the form of hardware, it would however also be possible to employ hardware adds software
The form of functional unit is realized.
The above-mentioned integrated unit realized in the form of SFU software functional unit, can be stored in a computer
In read/write memory medium.Above-mentioned SFU software functional unit is stored in a storage medium, including some fingers
Order is to cause a computer equipment (can be personal computer, server, or network equipment etc.)
Or processor (processor) performs the part steps of each embodiment methods described of the invention.And it is foregoing
Storage medium include：USB flash disk, mobile hard disk, read-only storage (Read-Only Memory, ROM),
Random access memory (Random Access Memory, RAM), magnetic disc or CD etc. are various can be with
The medium of store program codes.
Those skilled in the art can be understood that, for convenience and simplicity of description, only with above-mentioned each
The division progress of functional module is for example, in practical application, as needed can divide above-mentioned functions
With by different functional module completions, i.e., the internal structure of device is divided into different functional modules, with
Complete all or part of function described above.The specific work process of the device of foregoing description, can be with
With reference to the corresponding process in preceding method embodiment, it will not be repeated here.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than right
It is limited；Although the present invention is described in detail with reference to foregoing embodiments, this area it is common
Technical staff should be understood：It can still modify to the technical scheme described in foregoing embodiments,
Or equivalent substitution is carried out to which part or all technical characteristic；And these modifications or replacement, and
The essence of appropriate technical solution is not set to depart from the scope of various embodiments of the present invention technical scheme.
Claims (6)
1. a kind of preparation method of enhancement type gallium nitride transistor, it is characterised in that including：
The GaN dielectric layers of phosphorus doping, aluminium gallium nitride alloy AlGaN is grown successively on the surface of silicon substrate to be situated between
Matter layer and silicon nitride Si3N4 dielectric layers；
The first area and second area of the Si3N4 dielectric layers are performed etching, to expose described first
Region and the second area distinguish corresponding AlGaN dielectric layers；
In the AlGaN dielectric layers and the remaining Si3N4 dielectric layers upper surface deposited metal exposed
Layer；
Photoetching, etching are carried out to the metal level, is connect with exposing the Si3N4 dielectric layers and forming ohm
Touched electrode；
Dry etching is carried out downwards along the presumptive area on the surface of the Si3N4 dielectric layers exposed, directly
To the AlGaN dielectric layers of etch away sections, the Si3N4 dielectric layers being etched away and part institute
State AlGaN dielectric layers formation gate contact hole；
Silica SiO2 dielectric layers are deposited in the gate contact hole as gate medium, and the grid to be situated between
The surface of matter is less than surface where the aperture in the gate contact hole；
Adulterated in the upper surface deposit polycrystalline silicon PolySi of the SiO2 dielectric layers, and in the PolySi
Phosphorus formation grid, to complete the making of the enhancement type gallium nitride transistor.
2. according to the method described in claim 1, it is characterised in that described in the AlGaN exposed
Before dielectric layer and the remaining Si3N4 dielectric layers upper surface deposited metal layer, in addition to：
The AlGaN dielectric layers exposed and the remaining Si3N4 dielectric layers upper surface are carried out
Cleaning.
3. method according to claim 2, it is characterised in that the metal level is Ohmic electrode gold
Category, the Ohmic electrode metal include two layer medium, the two layer medium according to order from top to bottom according to
Secondary is titanium and aluminium.
4. method according to claim 3, it is characterised in that described that light is carried out to the metal level
Carve, etch, to expose the Si3N4 dielectric layers and be formed after Ohm contact electrode, in addition to：
Under conditions of 600 DEG C, annealed 10 minutes in N2 atmosphere.
5. method according to claim 4, it is characterised in that described in the gate contact hole
Deposition silica SiO2 dielectric layers connect as gate medium, and the surface of the gate medium less than the grid
Before surface where the aperture of contact hole, in addition to：
The gate contact hole is cleaned using HCL.
6. method according to claim 5, it is characterised in that described that light is carried out to the metal level
Carve, including：
Carry out gluing, exposure, development successively to the metal level.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417481A (en) * | 2018-03-22 | 2018-08-17 | 京东方科技集团股份有限公司 | Processing method, thin film transistor (TFT) and the display device of silicon nitride dielectric layer |
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| CN102709321A (en) * | 2012-04-20 | 2012-10-03 | 程凯 | Enhanced switch element and production method thereof |
| CN104821340A (en) * | 2014-02-05 | 2015-08-05 | 瑞萨电子株式会社 | Semiconductor device |
| CN105047692A (en) * | 2015-06-10 | 2015-11-11 | 上海新傲科技股份有限公司 | Substrate for high-electron-mobility transistor |
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| CN108417481A (en) * | 2018-03-22 | 2018-08-17 | 京东方科技集团股份有限公司 | Processing method, thin film transistor (TFT) and the display device of silicon nitride dielectric layer |
| CN108417481B (en) * | 2018-03-22 | 2021-02-23 | 京东方科技集团股份有限公司 | Processing method of silicon nitride dielectric layer, thin film transistor and display device |
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