CN107221502A - A kind of preparation method of trench gate DMOS - Google Patents
A kind of preparation method of trench gate DMOS Download PDFInfo
- Publication number
- CN107221502A CN107221502A CN201710388903.5A CN201710388903A CN107221502A CN 107221502 A CN107221502 A CN 107221502A CN 201710388903 A CN201710388903 A CN 201710388903A CN 107221502 A CN107221502 A CN 107221502A
- Authority
- CN
- China
- Prior art keywords
- ion
- layer
- type
- complete
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 150000002500 ions Chemical class 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 31
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- 238000000407 epitaxy Methods 0.000 claims description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 238000000137 annealing Methods 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- -1 boron ion Chemical class 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052786 argon Inorganic materials 0.000 claims description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 239000007943 implant Substances 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 4
- 239000012190 activator Substances 0.000 abstract description 3
- 238000004151 rapid thermal annealing Methods 0.000 abstract description 3
- 238000013459 approach Methods 0.000 abstract description 2
- 238000011982 device technology Methods 0.000 abstract description 2
- 238000005265 energy consumption Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000012986 modification Methods 0.000 abstract 1
- 230000004048 modification Effects 0.000 abstract 1
- 238000004904 shortening Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- UIFOTCALDQIDTI-UHFFFAOYSA-N arsanylidynenickel Chemical compound [As]#[Ni] UIFOTCALDQIDTI-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000009828 non-uniform distribution Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a kind of preparation method of trench gate DMOS, belong to semiconductor power device technology field.The present invention to the existing process modification for generally use ion implanting combination high temperature knot making trench gate DMOS device body area for：Injected ions into using the ion implantation technology of multiple different-energy to appropriate depth and directly form body area, then pass through rapid thermal annealing activator impurity ion.The control accuracy of body area dopant profiles is improved with preparation method of the present invention, and then improves the uniformity of different batches DMOS product threshold voltages；On the other hand, by suitably selecting the number of times, energy and dosage of ion implanting, the body area of approaches uniformity doping can be formed, the ability of the anti-drain-source break-through of device is enhanced；In addition, this invention simplifies technological process, shortening the production time, reduce energy consumption and production cost improves the competitiveness of product in market.
Description
Technical field
The invention belongs to semiconductor power device technology field, and in particular to a kind of preparation method of trench gate DMOS.
Background technology
Power DMOS is the power electronic devices grown up on the basis of MOS integrated circuit technologies.With bipolar-type power
Device is compared, and DMOS has switching speed fast, and input impedance is high, the advantages of driving power is small, its structure mainly have plane grid-type,
Trench gate, shielding grid-type, the type of superjunction four.Trench gate DMOS forms ditch by longitudinal junction depth difference of body area and source region
Road, eliminates the JFET areas of planar gate DMOS presence, its cellular size and conducting resistance be substantially reduced, Switching Power Supply,
The occasions such as inverter, high speed line driver are applied widely.Threshold voltage is DMOS important parameter, is also design
The important parameter of DMOS peripheral control circuits, it to device be switched on and off have a major impact, it is therefore desirable to accurate control
DMOS threshold voltage.
Threshold voltage depends primarily on gate oxide thickness, the dopant profiles in grid oxygen fixed charge Liang Heti areas.At present, making
Body area is generally made using the technique of ion implantation combination high temperature knot in trench gate DMOS device, though with above-mentioned technique
It is simple and reliable, but still suffer from following weak point：On the one hand, can not during high temperature knot because diffusion furnace temperature-controlled precision is not high
The dopant profiles in accurate control DMOS bodies area, cause the uniformity of mesosome area dopant profiles of different batches DMOS products by not
Profit influence so that the uniformity reduction of threshold voltage；On the other hand, high temperature knot is general is carried out in diffusion furnace, its " heating-
Constant temperature-cooling " process needs to expend longer time, this also means that higher time cost；In addition, being formed with the technique
Body area, its longitudinal direction is doped to non-uniform Distribution so that the anti-drain-source break-through ability of device is relatively weak, is unfavorable for manufacturing short ditch
Road device.
The content of the invention
The present invention provides a kind of trench gate DMOS preparation method for being capable of accurate control volume area dopant profiles, with the making
Threshold voltage between multiple batches of DMOS made from method has good uniformity, and simplifies production procedure, shortens life
The production time, reduce production cost.
To achieve the above object, the present invention provides following technical scheme：
Technical scheme 1：
A kind of preparation method of trench gate DMOS, comprises the following steps：
Step A：N-type epitaxy layer is grown in N-type substrate, then performs etching to form groove in N-type epitaxy layer；
Step B：The inner surface of groove is made in step A and the N-type epitaxy layer upper surface formation gate oxide of groove is removed；
Step C：In deposit polycrystalline silicon layer on gate oxide made from step B；
Step D：Polysilicon layer made from step C is subjected to surface planarisation processing so that polysilicon layer surface in groove
With N-type epitaxy layer upper surface flush；
Step E：Complete after step D, acceptor ion is injected into outside N-type by the ion implanting operation of multiple different-energy
Prolong and body area is formed in floor；
Step F：Complete after step E, donor ion be injected into N-type epitaxy layer using ion implantation and forms source region,
The junction depth of formed source region is no more than the junction depth in body area；
Step G：Complete after step F, in N-type epitaxy layer surface depositing insulating layer, then in insulating barrier formation contact hole；
Step H：Acceptor ion is injected to form P by contact hole made from step G using ion implantation+Area；
Step I：Complete after step H, sample is subjected to quick thermal annealing process, annealing temperature is 1000~1100 DEG C, is moved back
The fiery time is 1~60 second；
Step J：Complete after step I, in the upper and lower surface difference deposited metal layer of sample, and then form source electrode and drain electrode.
Technical scheme 2：
A kind of preparation method of trench gate DMOS, comprises the following steps：
Step A：The growing P-type epitaxial layer in P type substrate, then performs etching to form groove in p-type epitaxial layer；
Step B：The inner surface of groove is made in step A and the p-type epitaxial layer upper surface formation gate oxide of groove is removed；
Step C：In deposit polycrystalline silicon layer on gate oxide made from step B；
Step D：Polysilicon layer made from step C is subjected to surface planarisation processing so that polysilicon layer surface in groove
With p-type epitaxial layer upper surface flush；
Step E：Complete after step D, donor ion is injected into outside p-type by the ion implanting operation of multiple different-energy
Prolong and body area is formed in floor；
Step F：Complete after step E, acceptor ion be injected into p-type epitaxial layer using ion implantation and forms source region,
The junction depth of formed source region is no more than the junction depth in body area；
Step G：Complete after step F, in p-type epi-layer surface depositing insulating layer, then in insulating barrier formation contact hole；
Step H：Donor ion is injected to form N by contact hole made from step G using ion implantation+Area；
Step I：Complete after step H, sample is subjected to quick thermal annealing process, annealing temperature is 1000~1100 DEG C, is moved back
The fiery time is 1~60 second；
Step J：Complete after step I, in the upper and lower surface difference deposited metal layer of sample, and then form source electrode and drain electrode.
The technical program simply exchanges the donor ion in technical scheme 1 and acceptor ion, and other guide keeps constant,
So that P-channel device is made.
Technical scheme 3：
A kind of preparation method of trench gate DMOS, comprises the following steps：
Step A：N-type epitaxy layer is grown in N-type substrate, by the operation of the ion implanting of multiple different-energy by acceptor from
Son, which is injected into N-type epitaxy layer, forms body area；
Step B：Complete after step A, donor ion be injected into N-type epitaxy layer using ion implantation and forms source region,
The junction depth of formed source region is no more than the junction depth in body area；
Step C：Complete after step B, perform etching to form groove in N-type epitaxy layer；
Step D：The inner surface of groove is made in step C and the N-type epitaxy layer upper surface formation gate oxide of groove is removed；
Step E：In deposit polycrystalline silicon layer on gate oxide made from step D；
Step F：Polysilicon layer made from step E is subjected to surface planarisation processing so that polysilicon layer surface in groove
With N-type epitaxy layer upper surface flush；
Step G：In N-type epitaxy layer surface depositing insulating layer made from step F, then in insulating barrier formation contact hole；
Step H：Acceptor ion is injected to form P by contact hole made from step G using ion implantation+Area；
Step I：Complete after step H, sample is subjected to quick thermal annealing process, annealing temperature is 1000~1100 DEG C, is moved back
The fiery time is 1~60 second；
Step J：Complete after step I, in the upper and lower surface difference deposited metal layer of sample, and then form source electrode and drain electrode.
It can be seen from common sense in the field：Body area and source region can be first prepared on epitaxial layer, remaining structure is then carried out again
The making of layer.
Technical scheme 4：
A kind of preparation method of trench gate DMOS, comprises the following steps：
Step A：The growing P-type epitaxial layer in P type substrate, by the operation of the ion implanting of multiple different-energy by alms giver from
Son, which is injected into p-type epitaxial layer, forms body area；
Step B：Complete after step A, acceptor ion be injected into p-type epitaxial layer using ion implantation and forms source region,
The junction depth of formed source region is no more than the junction depth in body area；
Step C：Complete after step B, perform etching to form groove on p-type epitaxial layer；
Step D：The inner surface of groove is made in step C and the p-type epitaxial layer upper surface formation gate oxide of groove is removed；
Step E：In deposit polycrystalline silicon layer on gate oxide made from step D；
Step F：Polysilicon layer made from step E is subjected to surface planarisation processing so that polysilicon layer surface in groove
With p-type epitaxial layer upper surface flush；
Step G：In p-type epi-layer surface depositing insulating layer made from step F, then in insulating barrier formation contact hole；
Step H：Donor ion is injected to form N by contact hole made from step G using ion implantation+Area；
Step I：Complete after step H, sample is subjected to quick thermal annealing process, annealing temperature is 1000~1100 DEG C, is moved back
The fiery time is 1~60 second；
Step J：Complete after step I, in the upper and lower surface difference deposited metal layer of sample, and then form source electrode and drain electrode.
The technical program simply exchanges the donor ion in technical scheme 3 and acceptor ion, and other guide keeps constant,
So that P-channel device is made.
Manufacture craft disclosed in technical solution of the present invention can be used for making trench gate IGBT Zhong Ti areas.
In four technical schemes described above, substrate and epitaxial film materials can be silicon, or carborundum, may be used also
To be gallium nitride.
In four technical schemes described above, donor ion generally uses phosphonium ion or arsenic ion, and acceptor ion leads to
Frequently with boron ion or aluminium ion.
In four technical schemes described above, surface planarisation processing can be using etching, CMP methods or any suitable
Method epi-layer surface excess polysilicon is removed.
In four technical schemes described above, body area is prepared using the method different from prior art, that is, carried out multiple
The ion implanting of different-energy；
Specifically, Implantation Energy is 40~500keV, and injection number of times is 2~5 times, total implantation dosage of multiple implant operation
For 1.0e12~1.0e14/cm2；
In four technical schemes described above, preparation source region is prior art, injection ion energy and dosage this area
Technical staff can be adjusted according to actual requirement；
Further, in four technical schemes described above using rapid thermal annealing come activator impurity ion, specific behaviour
Work includes：
Sample is rapidly warming up to 1000~1100 DEG C of target temperature in argon gas or the inert atmosphere of nitrogen formation, and it is short
Temporarily continue, the duration is 1~60 second.
In the manufacturing process of conventional trench gate DMOS devices, body area is usually ion implanting combination high temperature knot institute shape
Into.Ion implantation energy therein is relatively low, and the ion of injection concentrates on silicon chip surface.Then silicon chip is placed in diffusion furnace and carried out
High temperature knot, foreign ion spreads to form certain dopant profiles to silicon chip depths.And the present invention is directly injected ions into
To certain depth formation body area, then carry out rapid thermal annealing and carry out activator impurity ion.
The present invention is moved back when preparing the body area of trench gate DMOS using the ion implanting of multiple different-energy with reference to quick heat
The method of fire processing, compared with after the ion implanting generally used at present using the method for high temperature knot, has the advantage that：
(1) ion implantings have very high precision, and quick thermal annealing process hardly causes impurity to spread, because
This improves the control accuracy to DMOS bodies area dopant profiles so that body area dopant profiles between different batches DMOS products
Uniformity is improved, and the uniformity of threshold voltage is also improved.
(2) can form the body area of approaches uniformity doping by suitably selecting the number of times, energy and dosage of ion implanting,
As shown in Figure 6.Compared with the non-uniform doping of traditional handicraft formation, when the peak concentration of doping is identical, it has bigger
Doping total amount, therefore the ability enhancing of the anti-drain-source break-through of device.
(3) simplifies technological process, shortens the production time, energy consumption and production cost is reduced, with present invention process
Be conducive to improving the market competitiveness.
Brief description of the drawings
Fig. 1 is the flow chart that the embodiment of the present invention 1 makes trench gate DMOS device.
Fig. 2 is the structural representation that the embodiment of the present invention 1 makes trench gate DMOS device；Wherein, figure (a) is to prepare groove
Structural representation afterwards, figure (b) is prepares the structural representation after gate oxide, and figure (c) is that the structure after deposit polycrystalline silicon is shown
It is intended to, figure (d) is the structural representation after surface planarisation is handled, figure (e) is the structural representation formed behind body area, is schemed (f)
To form the structural representation after source region, figure (g) is prepares the structural representation after insulating barrier, and figure (h) is to prepare source electrode, drain electrode
Structural representation afterwards.
Fig. 3 is the flow chart that the embodiment of the present invention 2 makes trench gate DMOS device.
Fig. 4 is the structural representation that the embodiment of the present invention 2 makes trench gate DMOS device；Wherein, figure (a) is to form body area
Structural representation afterwards, figure (b) is the structural representation formed after source region, and figure (c) is schemed to prepare the structural representation after groove
(d) to prepare the structural representation after gate oxide, figure (e) is the structural representation after deposit polycrystalline silicon, and figure (f) is flat for surface
Structural representation after smoothization processing, figure (g) is prepares the structural representation after insulating barrier, and figure (h) is to prepare after source electrode, drain electrode
Structural representation.
Fig. 5 is longitudinal doping concentration distribution figure of trench gate DMOS device made from traditional handicraft.
Fig. 6 is longitudinal doping concentration distribution figure of trench gate DMOS device made from present invention process.
In figure, 1 is N-type substrate, and 2 be N-type epitaxy layer, and 3 be groove, and 4 be gate oxide, and 5 be polysilicon layer, and 6 be body area,
7 be source region, and 8 be insulating barrier, and 9 be P+Area, 10 be source electrode, and 11 be drain electrode, and 12 be P type substrate, and 13 be p-type epitaxial layer, and 14 be N+
Area.
Embodiment
The principle of the invention is described in detail below in conjunction with the specific embodiment of the invention and Figure of description：
Embodiment 1：
The schematic flow sheet of trench gate DMOS device is made for the present embodiment as shown in Figure 1, each step is carried out below
Illustrate one by one：
Step A：N-type epitaxy layer 2 is grown in N-type substrate 1, it can be seen from common sense in the field：N-type substrate 1 is heavy doping,
N-type epitaxy layer 2 is is lightly doped, and specific doping concentration is prior art, can be selected according to actual requirement, therefore herein no longer
Repeat, as shown in figure (a) in Fig. 2, then perform etching to form the vertical of groove 3 in groove 3, the present embodiment in N-type epitaxy layer
It is rectangle to cross sectional shape, it can be seen from common sense in the field：The depth of groove should be less than the thickness of N-type epitaxy layer 2, in addition, ditch
Groove preparation technology can be photoetching or etching technics, or other suitable techniques, and the present invention is not limited；
Step B：As shown in figure (b) in Fig. 2, the inner surface of groove 3 is made in step A and the N-type epitaxy layer of groove 3 is removed
The thickness for the gate oxide 4 that 2 upper surfaces are formed in gate oxide 4, the present embodiment is 300~500 angstroms；
Step C：As shown in figure (c) in Fig. 2, in deposit polycrystalline silicon layer 5 on gate oxide 4 made from step B；
Step D：As shown in figure (d) in Fig. 2, polysilicon layer 5 made from step C is carried out by surface planarisation using CMP methods
Handle so that the surface of polysilicon layer 5 and the upper surface flush of N-type epitaxy layer 2 in groove 3, the thickness of the present embodiment polysilicon layer 5 is
6000~8000 angstroms；
Step E：Complete after step D, carry out energy 70keV, dosage 9e12/cm2With energy 220keV, dosage 4.5e12/cm2
Boron ion injection it is each once, the body area 6 of about 0.6 micron of junction depth is formed in N-type epitaxy layer 2, as shown in figure (e) in Fig. 2；
Step F：Complete after step E, carry out primary energy 60keV, dosage 1e14/cm2Arsenic ion injection, in N-type extension
About 0.2 micron of source region 7 of junction depth is formed in layer 2；, as shown in figure (f) in Fig. 2；
Step G：Complete after step F, as shown in figure (g) in Fig. 2, in the surface depositing insulating layer 8 of N-type epitaxy layer 2, specifically
Technique is prior art, be will not be repeated here, and insulating barrier 8 can be silicon dioxide layer or boron-phosphorosilicate glass, or any
Suitable material, the present invention is not limited this, and then in the formation contact hole of insulating barrier 8, the technique for forming contact hole is existing
Technology, will not be repeated here；
Step H：It is 1.0e that the donor ion that the present embodiment is used, which carries out dose for boron difluoride ion, specially,15/
cm2, energy be 40keV boron difluoride ion implanting, 2 in N-type epitaxy layer in form P+In area 9, such as Fig. 2 shown in figure (h)；
Step I：Complete after step H, sample is subjected to quick thermal annealing process, annealing temperature is 1000 DEG C, annealing time
For 30 seconds；
Step J：Complete after step I, in the upper and lower surface difference deposited metal layer of sample, and then form source electrode 10 and drain electrode
In 11, such as Fig. 2 shown in figure (h)；The present embodiment source electrode material uses Al-Si-Cu alloy, and the present embodiment drain material uses titanium nickeline
Composite bed, thickness can be 2~4 microns.
The technique of the embodiment of the present invention 1 and traditional handicraft are emulated using TCAD softwares, as a result as shown in Figure 5 and Figure 6,
The body area dopant profiles of the DMOS devices made as can be seen from Figure 5 using the method for low energy ion beam implantation combination high temperature knot are not
Uniformly, technique provided by the present invention makes by using the ion implanting combination quick thermal annealing process of multiple different-energy
DMOS devices body area dopant profiles it is almost uniform.
Implement 2：
The schematic flow sheet that the present embodiment makes trench gate DMOS device is illustrated in figure 3, each step is carried out below
Illustrate one by one：
Step A：The growing P-type epitaxial layer 13 in P type substrate 12, it can be seen from common sense in the field：P type substrate 12 is heavily doped
Miscellaneous, p-type epitaxial layer 13 is is lightly doped, and specific doping concentration is prior art, can be selected according to actual requirement, therefore herein
Repeat no more, carry out energy 400keV, dosage 8e12/cm2With energy 150keV, dosage 3e12/cm2Phosphonium ion injection each one
It is secondary, the body area 6 of about 0.5 micron of junction depth is formed in p-type epitaxial layer 13；
Step B：Complete after step A, carry out primary energy 40keV, dosage 1e14/cm2Boron difluoride ion implanting, in P
In type epitaxial layer 13, the source region 7 of about 0.2 micron of junction depth is formed；
Step C：Complete after step B, perform etching to form groove 3 in groove 3, the present embodiment in p-type epitaxial layer 13
Longitudinal section shape is rectangle, it can be seen from common sense in the field：The depth of groove should be less than the thickness of p-type epitaxial layer 13, in addition,
Groove preparation technology can be photoetching or etching technics, or other suitable techniques, and the present invention is not limited；
Step D：The inner surface of groove 3 is made in step A and the upper surface of the p-type epitaxial layer 13 formation grid oxygen of groove 3 is removed
The thickness for changing the gate oxide 4 in layer 4, the present embodiment is 300~500 angstroms；
Step E：In deposit polycrystalline silicon layer 5 on gate oxide 4 made from step B；
Step F：Polysilicon layer 5 made from step C is carried out by surface planarisation processing using CMP methods so that many in groove 3
The surface of crystal silicon layer 5 and the upper surface flush of N-type epitaxy layer 2, the thickness of the present embodiment polysilicon layer 5 is 6000~8000 angstroms；
Step G：Complete after step F, in the surface depositing insulating layer 8 of p-type epitaxial layer 13, specific technique is prior art,
It will not be repeated here, insulating barrier 8 can be silicon dioxide layer or boron-phosphorosilicate glass, or any suitable material, this hair
Bright that this is not limited, then in the formation contact hole of insulating barrier 8, the technique for forming contact hole is prior art, is no longer gone to live in the household of one's in-laws on getting married herein
State；
Step H：Complete after step G, progress dose is 1e14/cm2, energy for 60keV arsenic ion inject, in p-type
N is formed in 13 in epitaxial layer+Area 14,；
Step I：Complete after step H, sample is subjected to quick thermal annealing process, annealing temperature is 1100 DEG C, annealing time
For 10 seconds；
Step J：Complete after step I, in the upper and lower surface difference deposited metal layer of sample, and then form source electrode 10 and drain electrode
11, the present embodiment source electrode material uses Al-Si-Cu alloy, and the present embodiment drain material uses titanium nickeline composite bed, and thickness can be
2~4 microns.
Embodiments of the invention are set forth above in association with accompanying drawing, but the invention is not limited in above-mentioned specific
Embodiment, above-mentioned embodiment is only schematical, rather than restricted, and one of ordinary skill in the art exists
Under the enlightenment of the present invention, in the case of present inventive concept and scope of the claimed protection is not departed from, many shapes can be also made
Formula, these are belonged within the protection of the present invention.
Claims (9)
1. a kind of preparation method of trench gate DMOS, comprises the following steps：
Step A：N-type epitaxy layer is grown in N-type substrate, then performs etching to form groove in N-type epitaxy layer；
Step B：The inner surface of groove is made in step A and the N-type epitaxy layer upper surface formation gate oxide of groove is removed；
Step C：In deposit polycrystalline silicon layer on gate oxide made from step B；
Step D：Polysilicon layer made from step C is subjected to surface planarisation processing so that polysilicon layer surface and N-type in groove
Epitaxial layer upper surface flush；
Step E：Complete after step D, operated by the ion implanting of multiple different-energy and acceptor ion is injected into N-type epitaxy layer
Interior formation body area；
Step F：Complete after step E, donor ion is injected into N-type epitaxy layer using ion implantation and forms source region, institute's shape
Junction depth into source region is no more than the junction depth in body area；
Step G：Complete after step F, in N-type epitaxy layer surface depositing insulating layer, then in insulating barrier formation contact hole；
Step H：Acceptor ion is injected to form P by contact hole made from step G using ion implantation+Area；
Step I：Complete after step H, sample is subjected to quick thermal annealing process, annealing temperature is 1000~1100 DEG C, during annealing
Between be 1~60 second；
Step J：Complete after step I, in the upper and lower surface difference deposited metal layer of sample, and then form source electrode and drain electrode.
2. a kind of preparation method of trench gate DMOS, comprises the following steps：
Step A：The growing P-type epitaxial layer in P type substrate, then performs etching to form groove in p-type epitaxial layer；
Step B：The inner surface of groove is made in step A and the p-type epitaxial layer upper surface formation gate oxide of groove is removed；
Step C：In deposit polycrystalline silicon layer on gate oxide made from step B；
Step D：Polysilicon layer made from step C is subjected to surface planarisation processing so that polysilicon layer surface and p-type in groove
Epitaxial layer upper surface flush；
Step E：Complete after step D, operated by the ion implanting of multiple different-energy and donor ion is injected into p-type epitaxial layer
Interior formation body area；
Step F：Complete after step E, acceptor ion is injected into p-type epitaxial layer using ion implantation and forms source region, institute's shape
Junction depth into source region is no more than the junction depth in body area；
Step G：Complete after step F, in p-type epi-layer surface depositing insulating layer, then in insulating barrier formation contact hole；
Step H：Donor ion is injected to form N by contact hole made from step G using ion implantation+Area；
Step I：Complete after step H, sample is subjected to quick thermal annealing process, annealing temperature is 1000~1100 DEG C, during annealing
Between be 1~60 second；
Step J：Complete after step I, in the upper and lower surface difference deposited metal layer of sample, and then form source electrode and drain electrode.
3. a kind of preparation method of trench gate DMOS, comprises the following steps：
Step A：N-type epitaxy layer is grown in N-type substrate, acceptor ion is noted by the ion implanting operation of multiple different-energy
Enter to N-type epitaxy layer and form body area；
Step B：Complete after step A, donor ion is injected into N-type epitaxy layer using ion implantation and forms source region, institute's shape
Junction depth into source region is no more than the junction depth in body area；
Step C：Complete after step B, perform etching to form groove in N-type epitaxy layer；
Step D：The inner surface of groove is made in step C and the N-type epitaxy layer upper surface formation gate oxide of groove is removed；
Step E：In deposit polycrystalline silicon layer on gate oxide made from step D；
Step F：Polysilicon layer made from step E is subjected to surface planarisation processing so that polysilicon layer surface and N-type in groove
Epitaxial layer upper surface flush；
Step G：In N-type epitaxy layer surface depositing insulating layer made from step F, then in insulating barrier formation contact hole；
Step H：Acceptor ion is injected to form P by contact hole made from step G using ion implantation+Area；
Step I：Complete after step H, sample is subjected to quick thermal annealing process, annealing temperature is 1000~1100 DEG C, during annealing
Between be 1~60 second；
Step J：Complete after step I, in the upper and lower surface difference deposited metal layer of sample, and then form source electrode and drain electrode.
4. a kind of preparation method of trench gate DMOS, comprises the following steps：
Step A：The growing P-type epitaxial layer in P type substrate, is noted donor ion by the ion implanting operation of multiple different-energy
Enter to p-type epitaxial layer and form body area；
Step B：Complete after step A, acceptor ion is injected into p-type epitaxial layer using ion implantation and forms source region, institute's shape
Junction depth into source region is no more than the junction depth in body area；
Step C：Complete after step B, perform etching to form groove on p-type epitaxial layer；
Step D：The inner surface of groove is made in step C and the p-type epitaxial layer upper surface formation gate oxide of groove is removed；
Step E：In deposit polycrystalline silicon layer on gate oxide made from step D；
Step F：Polysilicon layer made from step E is subjected to surface planarisation processing so that polysilicon layer surface and p-type in groove
Epitaxial layer upper surface flush；
Step G：In p-type epi-layer surface depositing insulating layer made from step F, then in insulating barrier formation contact hole；
Step H：Donor ion is injected to form N by contact hole made from step G using ion implantation+Area；
Step I：Complete after step H, sample is subjected to quick thermal annealing process, annealing temperature is 1000~1100 DEG C DEG C, annealing
Time is 1~60 second；
Step J：Complete after step I, in the upper and lower surface difference deposited metal layer of sample, and then form source electrode and drain electrode.
5. the preparation method of a kind of trench gate DMOS according to claim 1 or 3, it is characterised in that form body area and adopted
Acceptor ion is boron ion or aluminium ion.
6. the preparation method of a kind of trench gate DMOS according to claim 2 or 4, it is characterised in that form body area and adopted
Donor ion is phosphonium ion or arsenic ion.
7. a kind of preparation method of trench gate DMOS according to any one of Claims 1-4, it is characterised in that substrate and
The material of epitaxial layer is silicon, carborundum or gallium nitride.
8. the preparation method of a kind of trench gate DMOS according to any one of Claims 1-4, it is characterised in that repeatedly not
In co-energy ion implanting operation：Implantation Energy be 40~500keV, injection number of times be 2~5 times, multiple implant operation it is total
Implantation dosage is 1.0e12~1.0e14/cm2。
9. a kind of preparation method of trench gate DMOS according to any one of Claims 1-4, it is characterised in that fast speed heat
Annealing is specifically：It is rapidly heated in the atmosphere of nitrogen or argon gas to annealing temperature, and continues 1~60 at this temperature
Second.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710388903.5A CN107221502A (en) | 2017-05-25 | 2017-05-25 | A kind of preparation method of trench gate DMOS |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710388903.5A CN107221502A (en) | 2017-05-25 | 2017-05-25 | A kind of preparation method of trench gate DMOS |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107221502A true CN107221502A (en) | 2017-09-29 |
Family
ID=59948187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710388903.5A Pending CN107221502A (en) | 2017-05-25 | 2017-05-25 | A kind of preparation method of trench gate DMOS |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107221502A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107978629A (en) * | 2017-11-30 | 2018-05-01 | 上海华虹宏力半导体制造有限公司 | P-type trench gate mosfet and its manufacture method |
| CN111009464A (en) * | 2019-11-25 | 2020-04-14 | 深圳第三代半导体研究院 | Manufacturing method of SiC power device chip gate oxide layer and power device |
| CN111799158A (en) * | 2020-07-17 | 2020-10-20 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of one-time programmable device |
| CN112530867A (en) * | 2019-09-17 | 2021-03-19 | 华润微电子（重庆）有限公司 | Groove type field effect transistor structure and preparation method thereof |
| CN112786693A (en) * | 2021-01-22 | 2021-05-11 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
| CN118112307A (en) * | 2024-04-17 | 2024-05-31 | 杭州元芯半导体科技有限公司 | Current sampling circuit and current sampling method of switching power supply |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1197168C (en) * | 1999-10-18 | 2005-04-13 | 精工电子有限公司 | Vertical MOS transistor |
| CN1729578A (en) * | 2002-12-19 | 2006-02-01 | 西利康尼克斯股份有限公司 | Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same |
| CN102129990A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Method for manufacturing base region of bipolar transistor |
| CN104835740A (en) * | 2014-02-11 | 2015-08-12 | 北大方正集团有限公司 | Manufacturing method of groove-type power device |
-
2017
- 2017-05-25 CN CN201710388903.5A patent/CN107221502A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1197168C (en) * | 1999-10-18 | 2005-04-13 | 精工电子有限公司 | Vertical MOS transistor |
| CN1729578A (en) * | 2002-12-19 | 2006-02-01 | 西利康尼克斯股份有限公司 | Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same |
| CN102129990A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Method for manufacturing base region of bipolar transistor |
| CN104835740A (en) * | 2014-02-11 | 2015-08-12 | 北大方正集团有限公司 | Manufacturing method of groove-type power device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107978629A (en) * | 2017-11-30 | 2018-05-01 | 上海华虹宏力半导体制造有限公司 | P-type trench gate mosfet and its manufacture method |
| CN112530867A (en) * | 2019-09-17 | 2021-03-19 | 华润微电子（重庆）有限公司 | Groove type field effect transistor structure and preparation method thereof |
| CN111009464A (en) * | 2019-11-25 | 2020-04-14 | 深圳第三代半导体研究院 | Manufacturing method of SiC power device chip gate oxide layer and power device |
| CN111799158A (en) * | 2020-07-17 | 2020-10-20 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of one-time programmable device |
| CN111799158B (en) * | 2020-07-17 | 2022-09-09 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of one-time programmable device |
| CN112786693A (en) * | 2021-01-22 | 2021-05-11 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
| CN118112307A (en) * | 2024-04-17 | 2024-05-31 | 杭州元芯半导体科技有限公司 | Current sampling circuit and current sampling method of switching power supply |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107221502A (en) | A kind of preparation method of trench gate DMOS | |
| US6482681B1 (en) | Hydrogen implant for buffer zone of punch-through non epi IGBT | |
| CN101399288B (en) | LDMOS chip light doped drift region structure and forming method | |
| US20240266176A1 (en) | Semiconductor device and method for manufacturing | |
| CN104701160B (en) | Manufacture the method and semiconductor structure of semiconductor structure | |
| US9269805B2 (en) | Method to manufacture short channel trench MOSFET | |
| CN107710417A (en) | The manufacture method of semiconductor device | |
| US11764296B2 (en) | Method for manufacturing a semiconductor device | |
| CN102891180A (en) | Semiconductor device comprising MOSFET device and manufacturing method | |
| CN102412162B (en) | Method for improving breakdown voltage of N-groove laterally diffused metal oxide semiconductor (LDMOS) | |
| CN112397567A (en) | High-voltage RESURF LDMOS device with P-type transverse variable doping area | |
| CN107093632A (en) | Semiconductor devices and the method for forming semiconductor devices | |
| CN106328524A (en) | Manufacturing method of vertical double-diffused MOS device | |
| US11990515B2 (en) | Up-diffusion suppression in a power MOSFET | |
| CN104716039B (en) | Improve the back process preparation method of IGBT performances | |
| CN104518027B (en) | LDMOS device and its manufacturing method | |
| CN109065612A (en) | A kind of super junction MOSFET structure and its manufacturing method | |
| CN106257630B (en) | The manufacturing method of radio frequency LDMOS device | |
| CN104992966B (en) | A kind of preparation method of the low bipolar high frequency power transistor chip of heat budget | |
| CN105493289B (en) | Method for manufacturing insulated gate bipolar transistor | |
| CN208433413U (en) | Semiconductor structure | |
| Cheng et al. | A Novel Junction Termination Technique with Excellent Cost-Performance and Extraordinary Anti-Charge-Deviation Ability | |
| CN106298531A (en) | The manufacture method of rf-ldmos quasiconductor | |
| CN118299257A (en) | Semiconductor structure and forming method thereof | |
| CN102403335A (en) | MOS (metal oxide semiconductor) device and manufacturing method for same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170929 |
|
| WD01 | Invention patent application deemed withdrawn after publication |