CN107204395B

CN107204395B - Semiconductor device and method for manufacturing the same

Info

Publication number: CN107204395B
Application number: CN201610150144.4A
Authority: CN
Inventors: 廖世安; 陈効义; 许明祺; 刘俊宏; 谢明勋
Original assignee: Epistar Corp
Current assignee: Epistar Corp
Priority date: 2016-03-16
Filing date: 2016-03-16
Publication date: 2021-02-05
Anticipated expiration: 2036-03-16
Also published as: CN112909151A; CN112885944A; CN107204395A

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a semiconductor die including a laminated structure, a first bonding pad and a second bonding pad protruding from a surface of the laminated structure, wherein the shortest distance between the first bonding pad and the second bonding pad is less than 150 μm, a carrier having a surface, a third bonding pad and a fourth bonding pad disposed on the surface of the carrier, and a conductive bonding layer including a current conduction region disposed between the first bonding pad and the third bonding pad and between the second bonding pad and the fourth bonding pad.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor device, and more particularly, to a bonding structure of a semiconductor device and a method for manufacturing the same.

Background

The semiconductor device includes a compound semiconductor composed of a group iii-v element, such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium nitride (GaN), and may be a Light Emitting Diode (LED), a power device, or a solar cell. The LED structure comprises a p-type semiconductor layer, an n-type semiconductor layer and an active layer, wherein the active layer is arranged between the p-type semiconductor layer and the n-type semiconductor layer, so that electrons and holes respectively provided by the n-type semiconductor layer and the p-type semiconductor layer are compounded on the active layer under the action of an external electric field, and electric energy is converted into light energy.

In order to improve the electrical performance and heat dissipation efficiency of the LED, the flip-chip LED with a chip directly bonded to a carrier plate is used, however, as the electronic product is thinned, the yield of the flip-chip LED manufactured by the conventional method is reduced, and the reliability of the flip-chip LED is also affected.

Disclosure of Invention

The invention relates to a semiconductor device, comprising a semiconductor die comprising a laminated structure, a first bonding pad and a second bonding pad arranged on a surface of the laminated structure, wherein the shortest distance between the first bonding pad and the second bonding pad is less than 150 mu m, a carrier plate provided with a surface, a third bonding pad and a fourth bonding pad arranged on the surface of the carrier plate, and a conductive bonding layer comprising a current conducting area arranged between the first bonding pad and the third bonding pad and between the second bonding pad and the fourth bonding pad.

The invention relates to a method for manufacturing a semiconductor device, which comprises providing a semiconductor die comprising a laminated structure, a first bonding pad and a second bonding pad arranged on a surface of the laminated structure, wherein the shortest distance between the first bonding pad and the second bonding pad is less than 150 μm, providing a carrier plate comprising a surface, a third bonding pad and a fourth bonding pad arranged on the surface of the carrier plate, coating a conductive adhesive on the surface of the semiconductor die or the surface of the carrier plate, wherein the conductive adhesive covers the first bonding pad and the second bonding pad, or the conductive adhesive covers the third bonding pad or the fourth bonding pad, the first bonding pad and the second bonding pad of the semiconductor die are respectively opposite to the third bonding pad and the fourth bonding pad of the carrier plate, and curing the conductive adhesive to form a space between the first bonding pad and the third bonding pad, And a current conducting region is formed between the second bonding pad and the fourth bonding pad, wherein the conductive adhesive comprises a conductive material and a non-conductive material.

Drawings

Fig. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;

fig. 2 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention;

fig. 3 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention;

fig. 4 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention;

fig. 5 is a perspective view of a semiconductor device according to a fourth embodiment of the present invention;

fig. 6 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention, taken along the cross-section of fig. 5 a-a';

FIG. 7 is a flow chart of a method of fabricating a semiconductor device of the present invention;

fig. 8 is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention;

fig. 9 is a cross-sectional view of a semiconductor device according to a sixth embodiment of the present invention;

fig. 10 is a top view of a light emitting module according to a first embodiment of the present invention;

fig. 11 is a sectional view of a light emitting module according to a second embodiment of the present invention;

FIG. 12 is a perspective view of a light emitting module according to a second embodiment of the present invention;

fig. 13 is a cross-sectional view of a semiconductor die in accordance with one embodiment of the present invention;

fig. 14 is a cross-sectional view of a semiconductor die of another embodiment of the invention.

Description of the symbols

100 semiconductor device

200. 300 light emitting module

1 semiconductor die, first light emitting die

11 surface of the laminated structure 111

112 first bonding pad 112a first bonding surface

112b side surface 112E first metal extension

112T first end 113 second bond pad

113E second metal extension 113T second end

114 first side surface 115 second side surface

116. 116' major light emitting surface

121 substrate 122 semiconductor stack

122a first semiconductor layer 122b second semiconductor layer

122c active layer 13 first channel

14 second channel 15 reflective layer

16 insulating layer

2 support plate

21 surface 22 third bonding pad

22a second bonding surface 23 fourth bonding pad

24 reflective wall 25 notch

26 reflective wall

3 conductive bonding layer

31 current conducting region 311 first conducting part

312 second conducting portion 32 current exclusion zone

321 first insulating part 322 and second insulating part

323 third insulating portion

4 second light emitting die

41 second wavelength conversion layer

5 third light emitting die

51 third wavelength conversion layer 52 first electrode

53 second electrode 54 metal line

6 transparent colloid

301 light guide plate

302 diffuser plate 301a light exit surface

303 reflective layer 304 support plate

d shortest distance

C1, C2 and C3 conductive material

I1, I2 and I3 non-conductive material

a1 first normal direction

a2 second normal direction

Theta 1 first angle

Height of H max

Maximum width of W

P1, P2 bonding pad

B light barrier wall

D area of notch

Detailed Description

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below. In the drawings or description, like or similar structures are referred to with the same reference numerals. It is to be noted that elements not shown in the drawings are well known to those skilled in the art.

Referring to fig. 1, which is a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention, the semiconductor device 100 includes a semiconductor die (die)1 and a carrier 2, and a conductive bonding layer 3 is disposed between the semiconductor die 1 and the carrier 2, so that the semiconductor die 1 is electrically connected to the carrier 2 through the conductive bonding layer 3. The semiconductor die 1 includes a first bonding pad 112 and a second bonding pad 113, the carrier 2 includes a third bonding pad 22 and a fourth bonding pad 23, and the conductive bonding layer 3 has a current-conducting region 31 and a current-isolating region 32, the current-conducting region 31 is disposed between the first bonding pad 112 and the third bonding pad 22, and between the second bonding pad 113 and the fourth bonding pad 23.

In detail, the semiconductor die 1 is formed by cutting a semiconductor chip (wafer) during the manufacturing process, and in order to meet the application requirement of the thin electronic product, the area of the semiconductor die 1 according to an embodiment of the present invention is controlled to be, for example, 150mil²And the first bonding pad 112 and the second bonding pad 113 have a shortest distance d less than 150 μm, for example, the shortest distance d is

In addition, the semiconductor die 1 may be a light emitting die, a power element or a solar cell. The semiconductor die 1 has a stacked structure 11, the stacked structure 11 has a surface 111, and the first bonding pads 112 and the second bonding pads 113 are disposed on the surface 111. The first bonding pad 112 has a first bonding surface 112a, the first bonding surface 112a is substantially parallel to the surface 111 of the semiconductor die 1, the first bonding surface 112a has a first normal direction a1 perpendicular to the first bonding surface 112a, generally, the first bonding surface 112a is a surface having a larger area than other surfaces of the first bonding pad 112, and the first bonding surface 112aThe outer surface of the

bonding pads

112 and 113 may be gold, silver, copper, tin, nickel or an alloy thereof. In one embodiment, semiconductor die 1 is a light emitting die and its operating current is less than 10 mA. The semiconductor die 1 of the present invention includes a bare die without a packaging material, a die with a conformal phosphor layer on the surface of the bare die, or a die with a packaging material formed by a chip-scale-package (CSP) technology.

Referring to fig. 1 again, the carrier 2 has a surface 21, the third bonding pad 22 and the fourth bonding pad 23 are disposed on the surface 21 of the carrier 2 in a protruding manner, the third bonding pad 22 has a second bonding surface 22a, the second bonding surface 22a is substantially parallel to the surface 21 of the carrier 2, the second bonding surface 22a has a second normal direction a2 perpendicular to the second bonding surface 22a, and generally, the second bonding surface 22a is a surface having a larger area than other surfaces of the third bonding pad 22, and the outer surface materials of the third bonding pad 22 and the fourth bonding pad 23 may be gold, silver, copper, tin, nickel or an alloy of the above metals. In one embodiment, after the carrier 2 and the semiconductor die 1 are bonded by the conductive bonding layer 3, the first normal direction a1 of the first bonding pad 112 is substantially parallel to the second normal direction a2 of the third bonding pad 22, the first bonding pad 112 and the second bonding pad 113 face the third bonding pad 22 and the fourth bonding pad 23, respectively, and the semiconductor die 1 and the carrier 2 are bonded by the conductive bonding layer 3, so that current flows through the semiconductor die 1 and the carrier 2. In detail, an angle is set between the first normal direction a1 and the second normal direction a2, and the angle is 160 to 200 degrees, preferably 180 degrees. In another embodiment, after the carrier 2 and the semiconductor die 1 are bonded by the conductive bonding layer 3, the distance between the surface 111 of the stacked structure 11 and the surface 21 of the carrier 2 is preferably less than 60 μm, so that the height of the formed semiconductor device 100 can be effectively reduced for small-sized or thin devices. The carrier 2 is used to electrically connect to an external power supply, for example, the carrier 2 may be a package carrier or a Printed Circuit Board (PCB), and the current flows to the conductive bonding layer 3 through the third bonding pad 22 and the fourth bonding pad 23 of the carrier 2 and is transmitted to the semiconductor die 1 through the first bonding pad 112 and the second bonding pad 113 to drive the semiconductor die 1.

Referring to fig. 2, it is a cross-sectional view of the semiconductor device 100 according to the first embodiment of the present invention, wherein the current conducting region 31 of the conductive bonding layer 3 is disposed between the first bonding pad 112 and the third bonding pad 22, and between the second bonding pad 113 and the fourth bonding pad 23, and the current isolating region 32 is disposed in the conductive bonding layer 3 except the current conducting region 31, for example, the current isolating region 32 of the present embodiment is located between the surface 111 of the stacked structure 11 without the first bonding pad 112 and the second bonding pad 113, and the surface 21 of the carrier 2 without the third bonding pad 22 and the fourth bonding pad 23; in other words, the current isolating region 32 is defined by the first bonding pad 112, the second bonding pad 113, the third bonding pad 22, the fourth bonding pad 23, the surface 111 of the semiconductor die 1, the surface 21 of the carrier 2, and the current conducting region 31, and the current isolating region 32 surrounds and covers the current conducting region 31. In the first embodiment, the surface 111 of the semiconductor die 1 of the semiconductor device 100 is substantially parallel to the surface 21 of the carrier 2, and the structure thereof is as described above, and in order to be applied to the field of thinning the semiconductor device, the thickness of the current-conducting region 31 is, for example, less than 40 μm, that is, the distance between the first bonding pad 112 and the third bonding pad 22 is, for example, less than 40 μm, or the distance between the second bonding pad 113 and the fourth bonding pad 23 is, for example, less than 40 μm, so as to reduce the overall thickness of the semiconductor device 100. The conductive bonding layer 3 comprises a conductive material C1 and a non-conductive material I1, the current-conducting region 31 and the current-isolating region 32 contain different contents of the conductive material C1, and in detail, the content of the conductive material C1 in the current-conducting region 31 is greater than the content of the conductive material C1 in the current-isolating region 32. For example, in the first embodiment shown in fig. 2, the content of the conductive material C1 in the current conducting region 31 is 7% to 75%, and preferably 15% to 30%, and the content of the conductive material C1 in the current isolating region 32 is 2% to 50%, and preferably 3% to 10%. It should be noted that the "content of the conductive material C1" referred to herein is defined by the content of the conductive material C1 in a specific region through a cross-sectional microscopic image of the semiconductor device 100. In detail, in a cross section of the semiconductor device 100, the percentage of the total area of the conductive material C1 in the representative area divided by the total area of the representative area is calculated as the "" content "" of the conductive material C1 in the specific area. This definition also applies to the "content of conductive material" described below.

Referring to fig. 2, the conductive material C1 according to the first embodiment of the present invention is in a spherical or granular shape. The content of the conductive material C1 in the current-conducting region 31 is 7% to 75%, so that the first bonding pad 112 and the third bonding pad 22 are electrically connected through the conductive material C1, and the second bonding pad 113 and the fourth bonding pad 23 are electrically connected through the conductive material C1, so as to transfer the current of the carrier board 2 to the semiconductor die 1. Furthermore, although the current isolation region 32 has a small amount of the conductive material C1, the content of the conductive material C1 in the current isolation region 32 is not enough to make the semiconductor die 1 and the carrier board 2 conduct current through the current isolation region 32, for example, the content of the conductive material C2 in the current isolation region 32 is 2% to 50%, preferably 3% to 10%; in detail, the first bonding pad 112 and the second bonding pad 113, the third bonding pad 22 and the fourth bonding pad 23, the first bonding pad 112 and the fourth bonding pad 23, and the second bonding pad 113 and the third bonding pad 22 cannot be electrically connected to each other through the limited conductive material C1, so that the semiconductor die 1 and the carrier 2 can be electrically isolated from each other in the current isolation region 32, and the current conduction between the first bonding pad 112 and the second bonding pad 113, or the current conduction between the third bonding pad 22 and the fourth bonding pad 23 to generate a short circuit can be effectively prevented.

Further, the conductive material C1 of the first embodiment has a metal or metal alloy with a melting point higher than 300 ℃, such as gold, copper, aluminum, nickel, silver, or an alloy of any two or more of gold, copper, aluminum, nickel, and silver; the non-conductive material I1 may be a thermosetting or thermoplastic polymer material, and may be selected from the group consisting of epoxy resin (epoxy), silicone resin (silicone), polymethyl methacrylate (PMMA), episulfide (episulfide), and the like. The non-conductive material I1 of the present embodiment is a thermosetting material and has a curing temperature, and the melting point of the conductive material C1 is higher than the curing temperature of the non-conductive material I1. In addition, the conductive material C1 of the present embodiment is granular and has a particle size (i.e., diameter), such as: is between 5 and 50 μm. The shortest distance d between the first bonding pad 112 and the second bonding pad 113 is preferably greater than or equal to twice the grain size, so as to avoid the conductive material C1 from being too large, and during the heating and/or pressing process in the manufacturing process, the conductive material C1 contacts the first bonding pad 112 and the second bonding pad 113, so that the current is conducted between the first bonding pad 112 and the second bonding pad 113 to cause short circuit. As mentioned above, the shortest distance d is not more than 150 μm to meet the application requirement of thinning the electronic product. The conductive material C1 is, for example, a core-shell (core-shell) structure, and in an embodiment, the conductive material C1 includes a conductive core and an insulating layer covering the conductive core, wherein the insulating layer may be made of the same material as or different from the non-conductive material I1, which is not limited herein; in another embodiment, the conductive material C1 includes an insulating core and a conductive layer wrapped around the insulating core.

Referring to fig. 3, which is a cross-sectional view of the semiconductor device 100 according to the second embodiment of the present invention, the conductive bonding layer 3 of this embodiment includes a conductive material C2 and a non-conductive material I2, the current-conducting region 31 and the current-blocking region 32 contain different contents of conductive material C2, the content of the conductive material C2 in the current-conducting region 31 is greater than 75% or preferably does not contain the non-conductive material I2, the content of the conductive material C2 in the current-blocking region 32 is less than 40%, the current-blocking region 32 contains trace amount of conductive material C2, the content of the conductive material C2 in the current-blocking region 32 is not 0, for example, the content of the conductive material C2 in the current-blocking region 32 is 0.1% to 40%, preferably 2% to 10%; the content of the non-conductive material I2 in the current isolation region 32 is greater than 60%, preferably 60% to 99.9%, and more preferably 90% to 98%. In one embodiment, the current isolation region 32 has 10% to 40% of the conductive material C2 and 60% to 90% of the non-conductive material I2, and preferably, the current isolation region 32 has 20% to 30% of the conductive material C2 and 70% to 80% of the non-conductive material I2. It should be noted that, the components and their connection relationship of the semiconductor device 100 of the present embodiment are similar to those of the first embodiment shown in fig. 2, however, the content of the conductive material C2 in the current isolating region 32 of the present embodiment is lower than that of the conductive material C1 in the current isolating region 32 of the first embodiment, so that the current conduction path in the conductive bonding layer 3 is less prone to pass through the current isolating region 32, the distribution of the conductive material C2 in the current isolating region 32 shown in fig. 3 is more dispersed than the distribution of the conductive material C1 in the current isolating region 32 shown in fig. 2, therefore, the first bonding pad 112 and the second bonding pad 113, the third bonding pad 22 and the fourth bonding pad 23, the first bonding pad 112 and the fourth bonding pad 23, and the second bonding pad 113 and the third bonding pad 22 cannot contact each other through a small amount of the conductive material C2, so the insulating effect of the current blocking region 32 in the second embodiment is better.

More specifically, the conductive material C2 in the second embodiment has a metal or metal alloy with a melting point lower than 300 ℃, such as bismuth, tin, indium or an alloy consisting of any two or more of bismuth, tin, silver and indium, such as a tin-bismuth-silver alloy, and when the conductive material C2 is a metal alloy, the melting point of the conductive material C2 means the eutectic temperature of the metal alloy; the non-conductive material I2 is a thermosetting polymer material, and can be selected from the group consisting of epoxy resin (epoxy), silicone resin (silicone), polymethyl methacrylate (PMMA), and episulfide (epistilefide). The non-conductive material I2 has a curing temperature, and the melting point of the conductive material C2 of the present embodiment is lower than the curing temperature of the non-conductive material I2. In the preparation of the semiconductor device 100 of the present invention, a heating step is required, and a detailed preparation method will be described later, but before the conductive bonding layer 3 is heated, the conductive material C2 is granular in the conductive bonding layer 3 and has a particle size, for example: between 5 and 50 μm, the shortest distance d between the first bonding pad 112 and the second bonding pad 113 is preferably greater than or equal to two times the grain size and not greater than 150 μm, for the reasons mentioned above. In one embodiment, the conductive material C2 has a first metal and a second metal, and in detail, the composition of a single particle in the conductive material C2 of fig. 3 includes the first metal and the second metal, and the melting point of the first metal is lower than that of the second metal, and the content of the first metal in the composition of the single particle of the conductive material C2 is less than that of the second metal. For example, the single-particle conductive material C2 includes 42 wt% of a first metal, such as tin (melting point about 231 ℃), and 58 wt% of a second metal, such as bismuth (melting point about 271 ℃), and the conductive material C2 has a eutectic temperature of about 139 ℃; in another embodiment, the conductive material C2 is an alloy of tin, silver and copper, and has a eutectic temperature of 217 ℃; in another embodiment, the conductive material C2 is a core-shell structure including an insulating core and a metal layer sequentially wrapped around the insulating core. The material of the insulating core may be the same as or different from that of the non-conductive material I2, which is not limited herein.

It is noted that in the semiconductor device 100 of the second embodiment of fig. 3, the conductive material C2 of the current-conducting region 31 is in a bulk state, and the conductive material C2 of the current-isolating region 32 is in a granular state; however, in the semiconductor device 100 of the first embodiment shown in fig. 2, the conductive material C1 in the current-conducting region 31 and the current-isolating region 32 are granular. In detail, in the second embodiment, the conductive material C2 of the current-conduction region 32 is continuously distributed between the first bonding pad 22 and the third bonding pad 112, and the second bonding pad 23 and the fourth bonding pad 113, and is arranged more closely and has fewer voids or substantially no voids than the conductive material C1 of the current-conduction region 32 of the first embodiment; in contrast, compared to the second embodiment in which the bulk conductive material C2 is formed by co-melting the granular conductive material C2 under heat and/or pressure so as to have a granular shape without the original conductive material C2, the conductive material C2 of the current conducting region 31 is continuously distributed between the

bonding pads

112 and 22 and between the

bonding pads

113 and 23, since the current conducting region 32 of the first embodiment is formed by the conductive materials C1 physically contacting each other, the current conducting region 32 of the first embodiment has a plurality of voids formed by the conductive materials C1 not being co-melted. The difference between the shapes of the conductive materials C1 and C2 in the two embodiments is due to the difference between the materials of the conductive bonding layer 3, so that the distribution mechanisms of the conductive materials C1 and C2 in the preparation of the semiconductor device 100 are obviously different in the two embodiments, and the distribution mechanisms will be described in detail later.

Referring to fig. 4, a cross-sectional view of a semiconductor device 100 according to a third embodiment of the present invention is shown, in which the semiconductor device 100 of the present embodimentThe components and their combination are similar to those of the semiconductor device 100 of the second embodiment, except that the semiconductor device 100 of this embodiment further includes a reflective wall 24 protruding from the surface 21 of the carrier 2, the reflective wall 24 surrounds the third bonding pad 22 and the fourth bonding pad 23, so that a recess 25 is defined by the reflective wall 24 and the surface 21 of the carrier 2, and the semiconductor die 1 is disposed in the recess 25. When the semiconductor die 1 is a light emitting die (the light emitting die may be a light emitting diode, for example), the reflective wall 24 has a reflectivity higher than 80% for light emitted by the light emitting die, the reflective wall 24 may be made of a material or a structure thereof and has a high reflectivity for light, or the reflective wall 24 may be coated with a reflective material on a surface facing the recess 25 to generate a high reflectivity for light emitted by the light emitting die, so as to concentrate light emitted by the light emitting die and increase the illumination (Luminance) of the light emitting die. The material of the reflective wall 24 is, for example, a silicon gel containing a metal, an alloy or a mixture of reflective particles, such as silicon oxide (SiO)_x) Titanium oxide (TiO)_x) Or Boron Nitride (BN).

Referring to fig. 5, which is a perspective view of a semiconductor device 100 according to a fourth embodiment of the present invention, the semiconductor device 100 according to the fourth embodiment includes a semiconductor die 1 and a carrier 2, and a conductive bonding layer 3 is disposed between the semiconductor die 1 and the carrier 2, so that a current flows between the semiconductor die 1 and the carrier 2 through the conductive bonding layer 3. The semiconductor die 1 includes a surface 111 and a first bonding pad 112 and a second bonding pad 113 disposed on the surface 111, the carrier 2 includes a surface 21 and a third bonding pad 22 and a fourth bonding pad 23 disposed on the surface 21, the conductive bonding layer 3 has a current-conducting region 31 and a current-isolating region 32, the current-conducting region 31 is disposed between the first bonding pad 112 and the third bonding pad 22 and between the second bonding pad 113 and the fourth bonding pad 23, and the current-isolating region 32 is disposed outside the current-conducting region 31. The components and their connections in the semiconductor device 100 of the fourth embodiment are substantially the same as those in the second embodiment, for example: in the semiconductor device 100 of the fourth embodiment, the first bonding pad 112 has a first bonding surface 112a, the third bonding pad 22 has a second bonding surface 22a, the first bonding surface 112a and the second bonding surface 22a are substantially parallel to the surface 111 of the semiconductor die 1 and the surface 21 of the carrier 2, respectively, and the current conducting region 31 is disposed between the first bonding surface 112a and the second bonding surface 22 a; however, the difference between the present embodiment and the second embodiment is the corresponding relationship between the first bonding surface 112a of the first bonding pad 112 of the semiconductor die 1 and the second bonding surface 22a of the third bonding pad 22 of the carrier board 2. In detail, in the second embodiment, the surface 11 of the semiconductor die 1 is substantially parallel to the surface 21 of the carrier board 2, and the first normal direction a1 of the first bonding pad 112 is substantially parallel to the second normal direction a2 of the third bonding pad 22, however, in the fourth embodiment, the surface 111 of the semiconductor die 1 is not parallel to the surface 21 of the carrier board 2, or the surface 111 of the semiconductor die 1 is perpendicular to the surface 21 of the carrier board 2, so that the first bonding surface 112a and the second bonding surface 22a have different corresponding relationships from the second embodiment. Referring to fig. 6, the first bonding surface 112a of the first bonding pad 112 has a first normal direction a1, the second bonding surface 22a of the third bonding pad 22 has a second normal direction a2, and the first normal direction a1 and the second normal direction a2 form a first angle θ 1, the first angle θ 1 is not 180 degrees, for example, the first angle θ 1 is about 60 to 150 degrees, preferably, the first angle θ 1 is about 80 to 100 degrees, and more preferably, the first angle θ 1 is about 90 degrees. Even though the surface 111 of the semiconductor die 1 and the surface 21 of the carrier 2 are not parallel and the first normal direction a1 and the second normal direction a2 form the above-mentioned included angle, the semiconductor device 100 of the present embodiment can also form the conductive bonding layer 3 between the semiconductor die 1 and the carrier 2, so that the current can be conducted between the first bonding pad 112 and the third bonding pad 22, and between the second bonding pad 113 and the fourth bonding pad 23, and the thickness of the semiconductor device 100 can be effectively reduced, and is suitable for the application range of the side backlight module with strict limitation on the volume of the semiconductor device 100.

Referring to fig. 5 and fig. 6, a perspective view of a semiconductor device 100 according to a fourth embodiment of the present invention and a cross-sectional view of the semiconductor device 100 taken along a direction a-a' in fig. 5 are shown. In detail, the semiconductor die 1 of the present embodiment has a first side surface 114 and a second side surface 115 opposite to each other, the first side surface 114 and the second side surface 115 are connected to the surface 111, wherein the first side surface114 is further away from the carrier plate 2 than the second side surface 115, and the second side surface 115 faces the surface 21 connected to the carrier plate 2, the semiconductor die 1 further has a main light emitting surface 116 connected to the first side surface 114 and the second side surface 115. The conductive bonding layer 3 is disposed between the surface 21 of the carrier 2 and the surface 111 of the semiconductor die 1, wherein the current conducting region 31 of the conductive bonding layer 3 is disposed between the first bonding pad 112 and the third bonding pad 22, and between the second bonding pad 113 and the fourth bonding pad 23, and the current blocking region 32 of the embodiment is disposed outside the current conducting region 31 of the conductive bonding layer 3, and preferably, the current blocking region 32 covers the outside of the current conducting region 31. Referring to fig. 6, the current conducting region 31 has, for example, a first conducting portion 311 and a second conducting portion 312, the first conducting portion 311 is disposed between the first bonding pad 112 and the third bonding pad 22, and between the second bonding pad 113 and the fourth bonding pad 23, the second conducting portion 312 is disposed between a side surface 112b of the first bonding pad 112 and the third bonding pad 22, and between a side surface of the second bonding pad 113 and the fourth bonding pad 23 (not shown), wherein the side surface 112b of the first bonding pad 112 is connected to the first bonding surface 112a and the second side surface 115, and preferably, the first conducting portion 311 is connected to the second conducting portion 312; the current isolation region 32 has, for example, a first insulating portion 321, a second insulating portion 322 and a third insulating portion 323, the first insulating portion 321 is disposed on the surface 111 not provided with the first bonding pad 112 and the second bonding pad 113, the surface 21 not provided with the third bonding pad 22 and the fourth bonding pad 23, and between the current conducting regions 31, the second insulating portion 322 covers the outer side of the current conducting region 31 (see fig. 6 for details), the third insulating portion 323 is disposed between the second side surface 115 and the second bonding surface 22a and is adjacent to the second conducting portion 312, and preferably, the first insulating portion 321, the second insulating portion 322 and the third insulating portion 323 of the current isolation region 32 are connected. As shown in the second embodiment, the conductive bonding layer 3 includes a conductive material C3 and a non-conductive material I3, the current-conducting region 31 and the current-isolating region 32 have different contents of the conductive material C3, and the content of the conductive material C3 in the current-conducting region 31 is greater than that in the current-isolating region 32, in one embodiment, the conductive material C3 in the current-conducting region 31 is greater than that in the current-isolating region 32The content is greater than 75%, and the content of the conductive material C3 in the current isolation region 32 is preferably less than 40%, for example, the content of the conductive material C3 in the current isolation region 32 is 0.1% to 40%, or 2% to 10%, and the conductive material C3 of this embodiment is preferably the same as the conductive material C2 of the second embodiment; the non-conductive material I3 of the present embodiment is preferably the same as the non-conductive material I2 of the second embodiment. Fig. 6 shows that the junction of current-conducting region 31 and first bonding pad 112 or second bonding pad 113 of semiconductor die 1 has a maximum height H, and the junction of current-conducting region 31 and third bonding pad 22 or fourth bonding pad 23 of carrier 21 has a maximum width W, and in one embodiment, the maximum height H is

The width W is 150 to 300 μm. The content of the non-conductive material in the first insulating portion 321, the second insulating portion 322, and the third insulating portion 323 is greater than 60%, preferably 60% to 99.9%, and more preferably 90% to 98%. In one embodiment of the present invention, the second insulating portion 322 and the third insulating portion 323 do not include the conductive material C3. In an embodiment of the invention, the second conductive portion 312 does not include the non-conductive material I3.

Referring to fig. 7, which is a flow chart of a method for manufacturing the semiconductor device 100 of the present invention, the method for manufacturing the semiconductor device of the present invention includes the following steps:

step a, preparing a semiconductor die 1, wherein the semiconductor die 1 comprises a laminated structure 11, the laminated structure 11 has a surface 111, the surface 111 is provided with a first bonding pad 112 and a second bonding pad 113, and the shortest distance between the first bonding pad 112 and the second bonding pad 113 is less than 150 μm;

step b, preparing a carrier 2, wherein the carrier 2 has a surface 21, and the surface 21 is provided with a third bonding pad 22 and a fourth bonding pad 23;

step c, coating a conductive adhesive on the surface 111 of the semiconductor die 1 or the surface 21 of the carrier 2, wherein the conductive adhesive covers the first bonding pads 112 and the second bonding pads 113, or covers the third bonding pads 22 and the fourth bonding pads 23 with the conductive adhesive;

step d, aligning the first bonding pads 112 and the second bonding pads 113 of the semiconductor die 1 to the third bonding pads 22 and the fourth bonding pads 23 of the carrier 2, respectively;

step e, curing the conductive adhesive to form a conductive bonding layer 3 including a current-conducting region 31 and a current-isolating region 32 between the

surfaces

111 and 21, wherein the current-conducting region 31 is disposed between the first bonding pad 112 and the third bonding pad 22, and between the second bonding pad 113 and the fourth bonding pad 23, and the current-isolating region 32 is formed between the

surfaces

111 and 21 and outside the current-conducting region 31.

In the step c, the conductive adhesive is preferably used to cover the first bonding pads 112, the second bonding pads 113 and the surface 111 of the semiconductor die 1 between the first bonding pads 112 and the second bonding pads 113 in a continuous block, or the conductive adhesive is preferably used to cover the third bonding pads 22, the fourth bonding pads 23 and the surface 21 of the carrier 2 between the third bonding pads 22 and the fourth bonding pads 23. Covering the area with the continuous block has the advantage of simple manufacturing process, and is particularly suitable for the manufacturing process requirement that the shortest distance d between the first bonding pad 112 and the second bonding pad 113 is reduced to 15-150 μm in order to make the semiconductor device 100 to meet the application requirement of thinning. In the embodiment of the present invention, in the step c, the conductive paste may be coated on the first bonding pads 112 and the second bonding pads 113 in the form of separate blocks by using a steel plate printing method with openings, and the allowable error of alignment between the openings of the steel plate and the first bonding pads 112 or the second bonding pads 113 is relatively large, so that yield loss caused by poor alignment can be effectively reduced, and thus, when the method is applied to the preparation of the semiconductor device 100 with miniaturized size, the yield of the product can be improved. In addition, the curing of the conductive adhesive in step e can be achieved by many ways, such as: heating, cooling or adding a curing reaction triggering factor, and if necessary, applying an appropriate physical quantity (e.g., pressure) to the conductive adhesive, so long as the conductive adhesive is cured to form the current conducting region 31 in the above region, is within the scope of the present invention.

In the method of manufacturing the semiconductor device 100 according to the first embodiment of the present invention, step e is to cure the conductive paste or the conductive film by heating and pressing simultaneously. Referring to fig. 2 and 7, in the semiconductor device 100 according to the first embodiment of the present invention, the conductive paste is cured to form the current-conducting region 31 and the current-blocking region 32, such that the content of the conductive material C1 in the current-conducting region 31 is 7% to 75%, and the content of the conductive material C1 in the current-blocking region 32 is 2% to 50%. In brief, the non-conductive material I1 in this embodiment is a thermosetting material and has a curing temperature, and the melting point of the conductive material C1 is higher than the curing temperature of the non-conductive material I1, and preferably, the curing temperature of the non-conductive material I1 is higher than the room temperature, so that the conductive adhesive can be in a flowable state at room temperature. Before the conductive adhesive is cured, uniformly mixing a conductive material C1 with a non-conductive material I1; then, pressing to make the surface 111 of the semiconductor die 1 and the surface 21 of the carrier board 2 approach each other, and at this time, since the distance between the first bonding pad 112 and the third bonding pad 22 is smaller than the distance from the surface 111 of the semiconductor die 1 to the surface 21 of the carrier board 2, or the distance between the second bonding pad 113 and the fourth bonding pad 23 is smaller than the distance from the surface 111 of the semiconductor die 1 to the surface 21 of the carrier board 2, the conductive adhesive in the current conducting area 31 is firstly sandwiched by the bonding pads 112, 22, 113, and 23 of the carrier board 2 aligned with each other by applying pressure, so as to reduce the volume, and the bonding pads 112, 22, 113, and 23 aligned with each other generate a current conducting path due to the conductive material C1 contacting therein, thereby forming the current conducting area 31; meanwhile, since the current blocking region 32 is not provided with the bonding pads 112, 113, 22 and 23 protruding from the surfaces 111 and 21, and thus has a larger space compared to the current conducting region 31, the conductive material C1 is dispersed in the current blocking region 32 without forming a continuous current path with the bonding pads 112, 113, 22 and 23 so that current cannot be conducted in the region, thereby forming the current blocking region 32. When the conductive paste is heated to a temperature higher than the curing temperature of the non-conductive material I1, the non-conductive material I1 is cured to confine the conductive material C1, thereby fixing the distribution of the conductive material C1 in the current-conducting region 31 and the current-isolating region 32. In another embodiment, the conductive paste can be replaced by a conductive film (not shown) that is solid at room temperature, the conductive film includes a conductive material and a non-conductive material, however, the difference between the conductive film and the conductive paste is: the non-conductive material in the conductive film is a thermoplastic material and has a melting point higher than room temperature, so that the conductive film is already formed into a solid sheet at room temperature, and is further heated to melt the non-conductive material, and is pressurized to bond the first bonding pad 22, the third bonding pad 112, the second bonding pad 23, and the fourth bonding pad 113, and a current conducting path is formed between the current conducting regions 31, and then the temperature is reduced to make the temperature of the non-conductive material lower than the melting point, so that the conductive film is solidified again, thereby fixing the distribution of the conductive material in the current conducting regions 31 and the current isolating regions 32, wherein the melting point of the conductive film is, for example, 140 ℃ to 200 ℃. In addition, the current isolation region 32 is filled with the non-conductive material I1, so that the current is blocked to avoid the occurrence of an unexpected conduction, and the semiconductor device 100 can also increase the structural strength of the semiconductor device 100 by the non-conductive material I1 filled in the current isolation region 32, thereby avoiding the semiconductor die 1 from being easily cracked or damaged by an external stress due to the gaps between the

bonding pads

112, 113, 22, 23 in a subsequent packaging process. In addition, in the case that the conductive material C1 is a core-shell structure including a conductive core and an insulating layer covering the conductive core, the process of curing the conductive adhesive enables the insulating layer on the surface of the conductive material C1 to be broken by compression, so that the conductive core is exposed and contacts with the first bonding pad 112 and the second bonding pad 22 to conduct current, thereby not only enabling the conductive material C1 to be uniformly dispersed in the non-conductive material I1 before curing the conductive adhesive, but also further avoiding the occurrence of unintended conduction in the non-pressurized horizontal direction when curing the conductive adhesive.

In the method for manufacturing the semiconductor device 100 according to the second embodiment of the present invention, wherein the step e is to cure the conductive adhesive by heating, a pressing process may be optionally added to the manufacturing method. Referring to fig. 3 and 7, in the second embodiment of the present invention, the conductive paste includes a conductive material C2 and a non-conductive material I2, the materials of the conductive material C2 and the non-conductive material I2 are as described above, the melting point temperature of the conductive material C2 is lower than the curing temperature of the non-conductive material I2, and the conductive paste of the present embodiment forms the current conducting region 31 and the current isolating region 32 after the conductive paste is cured by the material characteristics. In detail, before curing the conductive adhesive, the conductive material C2 is uniformly mixed with the non-conductive material I2, and the conductive material C2 is in a granular shape, and then the conductive adhesive is coated between the surfaces 111, 21, and preferably covers the first bonding pads 112, the second bonding pads 113 and the surface 111 of the semiconductor die 1 therebetween in a continuous block, or covers the third bonding pads 22, the fourth bonding pads 23 and the surface 21 of the carrier board 2 therebetween in a continuous block; then, a heat is applied to heat the conductive adhesive to a temperature higher than the melting point of the conductive material C2, the heating temperature in this embodiment is between 140 to 180 ℃, since the materials of the bonding pads 112, 113, 22, 23 and the conductive material C2 are all metal or alloy materials, and the conductive material C2 is selected to have excellent surface wetting property (wetting property) for the materials of the bonding pads 112, 113, 22, 23, when the heating temperature reaches the melting point of the conductive material C2 but does not reach the solidification temperature of the non-conductive material I2, the conductive material C2 can freely flow in the conductive adhesive, and under the influence of the surface wetting property, the conductive material C2 originally located in the current isolation region 23 is attracted and concentrated between the first bonding pad 112 and the third bonding pad 22, and between the second bonding pad 113 and the fourth bonding pad 23, and the conductive material C2 originally in a granular shape before solidification is gathered together to form a block due to the melting flow, so that the content of the conductive material C2 in the current conduction region 31 is higher than 75%; however, since the conductive material C2 flows and gathers to the current-conducting region 31 on the surfaces 111 and 21 without the bonding pads 112, 113, 22 and 23, the content of the conductive material C2 in the region outside the current-conducting region 31 is relatively low, the current-isolating region 32 in the semiconductor device 100 of the present embodiment only includes 0.1% -40% of the conductive material C2, and the rest is the non-conductive material I2. Then, the conductive adhesive is heated to a temperature higher than the curing temperature of the non-conductive material I2 to cure the non-conductive material I2, at this time, the conductive material C2 is gathered between the first bonding pad 112 and the third bonding pad 22, and between the second bonding pad 113 and the fourth bonding pad 23, the cured non-conductive material I2 can limit the flowing region of the conductive material C2 which still appears molten, so that the distribution of the conductive material C2 in the current conducting region 31 and the current isolating region 32 is fixed.

Referring to fig. 6 and 7, in the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention, step c preferably covers the first bonding pads 112 and the second bonding pads 113 of the semiconductor die 1 and the surface 111 of the semiconductor die 1 therebetween with a continuous block, or covers the third bonding pads 22 and the fourth bonding pads 23 of the carrier 2 and the surface 21 of the carrier 2 therebetween with a continuous block; step d, the semiconductor die 1 is positioned on the carrier 2 in a direction that the second side surface 115 faces the surface 21 of the carrier 2, so that the conductive adhesive covers the second side surface 115, and the side surfaces of the first bonding pad 112 and the second bonding pad 113 are correspondingly bonded to the surfaces of the third bonding pad 22 and the fourth bonding pad 23 of the carrier 21, wherein the first normal direction a1 of the first bonding surface 112a and the second normal direction a2 of the second bonding surface 22a sandwich a first angle θ 1, and the conductive adhesive covers between the second side surface 115 of the semiconductor die 1 and the carrier 21; step e is to heat the conductive adhesive to 140-180 ℃ by heating to cure the conductive adhesive, and the conductive adhesive of the present embodiment includes a conductive material C3 and a non-conductive material I3, which are preferably the same as the conductive adhesive of the second embodiment, and are not described herein again. Similarly to the second embodiment, since the surface wetting characteristics of the conductive material C3 and the

bonding pads

112, 113, 22 and 23 are good, the conductive particles in the conductive material C3 are aggregated into a block after being heated and melted and distributed between the first bonding pad 112 and the third bonding pad 22 and between the second bonding pad 113 and the fourth bonding pad 23; then, the conductive paste is heated to a temperature higher than the curing temperature of the non-conductive material I3 to cure the non-conductive material I3 so that most of the conductive material C3 is confined between the first bonding pad 112 and the third bonding pad 22 and between the second bonding pad 113 and the fourth bonding pad 23 to form the current-carrying region 32.

Referring to fig. 8, which is a cross-sectional view of a semiconductor device 100 according to a fifth embodiment of the present invention, the semiconductor device 100 includes a plurality of semiconductor dies 1 and a carrier 2, wherein the plurality of semiconductor dies 1 are light emitting dies. In detail, the semiconductor device 100 includes a carrier 2, a first light emitting die 1, a second light emitting die 4, a third light emitting die 5 and a reflective wall 26, the reflective wall 26 is disposed on the surface 21 of the carrier 2 and has a similar light reflection characteristic to the reflective wall 24, and the reflective wall 26 surrounds the first light emitting die 1, the second light emitting die 4 and the third light emitting die 5. The first light emitting die 1, the second light emitting die 4 and the third light emitting die 5 are similar to the semiconductor die 1 of the first and second embodiments, and three sets of third bonding pads 22 and fourth bonding pads 23 are disposed on the surface 21 of the carrier 2, wherein two

bonding pads

112, 113 of the first light emitting die 1 are correspondingly bonded to one set of

bonding pads

22, 23 on the surface 21 of the carrier 2 through the bonding structure and the method disclosed in the first or second embodiments, the second light emitting die 4 and the third light emitting die 5 are also disposed on the surface 21 of the carrier 2, the two bonding pads of the second light emitting die 4 and the third light emitting die 5 can be selectively bonded to the corresponding two sets of bonding pads on the carrier 2 respectively through the bonding structure and the method disclosed in the first and second embodiments, or bonded to the other two sets of bonding pads of the carrier 2 through wire bonding, the first light emitting die 1, the second light emitting die 4 and the third light emitting die 5 are electrically connected to the carrier 2. When current flows between the carrier plate 2 and the first light emitting die 1, the second light emitting die 4 and the third light emitting die 5, the first light emitting die 1, the second light emitting die 4 and the third light emitting die 5 respectively emit a first light, a second light and a third light, and the first light, the second light and the third light are mixed to form white light. The second light emitting die 4 shown in fig. 8 includes a first light emitting die 1 emitting the first light and a second wavelength conversion layer 41 formed on the light emitting surface of the corresponding first light emitting die 1, the third light emitting die 5 includes a first light emitting die 1 emitting the first light and a third wavelength conversion layer 51 formed on the light emitting surface of the corresponding first light emitting die 1, and the first light emitting die 1, the second light emitting die 4 and the third light emitting die 5 are all bonded to the carrier 2 by conductive glue. The first light emitting die 1, the second light emitting die 4 and the third light emitting die 5 preferably do not have a substrate structure, and are flip-chip bonded to the carrier 2, wherein the detailed structure of the first light emitting die 1 will be described later. In one embodiment, the first light emitted by the first light emitting die 1 is blue light; the second wavelength converting layer 41 of the second light emitting die 4 comprises a material capable of being excited by blue light and converted to green light, such as a phosphor or quantum dots, and the second light is green light; the third wavelength conversion layer 51 of the third light emitting die 5 includes a material capable of being excited by blue light and converted into red light, such as phosphor or quantum dots, and the third light is red light. It should be noted that the semiconductor device 100 may optionally include light blocking walls B surrounding the second light emitting die 4 and the third light emitting die 5, specifically, the light blocking walls B surrounding the side wall of the second light emitting die 4 and the second wavelength conversion layer 41, and the side wall of the third light emitting die 5 and the third wavelength conversion layer 51, so as to increase the ratio of wavelength conversion of the light emitted by the second light emitting die 4 and the third light emitting die 5 through the second wavelength conversion layer 41 and the third wavelength conversion layer 51, and prevent the first light leaking from the side of the second light emitting die 4 from exciting the adjacent third light emitting die 5, or prevent the first light leaking from the side of the third light emitting die 5 from exciting the adjacent second light emitting die 4 to mix with the undesired light.

Fig. 9 is a cross-sectional view of a semiconductor device 100 according to a sixth embodiment of the present invention. In the present embodiment, similar to fig. 8, the first light emitting die 1 and the second light emitting die 4 of the semiconductor device 100 are bonded to the carrier 2 by the bonding structure and the method thereof disclosed in the first and second embodiments, and the difference from the embodiment shown in fig. 8 is that the third light emitting die 5 of the present embodiment is a vertical structure and has a first electrode 52 and a second electrode 53 disposed on two opposite sides of the third light emitting die 5, the second electrode 53 of the third light emitting die 5 can be bonded to one of the bonding pads P1 on the carrier 2 by the bonding structure and the method thereof disclosed in the first and second embodiments, and the first electrode 52 is electrically connected to one of the bonding pads P2 on the carrier 2 by a metal wire 54 in a face-up wire bonding manner; alternatively, in another embodiment, when the third light emitting die 5 is a horizontal structure and has the first electrode 52 and the second electrode 53 (not shown) located on the same side of the third light emitting die 5, the first electrode 51 and the second electrode 52 of the third light emitting die 5 can be electrically connected to two corresponding bonding pads on the carrier 2 by two metal wires (not shown) through a positive wire bonding method. The first light emitting die 1, the second light emitting die 4 and the third light emitting die 5 respectively emit a first light, a second light and a third light, and the first light, the second light and the third light are mixed to form a white light, the second light emitting die 4 includes the first light emitting die 1 emitting the first light and a second wavelength conversion layer formed on the light emitting surface of the corresponding first light emitting die 1, and the third light emitting die does not have the third wavelength conversion layer 51 and can emit the third light, wherein the first light is, for example, a blue light, the second light is, for example, a green light, and the third light is, for example, a red light. In an embodiment, a recess defined by the reflective wall 26 and the surface 21 of the carrier 2 is filled with a transparent encapsulant 6 to protect the light emitting dies 1, 4, and 5, and the transparent encapsulant 6 may include, but is not limited to, epoxy, acryl, silicone, or a combination thereof. In another embodiment, the material of the transparent adhesive 6 includes the same material as the non-conductive materials I1, I2 in the conductive adhesive, so that the transparent adhesive 6 and the non-conductive materials I1, I2 have the same thermal expansion coefficient, thereby preventing the semiconductor device 100 from causing stress to the

light emitting dice

1, 4, 5 due to thermal expansion and contraction during operation, and affecting the bonding stability between the carrier board 2 and the

light emitting dice

1, 4, 5.

Referring to fig. 10, which is a top view of a light emitting module 200 according to a first embodiment of the present invention, the light emitting module 200 includes a plurality of semiconductor devices 100 as shown in fig. 8 or 9, wherein in an embodiment of the present invention, the plurality of semiconductor devices 100 have a common carrier 2 and are arranged in a two-dimensional matrix, wherein the plurality of semiconductor devices 100 are connected to each other by a reflective wall 26, a shape of a recess surrounded by the reflective wall 26 of each semiconductor device 100 may be a circle as in the present embodiment, or may be adjusted to be a square or a long bar or other shape according to display requirements, a single recess surrounded by the reflective wall 26 has a recess area D, and the recess area is preferably between 1 mm and 20mm². The light emitting module 200 may be further applied toDisplay devices such as television screens, cell phone screens, billboards or sports boards. The light emitting module 200 includes a plurality of semiconductor devices 100 as an array of pixels, and the number, color, and arrangement of the light emitting dice in the semiconductor devices 100 and the distance between the semiconductor devices 100 all affect the visual characteristics of a user when viewing, for example: the display device using the smaller semiconductor device 100 has a larger resolution than the larger semiconductor device 100 can accommodate a larger number of semiconductor devices 100 per unit area.

Fig. 11 and 12 show a light emitting module 300 according to a second embodiment of the invention, such as a side-type light emitting module, including the semiconductor device 100 according to the fourth embodiment shown in fig. 5 and 6, a light guide plate 301 and a diffusion plate 302, wherein the light emitting module 300 may include a plurality of semiconductor devices 100, the main light emitting surface 116 of the semiconductor die 1 is opposite to the surface 111 having the first electrode pad 112 and the second electrode pad 113, and the main light emitting surface 116 is disposed between the first side surface 114 and the second side surface 115; the light guide plate 301 has a light-emitting surface 301a and two opposite side surfaces 301b connected to the light-emitting surface 301a, and the plurality of semiconductor devices 100 are respectively disposed in a direction from the main light-emitting surface 116 of the semiconductor die 1 toward the two side surfaces 301b of the light guide plate 301; the diffusion plate 302 is disposed on the light-emitting surface 301a of the light guide plate 301. The light emitted from the semiconductor die 1 is emitted from the main light-emitting surface 116 to the side 301b of the light guide plate 301, and the light is guided by the light guide plate 301 to the light-emitting surface 301a and enters the diffusion plate 302, so that the light is uniformly emitted through the diffusion plate 302. The light emitting module 300 further preferably includes a reflective layer 303 bonded to a surface of the light guide plate 301 opposite to the light exit surface 301a, so that light is reflected by the reflective layer 303 and guided into the diffusion plate 302, thereby increasing light uniformity of the light emitting module 300. The light emitting module 300 may further include a supporting plate 304, such that the reflective layer 303, the light guide plate 301, the diffusion plate 302 and the semiconductor device 100 are disposed on the supporting plate 304. Fig. 12 is a perspective view of the light emitting module 300 of fig. 11, the semiconductor device 100 includes a plurality of semiconductor dies 1 disposed on a carrier plate 2, and the plurality of semiconductor dies 1 are arranged in a one-dimensional array along a side 301b of the light guide plate 301, but the number and arrangement of the semiconductor dies 1 of fig. 12 are merely exemplary and not limited thereto.

Referring to fig. 13, which is a cross-sectional view of a semiconductor die 1 according to an embodiment of the present invention, the semiconductor die 1 is a flip-chip type light emitting device, and the semiconductor die 1 of the present embodiment can be used as the semiconductor die 1 of fig. 1 to 6, the first light emitting die 1 and the second light emitting die 4 of fig. 8 to 9, and the third light emitting die 5 of fig. 8. In detail, the semiconductor die 1 includes a stacked structure 11, a first bonding pad 112 and a second bonding pad 113 disposed on a surface 111 of the stacked structure 11, and the stacked structure 11 includes a substrate 121 and a semiconductor stack 122, wherein the substrate 121 is used for supporting and carrying the semiconductor stack 122, and the first bonding pad 112 and the second bonding pad 113 are disposed on the same side of the semiconductor stack 122, and are of a horizontal (horizontal) type semiconductor structure. In one embodiment, the semiconductor stack 122 is disposed between the

bonding pads

112, 113 and the substrate 121, and the substrate 121 is a transparent substrate, such as but not limited to a transparent material such as sapphire (sapphire), glass, quartz, etc., so that the light can be emitted toward the substrate 121 after the semiconductor die 1 is bonded to the carrier 2.

The semiconductor stack 122 includes a first semiconductor layer 122a, a second semiconductor layer 122b, and an active layer 122c formed between the first semiconductor layer 122a and the second semiconductor layer 122b, the active layer 122c, and the first semiconductor layer 122a are sequentially disposed on the substrate 121, and the light-emitting stack 122 can be grown on the substrate 121 by direct epitaxy; or the light-emitting stack 122 is epitaxially grown on a growth substrate, and then the light-emitting stack 122 is bonded to the substrate 121 by a substrate transfer technique and the growth substrate is removed; alternatively, in another embodiment, the stacked structure 11 may not include any substrate structure, and the light-emitting stack 122 is directly epitaxially grown on a growth substrate, and then the growth substrate is removed, so that the stacked structure 11 does not have any substrate, thereby reducing the thickness of the semiconductor die 1 to meet the requirement of thinning applications, such as a backlight source applied to a mobile device. The light emitting layer 122 may be epitaxially deposited on the substrate 121 or the growth substrate by Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), or the like, the first semiconductor layer 122a and the second semiconductor layer 122b have a first conductivity type and a second conductivity type, respectively, and the active layer 122c may include a single heterostructure (single heterostructure), a double heterostructure (double heterostructure), or a multiple quantum well (multiple quantum well) for emitting light when driven. The first bonding pad 112 and the second bonding pad 113 are respectively disposed on the first semiconductor layer 122a and the second semiconductor layer 122b, and the transparent substrate refers to a material of the substrate 121 having a band gap larger than that of the active layer 122c so as to have a high transmittance for light generated by the active layer 122 c. When the light emitting stack 122 is bonded to the substrate 121 by the substrate transfer technique, a transparent adhesive layer (not shown) may be disposed between the substrate 121 and the semiconductor stack 122, and the adhesive layer may be an organic polymer material or an inorganic material, such as an oxide, a nitride, or a fluoride.

Referring to fig. 13, the stacked structure 11 further includes a reflective layer 15 disposed on the first semiconductor layer 122a and an insulating layer 16 disposed on the reflective layer 15. The semiconductor die 1 further has a first channel 13 and a second channel 14, wherein the first channel 13 is formed by removing a portion of the insulating layer 16 to expose the reflective layer 15 during the manufacturing process; the second channel 14 is formed by removing a portion of the active layer 122c, the first semiconductor layer 122a, the reflective layer 15 and the insulating layer 16 to expose the second semiconductor layer 122b in the manufacturing process. The first electrode pad 112 is electrically connected to the first semiconductor layer 122a through the first via 13, the second electrode pad 113 is electrically connected to the second semiconductor layer 122b through the second via 14, an opening area of the insulating layer 16 in the first via 13 is smaller than an area of the first bonding pad 112, and an opening area of the insulating layer 16 in the second via 14 is smaller than an area of the second bonding pad 113. In detail, the first bonding pad 112 and the second bonding pad 113 are electrically connected to the semiconductor stack 122 through the first via 13 and the second via 14, respectively, and the areas of the first via 13 and the second via 14 contacting the semiconductor stack 122 through the opening of the insulating layer 16 are smaller than the areas of the first bonding pad 112 and the second bonding pad 113, respectively, the first bonding pad 112 and the second bonding pad 113 can enable the semiconductor die 1 to introduce current through the first bonding pad 112 and the second bonding pad 113 with larger areas, and thus increase the heat dissipation capability of the semiconductor die 1. The reflective layer 16 is used to reflect the light emitted from the active layer 122c toward the first semiconductor layer 122a toward the substrate 121, thereby increasing the light extraction efficiency of the semiconductor die 1. The structure of the semiconductor die 1 is only one possible embodiment, but is not intended to limit the structural aspect of the semiconductor die 1, and the semiconductor die 1 with the shortest distance between the first bonding pad 112 and the second bonding pad 113 of the semiconductor die 1 smaller than 150 μm can be accommodated in the scope of the present embodiment.

Referring to fig. 14, which is a cross-sectional view of a semiconductor die 1 'according to another embodiment of the present invention, the semiconductor die 1' is a packaged die formed by chip-scale-package (CSP) technology. The semiconductor die 1' includes the semiconductor die 1 shown in fig. 13, which has the first bonding pad 112 and the second bonding pad 113 disposed on the surface 111, the first bonding pad 112 has a first metal extension 112E, the first metal extension 112E has a first end 112T facing the second bonding pad 113, the second bonding pad 113 has a second metal extension 113E, the second metal extension 113E has a second end 113T facing the first bonding pad 112, and the first end 112T of the first bonding pad 112 and the second end 113T of the second bonding pad 113 have a shortest distance d smaller than 150 μm. The semiconductor die 1 'further includes a package body 19 for encapsulating the semiconductor die 1, wherein the first metal extension portion 112E and the second metal extension portion 113E protrude out of the surface of the semiconductor die 1 and extend onto the package body 19, and a main light emitting surface 116' is formed on the surface 111 of the semiconductor die 1. Optionally, the package 19 may include a wavelength converter 191, and the wavelength converter 191 is capable of being excited by the light emitted from the semiconductor die 1 and converting the light emitted from the semiconductor die 1 into light with a different wavelength. The package 19 includes Epoxy (Epoxy), Silicone (Silicone), Polyimide (PI), benzocyclobutene (BCB), Perfluorocyclobutane (PFCB), Su8, Acrylic (Acrylic Resin), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), Polycarbonate (PC), or Polyetherimide (Polyetherimide); wavelength conversionThe body 191 includes one or more kinds of inorganic phosphors (phosphors), organic fluorescent pigments (organic fluorescent pigments), semiconductor materials (semiconductors), or a combination thereof. The inorganic phosphor materials include, but are not limited to, yellow-green phosphor and red phosphor. The yellow-green phosphor is composed of, for example, aluminum oxide (YAG or TAG), silicate, vanadate, alkaline earth metal selenide, or metal nitride. The red phosphor is, for example, a fluoride (K)₂TiF₆:Mn⁴⁺、K₂SiF₆:Mn⁴⁺) Silicates, vanadates, alkaline earth metal sulfides, metal oxynitrides, or mixtures of the tungsten molybdate family. The semiconductor material comprises a nano-sized crystalline (nano-crystalline) semiconductor material, such as a quantum-dot (quantum-dot) light emitting material. The quantum dot light emitting material may be selected from the group consisting of zinc sulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), zinc oxide (ZnO), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), gallium nitride (GaN), gallium phosphide (GaP), gallium selenide (GaSe), gallium antimonide (GaSb), gallium arsenide (GaAs), aluminum nitride (AlN), aluminum phosphide (AlP), aluminum arsenide (AlAs), indium phosphide (InP), indium arsenide (InAs), tellurium (Te), lead sulfide (PbS), indium antimonide (InSb), lead telluride (PbTe), lead selenide (PbSe), antimony telluride (SbTe), zinc selenide sulfide (ZnCdSeS), copper cadmium sulfide (CuInS), cesium lead chloride (PbCl)₃) Cesium lead bromide (CsPbBr)₃) And cesium lead iodide (CsPbI)₃) The group consisting of. The semiconductor die 1 ' of the present embodiment may include a reflective layer 15 on the surface 111, the first bonding pads 112 and the second bonding pads 113 as the semiconductor die 1 of the first embodiment, the first metal extension portions 112E are connected to the first bonding pads 112 through an opening of the reflective layer 15, and the second metal extension portions 113E are connected to the second bonding pads 113a through another opening of the reflective layer 15, but the reflective layer 15 of the present embodiment is an insulating material to transmit light of the semiconductor die 1 ' toward the surface 111 through the reflective layer 15 and emit the light toward the package 19 of the main light emitting surface 116 '.

The boundary of the current-conducting region 31 in the above embodiments is a continuous outer boundary formed by the continuous joining of the outer conductive materials C1, C2, and C3 in the current-conducting region 31, for example, as shown by the black bold line in fig. 2; the boundary of the current isolation region 32 in the above embodiments is the outer boundary formed by the non-conductive material on the outer side of the current isolation region 32, as described herein. The above-mentioned embodiments use descriptive technical content and inventive features to enable those skilled in the art to understand the content of the present invention and implement the same, which are not intended to limit the scope of the present invention. That is, any obvious modifications or alterations of the present invention can be made without departing from the spirit and scope of the present invention. For example, the electrical connection is not limited to a series connection. It should be understood that the above-described embodiments of the present invention may be combined with or substituted for one another as appropriate, and are not intended to be limited to the particular embodiments shown.

It is to be understood that various modifications and alterations may be made by those skilled in the art without departing from the spirit and scope of the invention. It is intended that all such modifications and variations of the present invention be included within the scope of the present invention and protected by the following claims.

Claims

1. A semiconductor device, comprising:

a semiconductor die comprising a stacked structure, a first bonding pad and a second bonding pad disposed on a surface of the stacked structure, wherein the first bonding pad has a top surface away from the stacked structure, and a shortest distance between the first bonding pad and the second bonding pad is less than 150 μm;

a carrier plate having a surface;

the third bonding pad and the fourth bonding pad are arranged on the surface of the carrier plate; and

a conductive bonding layer comprising:

a first conductive portion disposed between the first bonding pad and the third bonding pad and comprising a first conductive material having a first shape with a width;

a second conductive portion disposed between the second bonding pad and the fourth bonding pad and including the first conductive material; and

a current blocking region covering the first conductive portion in a cross-sectional view and comprising a first conductive material having a second shape having a particle diameter smaller than the width,

wherein the first shape has a height larger than the particle diameter, and the first conductive portion completely covers the top surface when viewed in a cross-sectional view,

the conductive bonding layer comprises a non-conductive material, and the first conductive material has better surface wetting property than the non-conductive material and the first bonding pad, the second bonding pad, the third bonding pad and the fourth bonding pad.

2. The semiconductor device of claim 1, wherein a thickness of the first conductive portion is less than 40 μm.

3. The semiconductor device of claim 1, wherein the distance between the surface of the stacked structure and the surface of the carrier is less than 60 μm.

4. The semiconductor device according to claim 1, wherein the stacked structure comprises a semiconductor stack, and contact areas of the first conductive portion and the second conductive portion with the semiconductor stack are smaller than areas of the third bonding pad and the fourth bonding pad, respectively.

5. The semiconductor device of claim 1, wherein a content of the first conductive material of the current exclusion zone is less than a content of the first conductive material of the first conductive portion.

6. The semiconductor device according to claim 5, wherein a content of the first conductive material in the first conductive portion is 8% to 75%.

7. The semiconductor device of claim 5, wherein the first conductive material content in the current exclusion zone is between 2% and 50%.

8. The semiconductor device of claim 1, wherein a shortest distance between the first bonding pad and the second bonding pad is 15-100 μm.

9. The semiconductor device of claim 1, wherein a shortest distance between the first and second bonding pads is greater than or equal to two times the width.