CN107204325B - Capacitor array and method of manufacture - Google Patents
Capacitor array and method of manufacture Download PDFInfo
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- CN107204325B CN107204325B CN201710378230.5A CN201710378230A CN107204325B CN 107204325 B CN107204325 B CN 107204325B CN 201710378230 A CN201710378230 A CN 201710378230A CN 107204325 B CN107204325 B CN 107204325B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
Abstract
The embodiment of the invention provides a capacitor array and a manufacturing method thereof. The capacitor array includes: the first group of capacitors comprises a first capacitor and a second capacitor, the second group of capacitors comprises a third capacitor and a fourth capacitor, the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are all capacitors with mirror symmetry plane polar plates and comprise an upper polar plate and a lower polar plate, the same-layer plane polar plates of the first capacitor and the second capacitor are distributed in a mirror symmetry mode by taking a first symmetry axis as an axis, the same-layer plane polar plates of the third capacitor and the fourth capacitor are distributed in a mirror symmetry mode by taking a second symmetry axis as an axis, and a preset angle is formed between the first symmetry axis and the second symmetry axis. The signals coupled from one set of capacitors to the other set of capacitors are of substantially equal magnitude and form a common mode signal that can be filtered by the differential signal detection port, thereby improving the interference problem between the different capacitive channels.
Description
Technical Field
The invention relates to the field of electric elements, in particular to a capacitor array and a manufacturing method thereof.
Background
The use of capacitors to transfer signals between chips or modules having high voltage differentials has wide application in communication modules and data buses. With the increase of system integration, discrete capacitive devices are gradually replaced by integrated capacitors on a chip.
The integrated capacitor adopts a planar structure and comprises an upper planar metal polar plate and a lower planar metal polar plate, and high-voltage isolation and electric field coupling between the capacitive polar plates are realized through a dielectric layer between the polar plates. As the system volume is reduced and the pulse width of the transmission signal is reduced, the electrode plate area of the integrated capacitor is correspondingly reduced, and the distance between adjacent capacitors is also continuously reduced. This results in an enhanced coupling between plates of different capacitances, which can lead to stronger interference signals between capacitances belonging to different signal paths.
Although the conventional differential signal detection method can effectively filter common-mode interference signals, the conventional differential signal detection method cannot eliminate non-common-mode interference signals generated by inter-channel coupling in an integrated capacitor, and particularly when the capacitor is used for bidirectional signal transmission, the inter-channel coupling condition is more complex and remarkable. Therefore, how to solve the interference problem of different capacitance channels in the capacitance integration technology is a problem in the art.
Disclosure of Invention
In view of the above, the present invention provides a capacitor array and a manufacturing method thereof to improve the interference problem of different capacitance channels in the existing capacitance integration technology.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the capacitor array comprises a first group of capacitors and a second group of capacitors, wherein the first group of capacitors comprises a first capacitor and a second capacitor, the second group of capacitors comprises a third capacitor and a fourth capacitor, the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are all capacitors with mirror symmetry plane polar plates, the upper polar plate and the lower polar plate are contained, the same-layer polar plates of the first capacitor and the second capacitor are distributed in mirror symmetry by taking a first symmetry axis as an axis, the same-layer polar plates of the third capacitor and the fourth capacitor are distributed in mirror symmetry by taking a second symmetry axis as an axis, and a preset angle is formed between the first symmetry axis and the second symmetry axis.
A method of manufacturing a capacitor array for manufacturing the capacitor array described above, the method comprising: depositing a first dielectric layer on a substrate; forming a first polar plate of the capacitor on the first dielectric layer by using a metal material; forming a second dielectric layer on the surface of the first polar plate and the surface of the first dielectric layer; forming a second polar plate of the capacitor on the second dielectric layer by using a metal material; and forming a third dielectric layer on the surface of the second polar plate and the surface of the second dielectric layer.
The capacitor array and the manufacturing method provided by the embodiment of the invention have the beneficial effects that:
the capacitor array and the manufacturing method provided by the embodiment of the invention comprise a first group of capacitors and a second group of capacitors, wherein the first group of capacitors comprise a first capacitor and a second capacitor, the second group of capacitors comprise a third capacitor and a fourth capacitor, the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are all capacitors with mirror symmetry plane polar plates and comprise upper polar plates and lower polar plates, the same-layer polar plates of the first capacitor and the second capacitor are distributed in mirror symmetry by taking a first symmetry axis as an axis, the same-layer polar plates of the third capacitor and the fourth capacitor are distributed in mirror symmetry by taking a second symmetry axis as an axis, and the first symmetry axis and the second symmetry axis have preset angles. The planar plates of the first capacitor and the second capacitor are mirror symmetry about the second symmetry axis, the planar plates of the third capacitor and the fourth capacitor are mirror symmetry about the first symmetry axis, so that the parasitic capacitance between the upper (lower) plate of the first capacitor and the upper or lower plate of the third capacitor and the upper or lower plate of the fourth capacitor is symmetrical (equal), the parasitic capacitance between the upper (lower) plate of the second capacitor and the upper or lower plate of the third capacitor and the parasitic capacitance between the upper (lower) plate of the third capacitor and the upper or lower plate of the first capacitor and the upper or lower plate of the second capacitor is symmetrical (equal), and the parasitic capacitance between the upper (lower) plate of the fourth capacitor and the upper or lower plate of the first capacitor and the upper or lower plate of the second capacitor is symmetrical (equal). The signals of one set of capacitors coupled to the other set of capacitors are of substantially equal magnitude, forming a common mode signal that can be filtered by the differential signal detection ports, thereby improving the interference problem for the different capacitive channels.
Drawings
For a clearer description of embodiments of the invention or of solutions in the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
FIG. 1 is a schematic top view of a portion of a capacitor array according to a first embodiment of the present invention;
FIG. 2 is a schematic top view of a single layer plate of one embodiment of a capacitor array provided by a first embodiment of the present invention;
FIG. 3a is a schematic top view of an upper plate of a capacitor array according to a first embodiment of the present invention;
FIG. 3b is a schematic top view of a bottom plate of a capacitor array according to a first embodiment of the present invention;
FIG. 4a is a schematic diagram of a capacitor array according to a second embodiment of the present invention;
FIG. 4b is a schematic top view of the upper plate of the capacitor array shown in FIG. 4 a;
FIG. 4c is a schematic top view of the lower plate of the capacitor array shown in FIG. 4 a;
FIG. 5 is a schematic step diagram of a method of fabricating a capacitor array according to an embodiment of the present invention;
fig. 6 is a flow chart of a method for fabricating a capacitor array according to an embodiment of the present invention.
Icon: a 10-capacitor array; 110-a first set of capacitors; 111-a first capacitor; 112-a second capacitor; 120-a second set of capacitors; 121-a third capacitor; 122-fourth capacitor; 130-a first symmetry axis; 140-a second symmetry axis; 150-conductor structure; 161-first trace; 162-second trace; 163-third trace; 164-fourth wiring; 171-first pads; 172-second pads; 173-third pads; 174-fourth pads; 180-parasitic capacitance; 191-upper layer polar plate; 192-lower plate; 193-sub-plates; 201-a first opening; 202-a second opening; 210-substrate; 220-a first dielectric layer; 230-a first plate; 240-a second dielectric layer; 250-a second polar plate; 260-third dielectric layer.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The following detailed description of the embodiments of the invention, provided in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
Referring to fig. 1 for details, fig. 1 is a schematic top view of a capacitor array 10 according to a first embodiment of the present invention. The capacitor array 10 includes a first set of capacitors 110 and a second set of capacitors 120. Wherein the first set of capacitors 110 comprises a first capacitor 111 and a second capacitor 112, and the second set of capacitors 120 comprises a third capacitor 121 and a fourth capacitor 122.
The capacitors each include an upper plate 191 and a lower plate 192. The lower plate 192 of the capacitor is formed by the same process step and is located substantially in a single plane; the upper plate 191 of the capacitor is also formed by the same process step and is also located substantially in a single plane; the upper plate 191 and the lower plate 192 of the capacitor are planar plates. The positions and shapes of the upper and lower electrode plates of the capacitor correspond to each other in the vertical direction, and therefore, the upper electrode plate and the lower electrode plate of the capacitor overlap each other in a plan view, and the plan view shown in fig. 1 represents a plan view of both the upper electrode plate 191 and the lower electrode plate 192.
Mirror symmetry in the present invention means that the pattern is folded along an axis of symmetry, the parts on either side of the axis of symmetry being able to coincide with each other. Mirror symmetry of a three-dimensional structure such as a planar plate in the present invention refers to mirror symmetry of a top view pattern of the three-dimensional structure.
The first capacitor 111 is a capacitor with mirror symmetry plane plates, and the top view patterns of the upper and lower plane plates of the first capacitor 111 are mirror symmetry patterns. Similarly, the second capacitor 112 is a capacitor having mirror symmetry planar plates, and the top view patterns of the upper and lower planar plates of the second capacitor 112 are mirror symmetry patterns. The top views of the same-layer electrode plates of the first capacitor 111 and the second capacitor 112 are distributed in a mirror symmetry manner by taking the first symmetry axis 130 as an axis.
The third capacitor 121 is a capacitor with mirror symmetry plane plates, and the top view patterns of the upper and lower plane plates of the third capacitor 121 are mirror symmetry patterns. Similarly, the fourth capacitor 122 is a capacitor having a mirror-symmetrical planar plate, and the top view patterns of the upper and lower planar plates of the fourth capacitor 122 are mirror-symmetrical patterns. The shape of the plate of the third capacitor 121 may be different from the plate shape of the first capacitor 111 or the plate shape of the second capacitor 112. The same-layer plate top view patterns of the third capacitor 121 and the fourth capacitor 122 are distributed in mirror symmetry with the second symmetry axis 140 as an axis.
The first capacitor 111 and the second capacitor 112 may each be a capacitor having a mirror plane plate about the second symmetry axis 140, and the third capacitor 121 and the fourth capacitor 122 may each be a capacitor having a mirror plane plate about the first symmetry axis 130. Mathematically, it can be demonstrated that when the planar plates of the first capacitor 111 and the second capacitor 112 are themselves mirror symmetric about the second symmetry axis 140, mirror symmetry is provided between the planar plates of the same layer of the first capacitor 111 and the second capacitor 112 about the first symmetry axis 130; and the plane plates of the third capacitor 121 and the fourth capacitor 122 are mirror symmetric about the first symmetry axis 130, the same plane plates of the third capacitor 121 and the fourth capacitor 122 are mirror symmetric about the second symmetry axis 140, and the capacitor array has the best symmetry and the technical effect when the preset included angle between the first symmetry axis 130 and the second symmetry axis 140 is 90 °.
The first symmetry axis 130 and the second symmetry axis 140 have a predetermined angle therebetween, and in particular, the predetermined angle between the first symmetry axis 130 and the second symmetry axis 140 may be 80 ° to 100 °, and preferably, the predetermined angle between the first symmetry axis 130 and the second symmetry axis 140 may be 90 °.
In a specific implementation manner of the capacitor array 10 according to the first embodiment of the present invention, the capacitor array further includes a conductor structure 150, where the conductor structure 150 may be disposed at edge positions of plates of the first capacitor 111, the second capacitor 112, the third capacitor 121, and the fourth capacitor 122, respectively, as shown in fig. 2 for details. The shape of the conductor structures 150 at the edge positions of the upper and lower electrode plates of the same capacitor can be independently set, that is, the shape is determined according to the specific application requirements of the upper and lower electrode plates, so that the edge conductor structures belonging to the upper and lower electrode plates can have the same or different shapes.
The area of the conductor structure 150 disposed at the edge of the plate of the first capacitor 111 is smaller than the area of the plate of the first capacitor 111, and preferably, the area of the conductor structure 150 disposed at the edge of the plate of the first capacitor 111 is smaller than or equal to 50% of the area of the plate of the first capacitor 111.
The area of the conductor structure 150 disposed at the edge of the plate of the second capacitor 112 is smaller than the area of the plate of the second capacitor 112, and preferably, the area of the conductor structure 150 disposed at the edge of the plate of the second capacitor 112 is smaller than or equal to 50% of the area of the plate of the second capacitor 112.
The area of the conductor structure 150 disposed at the edge of the plate of the third capacitor 121 is smaller than the area of the plate of the third capacitor 121; preferably, the area of the conductor structure 150 disposed at the edge of the plate of the third capacitor 121 is less than or equal to 50% of the area of the plate of the third capacitor 121.
The area of the conductor structure 150 disposed at the edge of the plate of the fourth capacitor 122 is smaller than the area of the plate of the fourth capacitor 122. Preferably, the area of the conductor structure 150 disposed at the edge of the plate of the fourth capacitor 122 is less than or equal to 50% of the area of the plate of the fourth capacitor 122.
The conductor structures 150 disposed at the edge positions of the capacitors may have a structure that does not have the symmetry described above or a mirror-symmetrical structure that has another symmetry axis as an axis with respect to the plates of the capacitors, for example, referring to fig. 2, the top view pattern formed by the first capacitor 111 and the conductor structures 150 at the edge of the plates of the first capacitor 111 and the top view pattern formed by the second capacitor 112 and the conductor structures 150 at the edge of the second capacitor 112 do not have the mirror symmetry. The shape of the conductor structures 150 at the edge positions of the upper and lower electrode plates of the same capacitor can be independently set, that is, the shape of the conductor structures can be determined according to the specific application requirements of the upper and lower electrode plates, so that the edge conductor structures belonging to the upper and lower electrode plates can have the same or different shapes, and only one electrode plate and the top view pattern of the conductor at the edge position thereof are shown in fig. 2.
The capacitor array 10 provided in the first embodiment of the present invention further includes a first wire 161, a second wire 162, a third wire 163, a fourth wire 164, a first pad 171, a second pad 172, a third pad 173, and a fourth pad 174.
Referring to fig. 3a for details, in the upper plate 191 of the entire capacitor array 10 shown in the first embodiment, the first pad 171, the second pad 172, the third pad 173, and the fourth pad 174 are disposed at the upper portion as shown in fig. 3 a.
The first capacitor 111 and the second capacitor 112 are distributed left and right, the third capacitor 121 and the fourth capacitor 122 are distributed up and down, and the shapes of the third capacitor 121 and the fourth capacitor 122 are respectively in a compact layout with the shapes of the first capacitor 111 and the second capacitor 112. The first capacitor 111 is connected to the first pad 171 through the first wire 161, the second capacitor 112 is connected to the second pad 172 through the second wire 162, the third capacitor 121 is connected to the third pad 173 through the third wire 163, and the fourth capacitor 122 is connected to the fourth pad 174 through the fourth wire 164.
Referring to fig. 3b in detail, in the lower plate 192 of the entire capacitor array 10 shown in the first embodiment, the first pad 171, the second pad 172, the third pad 173, and the fourth pad 174 are disposed at the lower portion as shown in fig. 3 b.
The first capacitor 111 and the second capacitor 112 are distributed in the left-right direction, the third capacitor 121 and the fourth capacitor 122 are distributed in the up-down direction, and the positions of the first capacitor 111 to the fourth capacitor 122 in the lower plate 192 correspond to the positions in the upper plate 191. The first capacitor 111 is connected to the first pad 171 through the first wire 161, the second capacitor 112 is connected to the second pad 172 through the second wire 162, the third capacitor 121 is connected to the third pad 173 through the third wire 163, and the fourth capacitor 122 is connected to the fourth pad 174 through the fourth wire 164. Therefore, in the upper plate 191 and the lower plate 192 of the capacitor array 10 shown in the first embodiment, the positions of the upper plate 191 and the lower plate 192 of the first to fourth capacitors 111 to 122 are correspondingly the same, except for the positions of the first pad 171, the second pad 172, the third pad 173, the fourth pad 174, and the first wire 161, the second wire 162, the third wire 163, and the fourth wire 164 respectively connected thereto.
And, the sum of the areas of the first wire 161 and the first pad 171 may be smaller than the area of the plate of the first capacitor 111, the sum of the areas of the second wire 162 and the second pad 172 may be smaller than the area of the plate of the second capacitor 112, the sum of the areas of the third wire 163 and the third pad 173 may be smaller than the area of the plate of the third capacitor 121, and the sum of the areas of the fourth wire 164 and the fourth pad 174 may be smaller than the area of the plate of the fourth capacitor 122.
Referring to fig. 4a for details, fig. 4a is a schematic structural diagram of a capacitor array 10 according to a second embodiment of the present invention. The plates of the first capacitor 111, the second capacitor 112, the third capacitor 121, and the fourth capacitor 122 each comprise at least one sub-plate 193. The sub-polar plates can shorten the wiring distance between the polar plates and the bonding pads, and reduce parasitic parameters.
The first capacitor 111 may comprise two sub-plates, see in particular fig. 4a, 4b and 4c. The two sub-plates may in particular be connected by a conductor structure 150. In the upper plate 191 of the capacitor array 10 shown in the second embodiment, the first pad 171, the second pad 172, the third pad 173, and the fourth pad 174 are located on the right side as viewed in fig. 4a and 4 b. In the lower plate 192 of the capacitor array 10 shown in the second embodiment, the first pad 171, the second pad 172, the third pad 173 and the fourth pad 174 are located on the left side as viewed in fig. 4a and 4c.
In the upper plate 191, referring to fig. 4b, the first capacitor 111 is connected to the first pad 171 through the first trace 161 by the conductor structure 150 connecting the two sub-plates. The two sub-plates of the second capacitor 112 may be connected to the second pad 172 through respective second wires 162, the third capacitor 121 may be connected to the third pad 173 through the third wire 163, and the fourth capacitor 122 may be connected to the fourth pad 174 through the fourth wire 164.
In the lower plate 192, referring to fig. 4c, two sub-plates 193 of the first capacitor 111 may be connected to the first pad 171 through respective first traces 161, and the second capacitor 112 may be connected to the second pad 172 through the first trace 161 through the conductor structure 150 connecting the two sub-plates. The third capacitor 121 is connected to the third pad 173 through the third trace 163, and the fourth capacitor 122 is connected to the fourth pad 174 through the fourth trace 164.
Similarly, the third capacitor and the fourth capacitor may also include sub-plates, which are not described herein.
The working principle of the capacitor array 10 provided by the embodiment of the invention is as follows:
the first set of capacitors 110 and the second set of capacitors 120 are used to transmit two different differential signals, respectively, and the second capacitor 112 is described as an example:
referring to fig. 1, since the planar plate of the second capacitor 112 has a mirror-symmetrical top view pattern, and in the first embodiment shown in fig. 1, the planar plate top view pattern of the second capacitor 112 is specifically a mirror-symmetrical pattern about the second symmetry axis 140. Thus, the second capacitor 112 is in operation a symmetrical potential body, i.e. the electric field lines and the potential distribution emitted by the second capacitor 112 are also mirror symmetrical with respect to a plane perpendicular to the plane of the planar plates and passing through the second symmetry axis 140, without being disturbed by the application of external forces. The electric fields, which are mirror symmetric about a plane perpendicular to the plane of the planar plate and passing through the second symmetry axis 140, are coupled to a third capacitor 121 and a fourth capacitor 122, respectively, which are mirror symmetric about a plane perpendicular to the plane of the planar plate and passing through the second symmetry axis 140. Thus, the resulting interference signal is also symmetrical.
Referring specifically to fig. 1, a plurality of parasitic capacitances 180 are distributed between the second capacitor 112 and the third capacitor 121, such as four parasitic capacitances 180 on the upper side shown in fig. 1; a plurality of parasitic capacitances 180 are also distributed between the second capacitor 112 and the fourth capacitor 122, such as the lower four parasitic capacitances 180 shown in fig. 1.
Since the parasitic capacitance 180 distributed between the second capacitor 112 and the third capacitor 121 and the parasitic capacitance 180 distributed between the second capacitor 112 and the fourth capacitor 122 are symmetrical, the signal size of the second capacitor 112 coupled to the third capacitor 121 and the signal size of the second capacitor 112 coupled to the fourth capacitor 122 are completely equal, constituting a common mode signal. The common mode signal is filtered by the differential signal detection port, and an error signal is not generated on the signal channel corresponding to the second capacitor 112, and an error signal is not generated on the signal channels corresponding to the third capacitor 121 and the fourth capacitor 122.
Similarly, the first capacitor 111, the third capacitor 121 and the fourth capacitor 122 may be verified one by one, the interference signals generated by the first capacitor set 110 in the second capacitor set 120 are common-mode signals with equal magnitudes and identical directions, the interference signals generated by the second capacitor set 120 in the first capacitor set 110 are common-mode signals with equal magnitudes and identical directions, and the common-mode signals may be filtered by the differential signal detection port.
The angle between the first symmetry axis 130 and the second symmetry axis 140 is 90 degrees, which is a better form of eliminating interference signals, and since the plates of the capacitors need to be connected to other components and circuits through traces and pads, the first group of capacitors 110 and the second group of capacitors 120 do not necessarily have strict symmetry, and the areas (e.g., conductor structures 150, traces, and pads) that do not have strict symmetry are smaller than the areas of the plate symmetry.
Therefore, the included angle between the first symmetry axis 130 and the second symmetry axis 140 may be a range, for example, between 80 degrees and 100 degrees, or the area of the conductor structure 150 without symmetry is less than or equal to half the area of the polar plate with symmetry, and the interference signal generated by the conductor structure 150 without symmetry is relatively small, so that the capacitor array 10 without strict symmetry can still significantly reduce the intensity of the interference signal.
Referring to fig. 6 for details, fig. 6 shows a process of manufacturing the capacitor array 10, specifically comprising the steps of:
in step S110, a first dielectric layer 220 is deposited on a substrate 210.
The substrate 210 may be a PCB board, a silicon wafer, glass or an organic substrate, as shown in fig. 5 (a). A first dielectric layer 220 is deposited over the substrate 210. Materials commonly used for the first dielectric layer 220 include silicon oxide, silicon nitride, aluminum oxide, polymers (e.g., polyimide, benzocyclobutene, etc.), as shown in fig. 5 (b). This step may be omitted if the substrate is an insulator.
In step S120, a first plate 230 of a capacitor is formed on the first dielectric layer 220 using a metal material.
The first plate 230 may be the lower plate 192 described above, i.e., the first plate 230 may be formed on the surface of the first dielectric layer 220 using a metal material (e.g., copper or aluminum) in the shape shown in fig. 3b or 4c, as shown in fig. 5 (c).
In step S130, a second dielectric layer 240 is formed on the surface of the first electrode plate 230 and the surface of the first dielectric layer 220.
Referring to fig. 5 (d), the surface of the first electrode plate 230 and the first dielectric layer 220 is covered with the second dielectric layer 240, and the lower electrode plate 192 needs to be led out, so that the first opening 201 may be left at the upper left side of fig. 5 (d). If a thicker second dielectric layer 240 is desired, it may be formed by multiple depositions.
In step S140, a second plate 250 of the capacitor is formed on the second dielectric layer 240 using a metal material.
The second electrode 250 is the upper electrode 191, and may be formed on the surface of the second dielectric layer 240 by using a metal material according to the shape of fig. 3a or fig. 4b, see fig. 5 (e).
In step S150, a third dielectric layer 260 is formed on the surface of the second electrode plate 250 and the surface of the second dielectric layer 240.
The second electrode 250 and the surface of the second dielectric layer 240 are covered with the second electrode 250, and the second electrode 250 may be provided with a second opening 202 for leading out the upper electrode 191, see fig. 5 (f).
The capacitor array 10 and the manufacturing method provided by the embodiment of the invention include a first group of capacitors 110 and a second group of capacitors 120, wherein the first group of capacitors 110 includes a first capacitor 111 and a second capacitor 112, the second group of capacitors 120 includes a third capacitor 121 and a fourth capacitor 122, the first capacitor 111, the second capacitor 112, the third capacitor 121 and the fourth capacitor 122 are all mirror symmetrical capacitors, plane polar plate top views of the first capacitor 111 and the second capacitor 112 are distributed in mirror symmetry with the first symmetry axis 130 as an axis, plane polar plate top views of the third capacitor 121 and the fourth capacitor 122 are distributed in mirror symmetry with the second symmetry axis 140 as an axis, and the first symmetry axis 130 and the second symmetry axis 140 have a preset angle. Since the first capacitor 111, the second capacitor 112, the third capacitor 121 and the fourth capacitor 122 are all mirror symmetrical, and the first capacitor 111 and the second capacitor 112 are distributed in mirror symmetry, and the third capacitor 121 and the fourth capacitor 122 are distributed in mirror symmetry, the parasitic capacitance 180 between the first capacitor 111 and the third capacitor 121, the fourth capacitor 122 is symmetrical, and the parasitic capacitance 180 between the second capacitor 112 and the third capacitor 121, the fourth capacitor 122 is symmetrical. Similarly, the third capacitor 121 and the fourth capacitor 122 are symmetrical with respect to the parasitic capacitance 180 of the first group capacitor 110. The signals of one set of capacitors coupled to the other set of capacitors are of substantially equal magnitude, forming a common mode signal that can be filtered by the differential signal detection ports, thereby improving the interference problem for the different capacitive channels.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention are clearly and completely described above in conjunction with the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Accordingly, the above detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are directions or positional relationships based on those shown in the drawings, or are directions or positional relationships conventionally put in use of the inventive product, are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element to be referred to must have a specific direction, be constructed and operated in a specific direction, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Claims (8)
1. A capacitor array, the capacitor array comprising: a first set of capacitors and a second set of capacitors, the first set of capacitors comprising a first capacitor and a second capacitor, the second set of capacitors comprising a third capacitor and a fourth capacitor,
the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are all capacitors with mirror symmetry plane polar plates and comprise an upper polar plate and a lower polar plate,
the same-layer planar polar plates of the first capacitor and the second capacitor are distributed in mirror symmetry by taking a first symmetry axis as an axis, the same-layer planar polar plates of the third capacitor and the fourth capacitor are distributed in mirror symmetry by taking a second symmetry axis as an axis, and a preset angle is formed between the first symmetry axis and the second symmetry axis;
wherein the mirror symmetry means that the image is folded along a symmetry axis, and parts at two sides of the symmetry axis can be mutually overlapped; the angle range of the preset angle between the first symmetry axis and the second symmetry axis is [80 degrees, 90 degrees) ], namely U (90 degrees, 100 degrees ].
2. The capacitor array of claim 1, wherein:
the polar plates of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor all comprise at least one sub-polar plate.
3. The capacitor array of claim 2, wherein: also included is a conductor structure that is configured to be electrically isolated from the conductor structure,
the pole plates of the first capacitor and the pole plates of the second capacitor comprise a plurality of sub-pole plates, the sub-pole plates of the first capacitor are connected through the conductor structure, and the sub-pole plates of the second capacitor are connected through the conductor structure.
4. The capacitor array of claim 1, wherein: still include the conductor structure, the conductor structure set up in respectively the border position of first condenser, second condenser, third condenser, fourth condenser polar plate, the conductor structure shape of upper and lower floor's polar plate sets up independently to:
the area of the conductor structure arranged at the edge position of the polar plate of the first capacitor is smaller than that of the polar plate of the first capacitor;
the area of the conductor structure arranged at the edge position of the polar plate of the second capacitor is smaller than that of the polar plate of the second capacitor;
the area of the conductor structure arranged at the edge position of the polar plate of the third capacitor is smaller than that of the polar plate of the third capacitor;
the area of the conductor structure arranged at the edge position of the polar plate of the fourth capacitor is smaller than that of the polar plate of the fourth capacitor.
5. The capacitor array of claim 4, wherein:
the area of the conductor structure arranged at the edge position of the polar plate of the first capacitor is less than or equal to half of the area of the polar plate of the first capacitor;
the area of the conductor structure arranged at the edge position of the polar plate of the second capacitor is less than or equal to half of the area of the polar plate of the second capacitor;
the area of the conductor structure arranged at the edge position of the polar plate of the third capacitor is less than or equal to half of the area of the polar plate of the third capacitor;
the area of the conductor structure arranged at the edge position of the polar plate of the fourth capacitor is less than or equal to half of the area of the polar plate of the fourth capacitor.
6. The capacitor array of claim 1, wherein: the device also comprises a first wire, a second wire, a third wire, a fourth wire, a first bonding pad, a second bonding pad, a third bonding pad and a fourth bonding pad,
the first capacitor is connected with the first bonding pad through a first wiring;
the second capacitor is connected with the second bonding pad through a second wiring;
the third capacitor is connected with a third bonding pad through a third wiring;
the fourth capacitor is connected with the fourth bonding pad through a fourth wiring.
7. The capacitor array of claim 6, wherein:
the sum of the areas of the first wiring and the first bonding pad is smaller than the area of a polar plate of the first capacitor;
the sum of the areas of the second wiring and the second bonding pad is smaller than the area of a polar plate of the second capacitor;
the sum of the areas of the third wiring and the third bonding pad is smaller than the area of a polar plate of the third capacitor;
the sum of the areas of the fourth wiring and the fourth bonding pad is smaller than the area of the polar plate of the fourth capacitor.
8. A method of manufacturing a capacitor array according to claim 1, wherein:
depositing a first dielectric layer on a substrate;
forming a first polar plate of the capacitor on the first dielectric layer by using a metal material;
forming a second dielectric layer on the surface of the first polar plate and the surface of the first dielectric layer;
forming a second polar plate of the capacitor on the second dielectric layer by using a metal material;
and forming a third dielectric layer on the surface of the second polar plate and the surface of the second dielectric layer.
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