CN114937557A - Capacitor array module - Google Patents
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- CN114937557A CN114937557A CN202210582226.1A CN202210582226A CN114937557A CN 114937557 A CN114937557 A CN 114937557A CN 202210582226 A CN202210582226 A CN 202210582226A CN 114937557 A CN114937557 A CN 114937557A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 298
- 239000000463 material Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 7
- 229910021645 metal ion Inorganic materials 0.000 claims description 4
- 230000009977 dual effect Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 25
- 238000000034 method Methods 0.000 description 22
- 230000008569 process Effects 0.000 description 15
- 238000010586 diagram Methods 0.000 description 14
- 238000004590 computer program Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 9
- 230000006870 function Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 238000006731 degradation reaction Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 238000003491 array Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
- H01G2/02—Mountings
- H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
Abstract
The application discloses capacitor array module relates to integrated circuit technical field. The module of this application includes: a first region and a second region; the first area is used for arranging a capacitor array; the first area is positioned in the central part of the capacitor array module; the second region is located at the edge part in the capacitor array module and located around the first region.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a capacitor array module.
Background
With the gradual development of integrated circuit technology, the use of digital-to-analog converters, baseband filters, and other electronic devices in electronic equipment is also gradually increasing. In using these electronic devices, it is often necessary to use a capacitor array to participate in the switching control process of the gate circuit. Therefore, the advantages and disadvantages of the capacitor array directly affect the stability of the electronic devices, and thus the use of the whole electronic equipment.
At present, in the design process of the existing capacitor array, generally, the capacitor subarrays of each part are set according to the proportion according to different capacitance value requirements, and then the capacitor array is produced by a factory according to layout design, so that the required capacitor array is obtained. However, in practical applications, due to the process characteristics in the factory production process, there are many errors between each basic capacitor in the capacitor array, so that the obtained capacitor array has a mismatch in the ratio between the sub-arrays due to the error of each basic capacitor in the capacitor array, thereby affecting the normal operation of the function of the whole capacitor array module.
Disclosure of Invention
The embodiment of the application provides a capacitor array module, and the main purpose is to realize the problem that the function of the whole capacitor array module is influenced because of the error of the basic capacitor caused by the process production.
In order to solve the above technical problem, an embodiment of the present application provides the following technical solutions:
the application provides a capacitor array module, the module includes:
a first region and a second region;
the first area is used for arranging a capacitor array; the first area is positioned in the central part of the capacitor array module;
the second region is located at the edge part in the capacitor array module and is located at the periphery of the first region.
Optionally, the capacitor array is a differential dual-channel capacitor array;
the differential dual-channel capacitive array includes: a first capacitor array and a second capacitor array;
the first capacitor array and the second capacitor array both comprise a plurality of capacitor units, every two capacitor units in the plurality of capacitor units have equal proportional capacitance values, and the arrangement modes of the plurality of capacitor units are the same in a mirror image mode.
Optionally, the first capacitor array includes: the first capacitor unit, the second capacitor unit, the third capacitor unit, the fourth capacitor unit and the fifth capacitor unit;
the capacitance values of the first capacitance unit, the second capacitance unit, the third capacitance unit, the fourth capacitance unit and the fifth capacitance unit are sequentially multiplied.
Optionally, each capacitor unit in the first capacitor array is formed by a capacitor module;
wherein the first capacitance unit comprises a capacitance module;
the second capacitor unit comprises two capacitor modules which are arranged in a row;
the third capacitor unit comprises four capacitor modules which are arranged in a row;
the fourth capacitor unit comprises eight capacitor modules which are arranged in a row;
the fifth capacitor unit comprises sixteen capacitor modules, the sixteen capacitor modules are arranged in two rows, and each row is provided with eight capacitor modules.
Optionally, the first capacitor unit, the second capacitor unit, and the third capacitor unit are disposed in a first row of the first capacitor array;
the fourth capacitor unit is arranged on a second row of the first capacitor array;
the fifth capacitor unit is arranged in a third row of the second capacitor array;
wherein the first row, the second row and the third row are arranged in sequence from the center to the edge of the capacitor array module.
Optionally, the second capacitor unit is disposed between the first capacitor unit and the third capacitor unit.
Optionally, the first capacitor array further includes: a sixth capacitance unit;
wherein the sixth capacitance unit comprises eight capacitance modules; the eight capacitor modules are arranged in a row; the sixth capacitor unit is arranged on the outer side of the fifth capacitor unit, and the outer side is one side close to the edge of the capacitor array module relative to the fifth capacitor unit.
Optionally, the capacitor module is square in a top view.
Optionally, the capacitor array module is disposed on the N-well material;
the second area is provided with a plurality of dummy capacitors, the dummy capacitors are distributed according to the same interval to surround the first area, the connection ends of the dummy capacitors are connected to the N-well substrate protection ring, and the N-well substrate protection ring is used for connecting a high level.
Optionally, the capacitor module is provided with a metal connection end formed based on metal ion superposition; the metal connecting end is provided with a through hole.
By means of the technical scheme, the technical scheme provided by the application at least has the following advantages:
the application provides a capacitor array module, which comprises a first area and a second area; the first area is used for arranging a capacitor array; the first area is positioned in the central part of the capacitor array module; the second region is located at the edge part in the capacitor array module and is located at the periphery of the first region. In this application, because present capacitor array production technology tends towards the marginal portion more during production, the degradation degree of the basic electric capacity of its production is higher, consequently, the capacitor array module of this application, through set up capacitor array in the first region of central part, rather than around the second region setting, this degree that just can be influenced by the production technology in the follow-up production process reduces, thereby avoid peripheral part to lay the degradation of basic electric capacity when arranging capacitor array and lead to the problem of mismatch between the appearance value proportion of capacitor array, thereby avoided the problem that the normal function of the capacitor array module that leads to producing because of design defect receives the influence, the accuracy nature of capacitor array module has been improved.
The foregoing description is only an overview of the technical solutions of the present application, and the present application can be implemented according to the content of the description in order to make the technical means of the present application more clearly understood, and the following detailed description of the present application is given in order to make the above and other objects, features, and advantages of the present application more clearly understandable.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present application are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:
fig. 1 is a block diagram illustrating a capacitor array module according to an embodiment of the present disclosure;
fig. 2 is a block diagram illustrating another capacitor array module according to an embodiment of the present disclosure;
fig. 3 is a block diagram illustrating a capacitor array module according to an embodiment of the present disclosure;
fig. 4 is a block diagram illustrating a capacitor array module according to another embodiment of the present disclosure;
FIG. 5 is a block diagram illustrating another capacitor array module according to an embodiment of the present disclosure;
fig. 6 shows a block diagram of another capacitor array module according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which this application belongs.
The embodiment of the present application provides a capacitor array module, as shown in fig. 1, the module includes:
a first region 11 and a second region 12;
wherein the first region 11 may be used to arrange a capacitor array; the first area 11 is arranged at the central part of the capacitor array module;
the second region 12 is located at the edge portion of the capacitor array module and around the first region 11.
In practical application, a production process of a production factory for carrying out the capacitor array module based on layout design is carried out based on an etching process, namely the capacitor array module is processed on a semiconductor material, so that based on the characteristics of the processing process, the etching effect of the produced capacitor in the central part is better relative to the etching effect of the capacitor in the edge area, namely the capacitor in the edge area can cause the capacitance values of different capacitors to be possibly the same due to degradation, namely the capacitance values are deviated, and the capacitor array is characterized in that a plurality of capacitors are divided according to areas to form different capacitor sub-arrays, so that the capacitance ratio among the capacitor sub-arrays in the edge area can be influenced due to the capacitance value deviation of the basic capacitor in the area, and the accuracy of the whole capacitor array module is further influenced.
In view of this, in the embodiment, since the edge region, that is, the second region is not provided with the capacitor array, but only the middle first region is provided with the capacitor array, in the etching process of the current production process, even if the peripheral region generates a large capacitance value deviation, since the capacitor array is not provided in the partial region, the capacitor array module is not affected, and the possibility that the capacitor array in the first region where the center is located is deviated by the process characteristics is low, so that the overall accuracy of the subsequently produced capacitor array module is not affected by the production process problem, thereby improving the accuracy of the capacitor array module.
It should be noted that, in this embodiment, the ranges of the first area and the second area shown in fig. 1 are only illustrative, and the sizes of the first area and the second area in the actual application process may be set according to the actual application situation, for example, the range of the first area may be larger than the range of the second area.
In one embodiment, as shown in fig. 2, in the present embodiment, the capacitor array is specifically a differential dual-channel capacitor array;
the differential dual-channel capacitor array of the present embodiment may include: a first capacitor array 21 and a second capacitor array 22;
the first capacitor array 21 and the second capacitor array 22 are both composed of a plurality of capacitor units, wherein the capacitor units have equal proportional capacitance values; in addition, the arrangement of the plurality of capacitor units in the first capacitor array 21 and the second capacitor array 22 are the same in a mirror image manner.
Because first capacitor array 21 and second capacitor array 22 are arranged according to the mirror image mode by a plurality of electric capacity units of the equal proportion appearance value, that is to say two capacitor arrays in the first region when based on the production technology influence, the influence effect tends to the same, thereby avoided first capacitor array 21 and second capacitor array 22 to receive the problem that the influence is different and produces different appearance value deviations because of the technology leads to the two, that is to say, make two passageways have the same parameter in the difference double-channel capacitor array, the accuracy nature of capacitor array module has been improved on the whole.
In one embodiment, as shown in fig. 3, the first capacitor array 21 in the foregoing embodiments may include: a first capacitor unit 211, a second capacitor unit 212, a third capacitor unit 213, a fourth capacitor unit 214, and a fifth capacitor unit 215;
the capacitance values of the first capacitor unit 211, the second capacitor unit 212, the third capacitor unit 213, the fourth capacitor unit 214, and the fifth capacitor unit 215 are sequentially multiplied.
In this embodiment, the capacitance values of the five capacitor units included in the first capacitor array are multiplied, that is, when the first capacitor unit is 1F, the capacitance value of the second capacitor unit is 2F, the capacitance value of the third capacitor unit is 4F, the capacitance value of the fourth capacitor unit is 8F, and the capacitance value of the fifth capacitor unit is 16F.
In one embodiment, as shown in fig. 3, each capacitive unit in the first capacitive array 21 is composed of a capacitive module 2111;
the first capacitor unit 211 includes a capacitor module 2111;
the second capacitor unit 212 includes two capacitor modules 2111, and the two capacitor modules 2111 are arranged in a column;
the third capacitance unit 213 includes four capacitance modules 2111, and the four capacitance modules 2111 are arranged in a column;
the fourth capacitance unit 214 includes eight capacitance modules 2111, and the eight capacitance modules 2111 are arranged in a column;
the fifth capacitance unit 215 includes sixteen capacitance modules 2111, and the sixteen capacitance modules 2111 are arranged in two columns, where each column is provided with eight capacitance modules 2111.
In this embodiment, since the capacitor units are all formed by the capacitor modules, and the capacitor modules have the same capacitance value, it is ensured that the plurality of capacitor units can be formed by a multiple number of capacitor modules, that is, the basic capacitor in the foregoing embodiment, since the capacitor modules are generated in the same production process, it is ensured that each capacitor module has the same capacitance value, and the capacitor modules are all located in the first region where the center of the capacitor array module is located, it is ensured that the capacitance values among the capacitor modules tend to be the same, thereby ensuring that the generated capacitor units can have capacitance values of different proportions, and then forming the differential dual-channel capacitor array.
In one embodiment, as shown in fig. 3, the first capacitor unit 211, the second capacitor unit 212 and the third capacitor unit 213 are disposed in the first column of the first capacitor array 21;
the fourth capacitor unit 214 is disposed in the second row of the first capacitor array 21;
the fifth capacitor unit 215 is disposed in the third row of the second capacitor array 22;
wherein, three columns of the first column, the second column and the third column are arranged in sequence from the center to the edge of the capacitor array module.
Since in practical application, the closer the factory production process is to the center, the higher the etching precision is, that is, the better the etching effect is, in this embodiment, since the relative capacitance values of the first capacitor, the second capacitor, and the third capacitor are smaller, in the case of a process error, the most possible influence is also, for example, in the case where there is a 0.5F deviation between 100F and 10F, the influenced proportion is different, that is, the lower the capacitance value is, the more easily influenced by the production process. Therefore, in this embodiment, the capacitor unit with a smaller capacitance value is disposed at a position close to the center, and the capacitor unit with a larger capacitance value, such as the fifth capacitor unit, is disposed at a position relatively outside the fifth capacitor unit, which is beneficial to further reducing the influence of the production process on the whole capacitor array module, thereby further improving the accuracy of the capacitor array module.
In one embodiment, as shown in fig. 3, the second capacitor unit 212 is disposed between the first capacitor unit 211 and the third capacitor unit 213.
Based on the foregoing embodiments, the first capacitor unit, the second capacitor unit, and the third capacitor unit are all disposed in the first row toward the center, and due to the requirement of the wiring, in this embodiment, the first capacitor unit may be disposed at the outer side, so that the problem of wiring caused by disposing the first capacitor unit between the second capacitor unit and the third capacitor unit may be reduced, and the complexity of the wiring process is simplified.
In one embodiment, as shown in fig. 4, the first capacitor array 21 further includes: a sixth capacitance unit 216;
wherein, the sixth capacitance unit includes eight capacitance modules 2111; the eight capacitor modules 2111 are arranged in a row; the sixth capacitor unit 216 is disposed outside the fifth capacitor unit 215, which in this embodiment may be understood as a side closer to the edge of the capacitor array module than the fifth capacitor unit.
The sixth capacitor unit is a fixed capacitor unit in this embodiment, and because the capacitor unit has low requirement on the capacitance value precision of the capacitor unit, the sixth capacitor unit is arranged on the outer side of the edge closer to the capacitor array module relative to the fifth capacitor unit, so that the problem that the occupied center position affects the precision of the more important first capacitor unit to the fifth capacitor unit can be avoided, and the precision of the capacitor array module can be further improved.
In one embodiment, as shown in FIG. 4, capacitive module 2111 is square in a top view.
Based on the description in the foregoing embodiment, it can be known that, since the accuracy of the capacitor in the production process of the capacitor array module is affected by the production process, that is, the closer to the center, the smaller the error is, the higher the accuracy of the capacitor is, and in the same way, for the most basic unit in the capacitor array module, the capacitor module is also affected by the process, and by setting the capacitor module to be a square, it is possible to avoid the influence caused by the different distances from different directions toward the center position when the capacitor module is set to be other shapes, thereby improving the accuracy of the capacitor module itself.
In one embodiment, as shown in fig. 4 and 5, the capacitor array module is disposed on the N-well material;
a plurality of dummy capacitors 121 are disposed in the second region 12, the dummy capacitors 121 are arranged at the same pitch to surround the first region 11, and connection terminals of the dummy capacitors are connected to the N-well substrate guard ring while the N-well substrate guard ring can be used for connecting a high level.
In the present embodiment, the capacitor array module is actually formed by etching a semiconductor material, so that the capacitor array module is required to be disposed on the N-well material side of the semiconductor material in the present embodiment based on the characteristics of the semiconductor material, and the substrate material may be a P-type material, i.e., an N-well region diffused on a P-type substrate. Due to the material characteristics, the dummy capacitors, namely dummy capacitors are arranged around the first area at the same intervals, the connecting ends of the dummy capacitors are connected with the high-level N-well substrate guard ring (guard driving), so that the whole dummy capacitors and the N-well guard ring form a ring-shaped band area surrounding the first area, namely surrounding the capacitor array, and the transfer of hole charges between the screen substrate and the N-well can be realized, so that the coupling influence of adjacent devices on the substrate can be effectively reduced.
In one embodiment, as shown in fig. 6, the capacitance module 2111 is provided with a metal connection terminal formed based on superposition of metal ions; the metal connecting end is provided with a through hole.
In this embodiment, because the link of capacitor module has set up the thickening metal that forms through the metal ion stack, and is provided with through-hole (VIA) to can ensure that unnecessary electric charge does not add up again, this not only can avoid the production of capacitor module parasitic resistance, can also avoid having avoided because of parasitic resistance to the influence of the electric capacity precision of this capacitor module, the change of the electric characteristic of the capacitor unit at capacitor module place.
The embodiment of the application provides a capacitor array module, which comprises a first area and a second area; the first area is used for arranging a capacitor array; the first area is positioned in the central part of the capacitor array module; the second area is located at the edge part in the capacitor array module and is located at the periphery of the first area. In this application, because present capacitor array production technology tends towards the marginal portion more during production, the degradation degree of the basic electric capacity of its production is higher, consequently, the capacitor array module of this application, through set up capacitor array in the first region of central part, rather than around the second region setting, this degree that just can be influenced by the production technology in the follow-up production process reduces, thereby avoid peripheral part to lay the degradation of basic electric capacity when arranging capacitor array and lead to the problem of mismatch between the appearance value proportion of capacitor array, thereby avoided the problem that the normal function of the capacitor array module that leads to producing because of design defect receives the influence, the accuracy nature of capacitor array module has been improved.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A capacitive array module, comprising:
a first region and a second region;
the first area is used for arranging a capacitor array; the first area is positioned in the central part of the capacitor array module;
the second region is located at the edge part in the capacitor array module and is located at the periphery of the first region.
2. The module of claim 1, wherein the capacitive array is a differential dual channel capacitive array;
the differential dual-channel capacitive array includes: a first capacitor array and a second capacitor array;
the first capacitor array and the second capacitor array both comprise a plurality of capacitor units, every two capacitor units in the plurality of capacitor units have equal proportional capacitance values, and the arrangement modes of the plurality of capacitor units are the same in a mirror image manner.
3. The module of claim 2, wherein the first capacitor array comprises: the first capacitor unit, the second capacitor unit, the third capacitor unit, the fourth capacitor unit and the fifth capacitor unit;
the capacitance values of the first capacitance unit, the second capacitance unit, the third capacitance unit, the fourth capacitance unit and the fifth capacitance unit are sequentially multiplied.
4. The module of claim 3, wherein each of the capacitive units in the first capacitive array is comprised of a capacitive module;
wherein the first capacitance unit comprises a capacitance module;
the second capacitor unit comprises two capacitor modules which are arranged in a row;
the third capacitor unit comprises four capacitor modules which are arranged in a row;
the fourth capacitor unit comprises eight capacitor modules which are arranged in a row;
the fifth capacitor unit comprises sixteen capacitor modules, the sixteen capacitor modules are arranged in two rows, and eight capacitor modules are arranged in each row.
5. The module according to claim 3 or 4,
the first capacitor unit, the second capacitor unit and the third capacitor unit are arranged in a first row of the first capacitor array;
the fourth capacitor unit is arranged in a second row of the first capacitor array;
the fifth capacitor unit is arranged in a third row of the second capacitor array;
wherein the first row, the second row and the third row are arranged in sequence from the center to the edge of the capacitor array module.
6. The module according to any one of claims 3-5, wherein the second capacitive unit is disposed between the first capacitive unit and the third capacitive unit.
7. The module of any of claims 3-6, wherein the first capacitive array further comprises: a sixth capacitance unit;
wherein the sixth capacitance unit comprises eight capacitance modules; the eight capacitor modules are arranged in a row; the sixth capacitor unit is arranged on the outer side of the fifth capacitor unit, and the outer side is opposite to the side, close to the edge of the capacitor array module, of the fifth capacitor unit.
8. The module of claim 7, wherein the capacitive module is square in a top view.
9. The module of claim 8, wherein the capacitive array module is disposed in an N-well material;
the second area is provided with a plurality of dummy capacitors, the dummy capacitors are distributed according to the same interval to surround the first area, the connection ends of the dummy capacitors are connected to the N-well substrate protection ring, and the N-well substrate protection ring is used for connecting a high level.
10. The module according to claim 9, wherein the capacitor module is provided with metal connection terminals formed based on superposition of metal ions; the metal connecting end is provided with a through hole.
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| CN202210582226.1A CN114937557A (en) | 2022-05-26 | 2022-05-26 | Capacitor array module |
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