CN107202948B - The circuit test plate of high test density - Google Patents
The circuit test plate of high test density Download PDFInfo
- Publication number
- CN107202948B CN107202948B CN201610156896.1A CN201610156896A CN107202948B CN 107202948 B CN107202948 B CN 107202948B CN 201610156896 A CN201610156896 A CN 201610156896A CN 107202948 B CN107202948 B CN 107202948B
- Authority
- CN
- China
- Prior art keywords
- insulating layer
- layer
- those
- connector
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Measuring Leads Or Probes (AREA)
Abstract
The present invention provides a kind of circuit test plate of high test density, it include a substrate, one first insulating layer, a wiring layer, a second insulating layer, multiple conductive cones, the upper and lower surface of the substrate is respectively equipped with multiple lower electrodes and multiple top electrodes, those lower electrodes are electrically connected with those top electrodes；First insulating layer is arranged in the upper surface of the substrate, the wiring layer is formed in first insulating layer and by least one first connector electrical connections those top electrodes, the second insulating layer is set to first insulating layer, those conduction cones are formed in the second insulating layer with matrix arrangement and are electrically connected the wiring layer by least one second connector, using the wiring layer, first connector, second connector line arrangement, the conduction cone of electrical measurement electric power to part is provided, electrical measurement density is promoted by the arrangement of those conduction cones.
Description
Technical field
The present invention relates to a kind of circuit test plates, refer in particular to a kind of circuit test plate with high test density.
Background technique
The electrical measurement of circuit board be make circuit board one of basic program, for examine circuit board can work well, because
This needs correct and perfect tool to support, and in electrical measurement, a circuit board is often stacked in a test of a measuring device
On jig, which transmits electric power to the test fixture, test fixture selectivity by power transmission to the circuit board
On electrode or tested point, to the circuit board carry out electrical measurement.It please refers to shown in Fig. 5, current test fixture 70 contains a bottom
Plate 71, two spring parts 72, a lifter plate 73, multiple pogo pins 74, a mask plate 75.The bottom plate 71 is formed with multiple shrinkage pools
76, those shrinkage pools 76 are evenly distributed in the surface of the bottom plate 71 with matrix arrangement, and the bottom plate 71 is fixed at two spring parts 72 interval
Surface, the lifter plate 73 are fixed on the top of two spring parts 72 and by two spring parts 72 relative to moving down on the bottom plate 71
It is dynamic, corresponding multiple perforation 77 vertical with those shrinkage pools 76 are formed on the lifter plate 73.
Each pogo pin 74 has a probe 741 and a pars contractilis 742, those pars contractilis 742 are respectively contained in those
The bottom of shrinkage pool 76, respectively the bottom of the probe 741 connects the top of the pars contractilis 742.
When using the test fixture 70 to test a circuit board under test 80, the mask plate 75 should be first prepared, in this
Multiple through-holes 751 are formed on mask plate 75, the position of those through-holes 751 corresponds to the multiple electrodes 81 of the circuit board under test 80
Or tested point.
The mask plate 75 is stacked to the lifter plate 73, and the circuit board under test 80 is placed on the mask plate 75, should
Mask plate 75 and the lifter plate 73 keep the lifter plate 73 mobile towards the bottom plate 71, at this point, having because of two spring part 72 of gravity compressed
Its probe 741 of partial pogo pin 74 passes through the perforation 77 of the lifter plate 73 and the partial through holes 751 of the mask plate 75,
Those probes 741 are made to be respectively electrically connected to those electrodes 81 of the circuit board under test 80, because this of each pogo pin 74 is stretched
Contracting portion 742 is connected with a conducting wire (not shown), those conducting wires transmit electric power to those pogo pins 74, when those probes 741 connect
It transmits electric power when touching to those electrodes 81 to those electrodes 81, electrical measurement is carried out to the test circuit board 80；Wherein, not electric with those
The part pogo pin 74 that pole 81 is arranged vertically, blocking of the probe 741 by the mask plate 75 will not be with the circuit under test
Plate 80 is in contact, and can avoid that short circuit occurs or accidentally contacts remaining conduction region (such as conducting wire) of the circuit board under test 80.
However, current lifter plate 73 needs in order to avoid those pogo pins 74 are mutually touched, there is a situation where short circuit
The spacing between pogo pin 74 is limited, i.e., certain spacing must be kept between those perforation 77, so that those are worn
The distance between adjacent probe head 741 can not shorten in hole 77, and the test density for resulting in current circuit test plate is relatively low, hold
Pogo pin 74, which easily occurs, can not contact all electrodes 81 or tested point of the circuit board under test 80, lead to the place that be powered
The mistake for being not powered on generation test leakage or testing result mistake is surveyed.
It please refers to shown in Fig. 6 A, in order to solve the problems, such as test density deficiency, using the test fixture of another structure,
In stacking an at least accessory plate 78 on the mask plate 75, at least an accessory plate 78 is formed with multiple perforations 781 for this, those flexible spies
Needle 74 wears those perforations 781.Measurement spacing when not tilting those pogo pins 74, between those 74 tops of pogo pin
There to be the electricity of part when the spacing L2 to be measured between the electrode 81 of the circuit board under test 80 is less than measurement spacing L1 for L1
The problem of pole 81 can not be electrically connected the pogo pin 74, and test leakage occurs or accidentally surveys.
It please refers to shown in Fig. 6 B, those perforations when moving horizontally the accessory plate 78, on an at least accessory plate 78
781 meeting horizontal displacements, when the offset distance of displacement is more than the aperture of the perforation 781, the perforation 781 is in displacement process tight against this
Probe 741 and push the probe 741, tilt the probe 741, the position in the aperture of those perforations 781, size with
And the offset distance of displacement determines the tilt angle of the probe 741.If the offset distance of displacement is less than the hole of the perforation 781
Diameter, the pogo pin 74 in the perforation 781 will not generate inclination or tilt angle is smaller, therefore part pogo pin 74 is protected
Hold vertical survey when part pogo pin 74 is tilted towards the direction of not inclined pogo pin 74, between those probes 741
Amount spacing L1 can shorten, and keep the spacing L2 to be measured between the measurement spacing L1 and those electrodes 81 identical, and it is close to promote test
Degree to carry out electrical measurement to circuit board under test 80.
Above-mentioned test fixture tilts those pogo pins 74 by displacement accessory plate 78, although those probes can be reduced
Measurement spacing L1 between 741, but during displacement, frequent occurrence because tilt angle is excessive and pogo pin 74
Length, elasticity it is different, the electrode 81 that cannot connect to the circuit board under test 80 after pogo pin 74 tilts occurs, or only
The edge for touching the electrode 81 causes test abnormal.It is excessive to probe in addition, pogo pin 74 has certain cost
Carrying out inclination will lead to pogo pin 74 often with mask plate 73 or the generation friction of accessory plate 78, destroy, abrasion pogo pin 74
Structure, shorten the reduced service life of pogo pin 74, it is necessary to make a big purchase pogo pin 74 in large quantities so that measurement cost on
It rises.
Summary of the invention
Via described above it is known that current circuit board testing device has the problem of test density deficiency, if
Tilt telescopic probe can then be prone to wear, destroy probe structure or cause to contact not with the electrode of circuit board because of curtailment
Good is very to the problem of can not contacting, in view of this, system of the present invention provides a kind of circuit test plate of high test density, Lai Gaishan
Problem above.
Technical way used in order to achieve the above object is to enable the circuit test plate of the high test density include
Have:
One substrate has a lower surface and a upper surface；
Multiple lower electrodes are formed in the lower surface of the substrate；
Multiple top electrodes are formed in the upper surface of the substrate and are electrically connected respectively with those lower electrodes；
One first insulating layer is set to the upper surface of the substrate, which has at least one first connector,
Respectively this at least one first connector is electrically connected those corresponding top electrodes；
One wiring layer is formed in the surface of first insulating layer and is electrically connected at least one first connector, with electrical connection
Those top electrodes；
One second insulating layer is set to the surface of first insulating layer, and the second insulating layer is at least one second connection
Part, respectively second connector is electrically connected the wiring layer；And
Multiple conductive cones, are formed in the surface of the second insulating layer and are electrically connected respectively at least one second connector,
Multiple conductive cone is in electrical contact with a circuit board under test.
By the above structure it is known that those conduction cones are for multiple tested points connection on a circuit board to be measured, the base
Those lower electrodes of plate are connected for an outer lead, to transmit electric power to those top electrodes, the top electrode utilize the wiring layer,
At least one first connector, at least one second connector are selected power transmission to the part for having connected those tested points
Those conduction cones, the conductive cone of not connected tested point do not receive electric power then, and the present invention uses those conduction cones to use as test
Probe, which conductive cone is provided using the wiring layer, at least one first connector, at least one second connector selection
Electric power can test the circuit board.The present invention replaces conventional probe using conductive cone, effectively promotes measurement density, in
In high density electrical testing, without flexure probe, testing procedure can be simplified, shorten the testing time, in addition, using electricity of the invention
Drive test test plate (panel) can not only reduce testing cost, there are no installing, replace the problem of probe without buying more probe.
Detailed description of the invention
Fig. 1 is diagrammatic cross-section of the invention；
Fig. 2 is stereoscopic schematic diagram of the invention；
Fig. 3 is the diagrammatic cross-section of conductive cone of the invention；
Fig. 4 is the diagrammatic cross-section that electrical measurement is carried out using the present invention；
Fig. 5 is the diagrammatic cross-section of existing circuit testing jig；
Fig. 6 A is the diagrammatic cross-section of its another embodiment of existing circuit testing jig；
Fig. 6 B is the operation chart of its another embodiment of existing circuit testing jig.
Appended drawing reference
10 substrate, 11 lower surface
12 upper surface, 13 conducting piece
21 lower 22 top electrodes of electrode
23 wiring layer, 24 connection electrode
25 surface electrode, 30 first insulating layer
31 first insulating surface, 32 first through hole
33 first connector, 40 second insulating layer
41 second insulating surface, 42 second through-hole
The conductive cone of 43 second connector 50
51 conductive layer, 52 strengthening layer
53 anti oxidation layer, 60 circuit board under test
61 tested point, 70 test fixture
71 bottom plate, 72 spring part
73 lifter plate, 74 pogo pin
741 probe, 742 pars contractilis
75 mask plate, 751 through-hole
The perforation of 76 shrinkage pools 77
78 accessory plate, 781 perforation
80 circuit board under test, 81 electrode
Specific embodiment
As shown in Figs.1 and 2, the present invention provides a kind of circuit test plate of high test density, includes: a substrate
10, multiple lower electrodes 21, multiple top electrodes 22, one first insulating layer 30, a wiring layer 23, multiple connection electrodes 24, one second
Insulating layer 40, multiple surface electrodes 25, multiple conductive cones 50.
The substrate 10 is a ceramic substrate, which has table on a lower surface 11 and opposite with the lower surface 11 one
Face 12.
Those lower electrodes 21 are formed in the lower surface 11 of the substrate 10, between those lower electrodes 21 arrange simultaneously in a matrix fashion
Every setting.Those top electrodes 22 are formed in the upper surface 12 of the substrate 10, and each top electrode 22 is hung down with each lower electrode 21 respectively
Straight corresponding arrangement, wherein the substrate 10 is respectively formed with multiple conducting pieces between electrode 21 and those top electrodes 22 under those
13, each 13 both ends of conducting shell are electrically connected electrode 21 and a top electrode 22.
First insulating layer 30 covers upper surface 12 and those top electrodes 22, which has one first insulation
Surface 31, at least a first through hole 32, at least one first connector 33.First insulating surface 31 refers to first insulating layer 30
Upper surface；An at least first through hole 32 is through first insulating layer 30 and adjacent and right with those top electrodes 22 of part
Together, this at least a connection piece 33 is formed in an at least first through hole 32 and is electrically connected with those part top electrodes 22.
The wiring layer 23 and those connection electrodes 24 are formed in first insulating surface 31, which connect with those
Electrode 24 is electrically connected；Those connection electrodes 24 those connection electrodes 24 arranged in a straight line and partial with those top electrodes 22 with should
The electrical connection of at least one first connector 33, makes the wiring layer 23 and those connection electrodes 24 via at least one first connector 33
It is electrically connected with part top electrode 22.The second insulating layer 40 covers first insulating surface 31, the wiring layer 23 and those connections
Electrode 24, the second insulating layer 40 have one second insulating surface 41, at least one second through-hole 42, at least one second connector
43.Second insulating surface 41 refers to the upper surface of the second insulating layer 40；At least one second through-hole 42 through this second absolutely
Edge layer 40 is simultaneously abutted and is aligned with those connection electrodes 24 of part, which is formed in this at least
It is electrically connected in one second through-hole 42 and with those part connection electrodes 24.
Those surface electrodes 25 are formed in second insulating surface 41, those surface electrodes 25 and those connection electrodes 24
Those surface electrodes 25 arranged in a straight line and partial are electrically connected at least one second connector 43, make those surfaces electricity of part
Pole 25 is electrically connected via at least one second connector 43 with those part connection electrodes 24.
Those conduction cones 50 are respectively formed on those surface electrodes 25 and are electrically connected with those surface electrodes 25, those are led
Electricity 50 its shape of cone are in tapered along the vertical direction of second insulating surface 41.It please refers to shown in Fig. 3, conduction cone 50 further includes
There are a conductive layer 51, strengthening layer 52, an anti oxidation layer 53.The strengthening layer 52 coats the conductive layer 51, the anti oxidation layer 53 cladding
The strengthening layer 52；The hardness of the strengthening layer 52 is greater than the conductive layer 51, to promote the intensity of conduction cone 50, the conduction is made to bore 50
With enough intensity to support circuit board to be measured；The oxide layer 53 coats the strengthening layer 52, the conductive layer 51, due to those
Conduction cone 50 is the tested point to be electrically connected on circuit board under test, to avoid its electric conductivity from declining because of oxidation, therefore is utilized
The buffer layer that the anti-ization layer 53 is contacted as those conduction cones 50 with outside air, to prevent those 50 oxidations of conduction cone.
The material of the conductive layer 51 can be copper or its alloy；The material of the strengthening layer 52 can be nickel, cobalt, tungsten or its alloy；
The material of the anti oxidation layer 53 can be gold, tin or its alloy, and in present embodiment, the material of the strengthening layer 52 is nickel cobalt (alloy)
Or nickel tungsten, wherein the ratio of nickel accounts for 97 95 percent to percent in the nickel cobalt (alloy) or the nickel tungsten
Between.
It please refers to shown in Fig. 4, it, will when carrying out electrical testing to a circuit board under test 60 using circuit test plate of the invention
The circuit test plate is installed in a test device (not shown) and connects the conductive plate in the test device or multiple conducting wires (not
Show), and the circuit board under test 60 is set on those conduction cones 50, by the tested point 61 (or electrode) of the test circuit board 60
Those conduction cones 50 are contacted respectively.Test device utilizes the conductive plate or those conducting wires to those lower electrodes of the circuit test plate
21 transmission electric power, by power transmission to the circuit test plate.Wherein, the circuit test plate using the wiring layer 23, this at least
The configuration of one first connector 33, at least one second connector 43, the electric power of the measuring device is transferred to by selection to be wanted
Contact those tested points 61 those conduction cone 50, to carry out electrical property or circuit test to the slowdown monitoring circuit plate 60, in order in response to
The wiring layer 23, at least one first connection can be changed in the position arrangement or variant of different 60 tested points 61 of circuit board under test
The layout of part 33, at least one second connector 43 adjusts the path of electric current, which conductive cone 50 control electric power will be transmitted to,
Therefore, the layout and the circuit board under test of the wiring layer 23, at least one first connector 33, at least one second connector 43
Tested point 61 on 60 corresponds to each other.
The structure of circuit test plate of the invention can be manufactured using existing circuit-board processes at present, which is somebody's turn to do
At least one first connector 33, at least one second connector 43 configuration then by the electrode 61 of the circuit board under test 60
It is correspondingly formed, makes the supplier of current circuit board using current existing material, can be completed and obtain high test of the invention
The circuit test plate of density, keeps the electrical measurement of circuit board more easy.
Existing pogo pin is not used to connect the tested point 61 of circuit board under test 60 in the present invention, and test of the invention is close
Degree is not only restricted to the spacing limitation of existing pogo pin.The present invention only needs to avoid those surface electrodes under those conduction cones 50
Conductive cone 50 highdensity can be arranged in 25 contacts, and circuit test plate of the invention can be via existing electricity
Road plate technique is completed, therefore, the minimum spacing that minimum spacing and circuit board industry between those conduction cones 50 can be formed at present
It is identical, the distance between tested point 61 on circuit board under test 60 will not occur and be less than between those conduction cones 50 of the invention
Distance, even if line footpath, the line width of its circuit board of industry become small at present, but the technology and circuit of circuit test plate of the invention
Plate manufacturing technology is identical, and it is insufficient to solve at present test density when for electrical measurement with industrial technology Synchronous lifting for test density
The problem of.
In conclusion the circuit test plate of the high test density of the present invention, uses the wiring layer, at least one first connection
The configuration of part, at least one second connector, enables electric power to be transmitted to the test point for needing to connect circuit board under test
Conduction cone, and because conductive cone highdensity can arrange, when so that carrying out electrical measurement using the present invention, with higher it can survey
Try density.In addition, structure of the invention can be completed using existing circuit-board processes, keep the acquirement of circuit test plate simpler
It is single, and when carrying out electrical measurement using the present invention, without device, replacement probe, electrical measurement efficiency can be promoted, the material of electrical measurement can be also reduced
Expect cost, and the spacing between conductive cone is identical as the current achievable electrode spacing of circuit board industry, makes test of the invention
Density can increase with the progress of circuit board industry, the electricity smaller and smaller even for line footpath, production precision is higher and higher
Road plate carries out electrical measurement, can all smoothly complete, and improves the defect that tradition carries out electrical measurement using probe.
Internal structure of the invention is disclosed via the content of present invention, has absolutely proved internal structure, action specification and effect,
It is in fact having had the important document applied for a patent；Wherein, content of the present invention is not limited only as the explanation of embodiment with this
Fixed scope of protection of the present invention, any local change, variation structure, still fall within the scope of protection of the invention.
Claims (10)
1. a kind of circuit test plate of high test density, which is characterized in that the circuit test plate includes:
One substrate has a lower surface and a upper surface；
Multiple lower electrodes are formed in the lower surface of the substrate；
Multiple top electrodes are formed in the upper surface of the substrate and are electrically connected respectively with the multiple lower electrode；
One first insulating layer is set to the upper surface of the substrate, and first insulating layer is at least one first connection
Part, each at least one first connector are electrically connected corresponding the multiple top electrode；
One wiring layer is formed in the surface of first insulating layer and is electrically connected at least one first connector, with electrical connection
The multiple top electrode；
One second insulating layer is set to the surface of first insulating layer, and the second insulating layer is at least one second connection
Part, each second connector are electrically connected the wiring layer；And
Multiple conductive cones are formed in the surface of the second insulating layer and are electrically connected each at least one second connector,
The multiple conductive cone is in electrical contact with a circuit board under test.
2. the circuit test plate of high test density according to claim 1, which is characterized in that each conductive cone further includes
Have:
One conductive layer；
One strengthening layer is coated in the conductive layer；
One anti oxidation layer is coated in the strengthening layer.
3. the circuit test plate of high test density according to claim 2, which is characterized in that the material of the conductive layer is
Copper or its alloy.
4. the circuit test plate of high test density according to claim 2, which is characterized in that the material of the strengthening layer is
Nickel, cobalt, tungsten, nickel cobalt (alloy) or nickel tungsten.
5. the circuit test plate of high test density according to claim 2, which is characterized in that the anti oxidation layer material is
Gold or tin.
6. according to claim 1 to the circuit test plate of high test density described in any claim in 5, which is characterized in that
The substrate is ceramic substrate.
7. according to claim 1 to the circuit test plate of high test density described in any claim in 5, which is characterized in that
Multiple surface electrodes are formed in the surface of the second insulating layer, the multiple surface electrode electrical connection described at least one second connects
Fitting, and each conductive cone is respectively arranged on the multiple surface electrode.
8. the circuit test plate of high test density according to claim 7, which is characterized in that the wiring layer has further included
Multiple connection electrodes, the multiple connection electrode are electrically connected at least one first connector, at least one second connector.
9. the circuit test plate of high test density according to claim 8, which is characterized in that the multiple connection electrode,
The multiple surface electrode, the multiple top electrode, the multiple lower electrode are to be vertically arranged.
10. according to claim 1 to the circuit test plate of high test density described in any claim in 5, which is characterized in that
First insulating layer covers the upper surface of the substrate and the multiple top electrode, the second insulating layer cover described first
The surface of insulating layer and the wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610156896.1A CN107202948B (en) | 2016-03-18 | 2016-03-18 | The circuit test plate of high test density |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610156896.1A CN107202948B (en) | 2016-03-18 | 2016-03-18 | The circuit test plate of high test density |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107202948A CN107202948A (en) | 2017-09-26 |
| CN107202948B true CN107202948B (en) | 2019-09-24 |
Family
ID=59904308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610156896.1A Active CN107202948B (en) | 2016-03-18 | 2016-03-18 | The circuit test plate of high test density |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107202948B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108709909B (en) * | 2018-06-25 | 2023-06-30 | 中国地质大学（武汉） | Electrode device based on EIT nondestructive test cement-based flat plate |
| CN110426536A (en) * | 2019-07-29 | 2019-11-08 | 重庆伟鼎电子科技有限公司 | PCB conductive fabric measurement circuit plate |
| CN111014057A (en) * | 2019-12-05 | 2020-04-17 | 临海市锦铮机械有限公司 | Brain wave sensor resistance automatic detection machine |
| CN117288824B (en) * | 2023-11-23 | 2024-03-19 | 有研(广东)新材料技术研究院 | Test system based on silicon nanowire field effect sensor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002310933A (en) * | 2001-04-17 | 2002-10-23 | Nidec-Read Corp | Apparatus and method for inspection of circuit board as well as electro-optical element |
| CN1452231A (en) * | 2002-04-18 | 2003-10-29 | 三菱电机株式会社 | Testing board for testing semiconductor |
| CN1985180A (en) * | 2004-07-15 | 2007-06-20 | Jsr株式会社 | Device and method for inspection of circuit board |
| CN201681141U (en) * | 2010-04-02 | 2010-12-22 | 徐宇震 | Combined density tester for printed circuit board |
| JP2015195272A (en) * | 2014-03-31 | 2015-11-05 | 新光電気工業株式会社 | Semiconductor device and semiconductor manufacturing method |
-
2016
- 2016-03-18 CN CN201610156896.1A patent/CN107202948B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002310933A (en) * | 2001-04-17 | 2002-10-23 | Nidec-Read Corp | Apparatus and method for inspection of circuit board as well as electro-optical element |
| CN1452231A (en) * | 2002-04-18 | 2003-10-29 | 三菱电机株式会社 | Testing board for testing semiconductor |
| CN1985180A (en) * | 2004-07-15 | 2007-06-20 | Jsr株式会社 | Device and method for inspection of circuit board |
| CN201681141U (en) * | 2010-04-02 | 2010-12-22 | 徐宇震 | Combined density tester for printed circuit board |
| JP2015195272A (en) * | 2014-03-31 | 2015-11-05 | 新光電気工業株式会社 | Semiconductor device and semiconductor manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107202948A (en) | 2017-09-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107202948B (en) | The circuit test plate of high test density | |
| CN101322035B (en) | Probe card | |
| CN102483435B (en) | For conduction Kelvin's contact of microcircuit tester | |
| US9733299B2 (en) | Inspection jig | |
| TWI524073B (en) | Contact inspection device | |
| KR20160063286A (en) | Contact inspection device | |
| KR20120024541A (en) | Electrically conductive pins for microcircuit tester | |
| JPS63256873A (en) | Electrical-function test apparatus for wiring panel | |
| JPWO2020145073A1 (en) | Contact terminals, inspection jigs, and inspection equipment | |
| KR20100069300A (en) | Probe card, and apparatus and method for testing semiconductor device | |
| JPWO2009011201A1 (en) | Inspection structure | |
| JP2017036997A (en) | Inspection device and inspection method of double-sided circuit board | |
| JP2016082179A (en) | Semiconductor evaluation device and evaluation method | |
| JP5836872B2 (en) | Semiconductor device characteristic evaluation system | |
| TW202332918A (en) | Spring probe assembly for a kelvin testing system | |
| JP5987447B2 (en) | Inspection device | |
| CN210323276U (en) | High-test-density circuit test board | |
| KR20040067794A (en) | Semiconductor device having pad | |
| TW201415040A (en) | Method of manufacturing for electric inspection jig | |
| US10371719B2 (en) | Printed circuit board circuit test fixture with adjustable density of test probes mounted thereon | |
| CN103837715B (en) | Fixture | |
| KR101397373B1 (en) | Jig for electrical inspection | |
| JP2022045831A (en) | Inspection device | |
| JP2010066031A (en) | Circuit board inspection apparatus | |
| US8366477B2 (en) | Electrical connecting apparatus and contacts used therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |