CN107194127A - A kind of transistor modeling method based on burst pulse weak-signal measurement - Google Patents
A kind of transistor modeling method based on burst pulse weak-signal measurement Download PDFInfo
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Abstract
The invention discloses a kind of transistor modeling method based on burst pulse weak-signal measurement in field of transistors, comprise the following steps：1）Go it is embedding, using transistor it is corresponding open circuit, short-circuit structure to transistor carry out S parameter go it is embedding；2）External parameter is extracted, and ectoparasitism parameter is extracted from open circuit, short-circuit structure S parameter；3）Set up constitutive relation, to go it is embedding after S Parameters of Transistor handle, determine each rank current source and each rank Charge Source needed for the transistor model；4）Training fitting, respectively described current source is trained or is fitted with Charge Source；5）Modeling, each rank current source trained or be fitted and Charge Source are imported into circuit simulating software, encapsulation forms the large-signal model of the transistor, small-signal equivalent circuit of the present invention without transistor internal, the constitutive relation of port voltage and electric current is directly extracted using burst pulse weak-signal measurement data, so as to set up the complete model of transistor, available in transistor modeling.
Description
Technical field
The present invention relates to a kind of modeling method, more particularly to a kind of transistor modeling method.
Background technology
High-quality transistor, system model are to non-linear microwave radio circuit, list based on CAD (CAD)
Piece microwave integrated circuit (MMICs), power amplifier (PAs) and non-linear radio frequency system are most important.With semiconductor technology
And its sustained and rapid development is applied, the power and working frequency of device constantly rise, and occur in that more complicated communication letter
Number transmission (the high standing-wave ratio signals of such as modern communicationses), exploitation high-precision radio frequency device and system model in order to semiconductor
Circuit design is very urgent.
Conventional transistor modeling side is based on device small-signal equivalent circuit, and the equivalent circuit optimized or parsing is obtained is joined
Numerical value, which is integrated, obtains current source and Charge Source, or parameter value directly is imported into progress emulation mould in circuit simulating software
Intend.However as new material, the appearance of new technology, conventional small-signal equivalent circuit can not accurate description device inside row
For.Such as the gallium nitride transistor that power density is big, caloric value is high, if directly using traditional small-signal equivalent circuit, device
Non-quasi-static effect, self-heating effect and trap effect are difficult to be accurately modeled.If increasing the quantity of parameter in equivalent circuit,
Complexity is improved come the behavior of the device for the manufacture that describes to adopt new technology, then extracting the difficulty of these parameters will increase greatly
Plus, and the accuracy of final modeling result can not be ensured.Therefore the transistor modeling side that exploitation can adapt to different process is needed badly
Method.
The content of the invention
It is an object of the invention to provide a kind of transistor modeling method based on burst pulse weak-signal measurement, without transistor
Internal small-signal equivalent circuit, directly extracts the constitutive relation of port voltage and electric current using burst pulse weak-signal measurement data
(current source and Charge Source), so as to set up the complete model of transistor.
The object of the present invention is achieved like this：A kind of transistor modeling method based on burst pulse weak-signal measurement, bag
Include following steps：
1) go it is embedding, using the corresponding open-circuit structure of transistor, short-circuit structure to transistor carry out S parameter go it is embedding；
2) external parameter is extracted, and is extracted with the method for parsing or global optimization from the open circuit, short-circuit structure S parameter
Ectoparasitism parameter；
3) set up constitutive relation, to go it is embedding after S Parameters of Transistor handle, needed for determining the transistor model
Each rank current source and each rank Charge Source；
4) training fitting, respectively described current source is trained or is fitted with Charge Source；
5) model, each rank current source trained or be fitted and Charge Source are imported into circuit simulating software, and add
Step 2) ectoparasitism parameter, encapsulation forms the large-signal model of the transistor.
It is used as the further restriction of the present invention, step 1) specific method is：
1-1) burst pulse S parameter of the measurement transistor at multiple temperature and multiple quiescent biasings；
1-2) measure the S parameter for being used to remove embedding open-circuit structure, short-circuit structure corresponding with the transistor；
1-3) progress of burst pulse S parameter is gone using the S parameter of open-circuit structure, short-circuit structure embedding.
It is used as the further restriction of the present invention, step 1-3) specific method is：
The burst pulse S parameter of measurement is converted into Y parameter, open-circuit structure S parameter is also converted into Y parameter, the two
Result is converted into Z after subtracting each other1Parameter；Short-circuit structure S parameter is converted into Y parameter, after the Y parameter for subtracting open-circuit structure
It is converted into Z2Parameter, then subtract each other with the result in step 1 and obtain final Z3Parameter, Z3=Z1-Z2。
It is used as the further restriction of the present invention, step 3) specific method is：
3-1) embedding burst pulse S parameter will be gone to be converted into Y parameter, the real part of Y parameter is carried out on many of angular frequency
Item formula expansion, carries out the polynomial expansion on angular frequency again after the imaginary part of Y parameter and angular frequency are divided by；
3-2) the precision according to needed for model, it is determined that the top step number of the fitting of a polynomial parameter needed, and then determine crystal
Current source, the top step number of Charge Source needed for tube model；
3-3) multinomial coefficient of the Y parameter real part is integrated according to top step number, each rank electric current is obtained
Source；The Y parameter imaginary part and the multinomial coefficient of the business of angular frequency are integrated, each rank Charge Source is obtained
Be used as the present invention further restriction, step 4) specific method be：
Respectively described current source artificial neural network topological structure corresponding with Charge Source structure, and utilize intelligent optimization
Technology is trained to the current source with electric charge source data respectively；Or using empirical equation model to the current source and electricity
He Yuan is fitted.
As the further restriction of the present invention, the empirical equation model for being fitted the current source and Charge Source includes
Staz models, Angelov models, Curtice models.
As the further restriction of the present invention, it is additionally included in the artificial neural network topological structure and adds fuel factor
The step of circuit and trap effect sub-circuit.
Compared with prior art, the beneficial effects of the present invention are：The present invention is directly using weak-signal measurement data come structure
Current source and Charge Source in established model, and do not need specific equivalent circuit to describe the structure of transistor internal, therefore energy
Enough it is adapted to the transistor device under various different process, such as GaAs field effect transistor, gallium nitride FET etc.；Also, on
Method is stated when building current source and Charge Source, in the input layer or empirical equation model of artificial neural network topological structure
In input variable, addition channel temperature variable and environment temperature variable and the quantity of state for describing trap effect, so as to right
The memory effects such as self-heating, the trap effect of transistor are effectively modeled；In addition, in artificial neural network topological structure is obtained
Weight or empirical equation model in fitting parameter during, employ the wheat quart method and artificial intelligence of back-propagating
Energy optimized algorithm, can obtain globally optimal solution with very high probability, so as to provide strong for the high accuracy modeling of transistor
Ensure.
Brief description of the drawings
Fig. 1 is flow chart of the present invention.
Fig. 2 is field-effect tube model schematic diagram in embodiment.
Fig. 3 is the schematic diagram of fuel factor sub-circuit in embodiment.
Fig. 4 is the schematic diagram of trap effect sub-circuit in embodiment
Embodiment
With reference to embodiment, the present invention will be further described.
A kind of transistor modeling method based on burst pulse weak-signal measurement as shown in Figure 1, comprises the following steps：
S101 measures burst pulse S parameter of the transistor at multiple temperature and multiple quiescent biasings；
The S102 measurements S parameter for being used to remove embedding open-circuit structure, short-circuit structure corresponding with the transistor, meanwhile, carry
Take out open-circuit structure, the outside equivalent parasitic parameter of the S parameter of short-circuit structure；
S103 carries out going embedding using the S parameter of open-circuit structure, short-circuit structure to burst pulse S parameter, and specific method is：It will survey
The burst pulse S parameter of amount is converted into Y parameter, and open-circuit structure S parameter is also converted into Y parameter, and the two will knot after subtracting each other
Fruit is converted into Z1Parameter；Short-circuit structure S parameter is converted into Y parameter, Z is converted into after the Y parameter for subtracting open-circuit structure2Parameter,
Subtract each other again with the result in step 1 and obtain final Z3Parameter (as go embedding after burst pulse S parameter), Z3=Z1-Z2；
S104 will go embedding burst pulse S parameter to be converted into Y parameter, and the real part of Y parameter is carried out on many of angular frequency
Item formula expansion, carries out the polynomial expansion on angular frequency again after the imaginary part of Y parameter and angular frequency are divided by；
S105 precision according to needed for model, it is determined that the top step number of the fitting of a polynomial parameter needed, and then determine described
The top step number of constitutive relation needed for transistor model (current source and Charge Source), exponent number is higher, and the model accuracy of acquisition is higher；
S106 is integrated according to top step number to the multinomial coefficient of the Y parameter real part, obtains each rank electric current
Source；The Y parameter imaginary part and the multinomial coefficient of the business of angular frequency are integrated, each rank Charge Source is obtained；
S107 is respectively current source artificial neural network topological structure corresponding with Charge Source structure, in the model
Fuel factor sub-circuit and trap effect sub-circuit step are added in topological structure, and using Intelligent Optimization Technique respectively to the electricity
Stream source is trained with electric charge source data；Or the current source and Charge Source are fitted using empirical equation model, use
Include Staz models, Angelov models, Curtice models in the empirical equation model for being fitted the current source and Charge Source；
Each rank current source trained or be fitted and Charge Source are imported circuit simulating software, addition outside etc. by S108
Parasitic parameter is imitated, encapsulation forms the large-signal model of the transistor.
By taking the modeling of gallium nitride FET as an example, this method is described in detail.
Burst pulse S parameter measurement of the gallium nitride FET at different temperatures and under different quiescent biasings is obtained first
Data；The temperature of environment, example where the gallium nitride FET can be controlled using temperature controller (Temperature Chamber)
Such as, the operating temperature that can control the gallium nitride FET is 25 degrees Celsius, 50 degrees Celsius, 75 degrees Celsius, 100 degrees Celsius
Deng；Under different operating temperatures, using the apparatus measures such as microwave vector network analyzer and pulse signal generator, this is imitated
Should burst pulse S parameter of the pipe under different quiescent biasings；The setting of pulse voltage needs the working range of covering transistor, such as
Grid impulse voltage (Vgs) can at equal intervals be chosen in the range of less than pinch-off voltage to certain forward bias, and the pulse electricity that drains
Press (Vds) then can be from zero to the workable maximum drain voltages of gallium nitride FET institute in the range of, choose at equal intervals；Example
Such as VgsFrom -6V to 1V, at intervals of 0.25V；VDS is from 0V to 60V, at intervals of 2V；The selection of static bias voltage needs to ensure to be somebody's turn to do
Gallium nitride FET does not have quiescent dissipation power.
Then using microwave vector network analyzer pair open circuit corresponding with the gallium nitride FET, the S of short-circuit structure
Parameter is measured；To be opened a way by matrix computations, the ectoparasitism parameter represented by short-circuit structure go it is embedding fall；While for ease of
By expression of the parasitic parameter in circuit simulating software, tied using the method for parsing or global optimization from the open circuit, short circuit
Ectoparasitism parameter is extracted in structure S parameter, the ectoparasitism topological structure that an example of the present invention is used is such as square frame in Fig. 2
External representation, including Cpg、Cpd、Cpgd、Lg、Rg、Ld、Rd、Ls、Rs。
The embedding concrete operations flow is gone to be using the open circuit, short-circuit structure S parameter：
Step 1) the burst pulse S parameter of measurement is converted into Y parameter, open-circuit structure S parameter is also converted into Y ginsengs
Number, result is converted into Z by the two after subtracting each other1Parameter；
Z1=(YDUT-Yopen)-1
Step 2) short-circuit structure S parameter is converted into Y parameter, it is converted into Z after the Y parameter for subtracting open-circuit structure2Parameter,
Z2=(Yshort-Yopen)-1
Step 3) by step 1) in result and step 2) in result subtract each other, obtain it is embedding after burst pulse S parameter；
Z3=Z1-Z2=(YDUT-Yopen)-1-(Yshort-Yopen)-1
Step 4) by step 3) in obtained result be converted into Y parameter；
Obtain it is embedding after transistor internal Y parameter (Yint) after, the multinomial on angular frequency is carried out to its real part
Expansion；By imaginary part is corresponding with angular frequency be divided by after do polynomial expansion on angular frequency again：
Wherein, ReijFor the real part of Y parameter, ImijFor the imaginary part of Y parameter.WithFor multinomial coefficient；
The multinomial coefficient of the Y parameter real part is integrated, each rank current source is obtainedWithK is electricity
The exponent number in stream source；
The Y parameter imaginary part and the multinomial coefficient of the business of angular frequency are integrated, each rank Charge Source is obtainedWithK is the exponent number of Charge Source；
Due to serious spontaneous fuel factor, fuel factor sub-circuit need to be introduced when being modeled to the gallium nitride FET；The heat
Effect sub-circuit is as shown in figure 3, wherein Pdiss=Vds×IdsRepresent the dissipated power of FET, RthRepresent FET
Thermal resistance, TambRepresent environment temperature, Δ TjRepresent the temperature change of raceway groove.PdissAverage value can be by measuring and calculating
Arrive, the environment temperature controlled by temperature controller is Tamb, channel temperature change Delta T caused by device spontaneous heatingjP can be passed throughdissMultiply
With thermal resistance RthObtain, i.e. Δ Tj=Rth×Pdiss=Rth×Vds×Ids, final channel temperature is T=Δs Tj+Tamb。
Simultaneously because also there is obvious trap effect in the gallium nitride FET, it is therefore desirable to introduce to describe trap
The sub-circuit of effect；The sub-circuit comprising two extreme values as shown in figure 4, extract circuit, and the trap for being respectively intended to portray grid is imitated
Should be with drain electrode trap effect；VgsWith VdsGrid and the instantaneous voltage of drain electrode, R are represented respectivelyg_capt, Rg_emitAnd Cg_trapFor counting
Calculate the time constant of capture electronics and release electronics in grid trap effect；Rd_capt, Rd_emitAnd Cd_trapFor calculating drain electrode
The time constant of electronics and release electronics is captured in trap effect.Diode direction difference causes the son on the left side in Fig. 4 sub-circuits
Circuit can extract VgsMinimum value φG, and the sub-circuit on the right can extract VdsMaximum φD。
The burst pulse S parameter measurement data is carried out under different environment temperatures and quiescent biasing respectively, therefore from
To measurement data in the current source that extracts and Charge Source with five dimensions, i.e.,
VgsFor with VdsFor pulse voltage, φGWith φDTo describe the quantity of state of trap effect,
φG=min (Vgs,VGSQ)
φD=max (Vds,VDSQ)
VGSQWith VDSQQuiescent biasing when being measured for burst pulse.
Respectively described current source artificial neural network topological structure corresponding with Charge Source structure, and utilize intelligent optimization
Technology is trained to the current source with electric charge source data respectively；Or using empirical equation model to the current source and electricity
He Yuan is fitted；
For each rank current sourceWith Charge SourceDifferent neutral net topology knots are chosen respectively
Structure, and optimization is trained to the weight of network；Five dimensions of the input layer of artificial neural network are pulse voltage V respectivelygs
With Vds, trapping state amount φGWith φD, work temperature；The method for training optimization is as follows：
First, using intelligent algorithm, the current source and electric charge source data, optimization lineup's work obtained according to extraction
The weight initial value of neural network；
Then, the weight initial value based on this group of artificial neural network, using the wheat quart method (Back of back-propagating
Propagation Levenberg-Marquardt), according to obtained current source and electric charge source data is extracted, to artificial neuron
The weight at networking is trained and suboptimization again, obtains final global optimum's weight；
By the way that the training to all rank current sources and Charge Source can be respectively completed with upper type.Wherein, the people of use
Work intelligent algorithm and the wheat quart method of back-propagating are the known technology means of this area, be will not be repeated here.In other realities
Apply in example, the methods such as steepest decline, Newton iteration can also be used to realize the optimization of artificial neural network weight.
For the drain current source of zeroth orderDrain charge sourceAnd gate charge sourceAlso experience can be taken
Formula model gempiricalData are optimized with fitting.Empirical equation model can based on Staz models, Angelov models,
Curtice models etc.；The method of fitting is as follows：
First, according to the five of input variable dimensions, pulse voltage Vgs and Vds, trapping state amount φ G and φ D and work
Temperature T, it is determined that the empirical equation model and required fitting parameter that need to use；
Then, based on selected empirical equation, using extracted current source and electric charge source data, calculated using artificial intelligence
Method obtains global optimum's fitting parameter.
The current source is fitted or trained after completion by above-mentioned steps with Charge Source, is conducted into circuit simulation soft
Part, and fuel factor sub-circuit, trap effect sub-circuit, ectoparasitism inductance, electric capacity and resistance are added, encapsulation forms gallium nitride
The large-signal model of effect pipe；By taking Advanced Design System as an example, can use user defined model or
Person symbolically defined model realize the big signal mode of the gallium nitride FET based on artificial neural network
The importing of type；During importing, the structure between each rank current source, Charge Source and parasitic parameter as shown in Figure 2, wherein rectangle frame
Internal representation go it is embedding after gallium nitride FET structure；Theoretically the Non-quasi-static effect of accurate description device, is needed
The current source wanted is infinity with Charge Source exponent number, but it can be intercepted according to required modeling accuracy, i.e., only
Highest second order or three ranks are needed just to can reach more satisfied modeling result.
The invention is not limited in above-described embodiment, on the basis of technical scheme disclosed by the invention, the skill of this area
Art personnel are according to disclosed technology contents, it is not necessary to which performing creative labour just can make one to some of which technical characteristic
A little to replace and deform, these are replaced and deformed within the scope of the present invention.
Claims (7)
1. a kind of transistor modeling method based on burst pulse weak-signal measurement, it is characterised in that comprise the following steps：
1）Go it is embedding, using the corresponding open-circuit structure of transistor, short-circuit structure to transistor carry out S parameter go it is embedding；
2）External parameter is extracted, and extracts outside from the open circuit, short-circuit structure S parameter with the method for parsing or global optimization
Parasitic parameter；
3）Set up constitutive relation, to go it is embedding after S Parameters of Transistor handle, determine each rank needed for the transistor model
Current source and each rank Charge Source；
4）Training fitting, respectively described current source is trained or is fitted with Charge Source；
5）Modeling, imports circuit simulating software, and add step by each rank current source trained or be fitted and Charge Source
2）Ectoparasitism parameter, encapsulation forms the large-signal model of the transistor.
2. a kind of transistor modeling method based on burst pulse weak-signal measurement according to claim 1, it is characterised in that
Step 1）Specific method is：
1-1）Measure burst pulse S parameter of the transistor at multiple temperature and multiple quiescent biasings；
1-2）The measurement S parameter for being used to remove embedding open-circuit structure, short-circuit structure corresponding with the transistor；
1-3）The progress of burst pulse S parameter is gone using the S parameter of open-circuit structure, short-circuit structure embedding.
3. a kind of transistor modeling method based on burst pulse weak-signal measurement according to claim 2, it is characterised in that
Step 1-3）Specific method is：
The burst pulse S parameter of measurement is converted into Y parameter, open-circuit structure S parameter Y parameter is also converted into, the two subtracts each other
Result is converted into Z afterwards1Parameter；Short-circuit structure S parameter is converted into Y parameter, conversion after the Y parameter of open-circuit structure is subtracted
For Z2Parameter, then subtract each other with the result in step 1 and obtain final Z3Parameter, Z3= Z1- Z2 。
4. a kind of transistor modeling method based on burst pulse weak-signal measurement according to claim 2, it is characterised in that
Step 3）Specific method is：
3-1）Embedding burst pulse S parameter will be gone to be converted into Y parameter, the multinomial on angular frequency is carried out to the real part of Y parameter
Expansion, carries out the polynomial expansion on angular frequency again after the imaginary part of Y parameter and angular frequency are divided by；
3-2）The precision according to needed for model, it is determined that the top step number of the fitting of a polynomial parameter needed, and then determine crystal pipe die
Current source, the top step number of Charge Source needed for type；
3-3）The multinomial coefficient of the Y parameter real part is integrated according to top step number, each rank current source is obtained；It is right
The Y parameter imaginary part and the multinomial coefficient of the business of angular frequency are integrated, and obtain each rank Charge Source.
5. a kind of transistor modeling method based on burst pulse weak-signal measurement according to claim 1, it is characterised in that
Step 4）Specific method be：
Respectively described current source artificial neural network topological structure corresponding with Charge Source structure, and utilize Intelligent Optimization Technique
The current source is trained with electric charge source data respectively；Or using empirical equation model to the current source and Charge Source
It is fitted.
6. a kind of transistor modeling method based on burst pulse weak-signal measurement according to claim 5, it is characterised in that
Empirical equation model for being fitted the current source and Charge Source includes Staz models, Angelov models, Curtice models.
7. a kind of transistor modeling method based on burst pulse weak-signal measurement according to claim 5, it is characterised in that
It is additionally included in the step of adding fuel factor sub-circuit and trap effect sub-circuit in the artificial neural network topological structure.
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Application publication date: 20170922 |