JP2011114213A - Method of generating equivalent circuit model of hetero-junction field effect transistor and circuit simulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of generating an equivalent circuit model of a hetero-junction field effect transistor, the circuit model having parameters provided with a physical meaning, easily fed back for extraction of initial values and for device development, and accurately expressing electric characteristics, and also to provide a circuit simulator therefor. <P>SOLUTION: An equivalent circuit model includes a nonlinear drain current model defined by an equation 1 for expressing a current I<SB>ds</SB>between a drain and a source in a hetero-junction field effect transistor. The method includes a step ST102 of preparing the equivalent circuit model, and a fitting step of using I<SB>max</SB>, V<SB>knee</SB>, g<SB>m</SB>, V<SB>p</SB>, P<SB>2</SB>, P<SB>3</SB>, and T<SB>c</SB>I<SB>max</SB>in parameters of the equivalent circuit model as fitting parameters and determining values thereof by fitting. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for modeling a semiconductor device, and more particularly to a method for creating an equivalent circuit model of a heterojunction field effect transistor (hereinafter referred to as a field effect transistor) and a circuit simulator including the model.

  Heterojunction FETs including HEMTs (High Electron Mobility Transistors) exhibit excellent high frequency characteristics and are used in various RF applications. In order to accurately predict the performance of such a device and to design various semiconductor circuits using such a device, an accurate model of the semiconductor device is required. By using a model, it is possible to extract model parameters and feed back the values to device design / creation and to perform highly accurate circuit simulation in the development of semiconductor devices and semiconductor circuits. This reduces the number of prototypes of semiconductor devices and semiconductor circuits and enables efficient development.

  Two methods are well known as methods for modeling the electrical characteristics of a semiconductor device. One is physical device simulation, and the other is equivalent circuit modeling. Device simulation is a method of calculating electrical characteristics using a device simulator that numerically solves a physical equation called a device simulator, using the physical position, structure, and material characteristics of the device as input parameters. For example, ATLAS (registered trademark) device simulator manufactured by Silvaco has the advantage that the physical structure of the device is directly input, so that the correlation between the calculation result and the input parameter is quite strong, and the calculation result is easily fed back to the device development. However, the ability of device simulators to accurately model the actual measured electrical characteristics is relatively inaccurate.

  Another disadvantage of modeling by device simulation is that it is incompatible with a circuit simulator. Even if the electrical characteristics of the device can be calculated by the device simulator, the circuit simulator and the calculation engine of the device simulator are completely different from each other. Therefore, the calculation model of the device simulator cannot be used by the circuit simulator. That is, even if the electrical characteristics of the semiconductor device can be calculated by the device simulator, an unreasonable fact that the electrical characteristics of the circuit including the semiconductor device cannot be calculated occurs.

Next, equivalent circuit modeling will be described. An equivalent circuit model is a model that calculates the electrical characteristics of a device using a network of electrical elements such as resistors, inductors, capacitors, and current sources. In particular, a model expressing the nonlinearity of a semiconductor device by describing a current source, a resistor, and a capacitor with a nonlinear function of a gate voltage and a drain voltage is called a large signal equivalent circuit model. Each parameter is determined by parameter fitting so that the measurement result matches the calculation result. In the normal large signal equivalent circuit model, the capacitors C _gs , C _gd , current sources I _gs , I _gd , I _ds are made nonlinear, but the current source I _ds is particularly the most important part that affects the model accuracy. It is. As an equivalent circuit model of the FET, the Curtis-Etenberg model is widely used (see, for example, Non-Patent Document 1).

  The calculation formula of the drain current source model used in the Curtis-Etenberg model is shown below.

Where V _gs : Gate-source voltage
V _ds : drain-source voltage
A ₀ , A ₁ , A ₂ , A ₃ : parameters representing changes in Ids with respect to Vgs
γ: a parameter representing the rise of I _ds
β ₂ : Parameter representing pinch-off fluctuation
V _ds0 : Parameter when A ₀ -A ₃ is evaluated

  The above parameters are subjected to parameter fitting with respect to actually measured values such as IV characteristics to determine values. Since the equivalent circuit model determines parameter values based on actual measurement values, the electrical characteristics of the device can be reproduced with relatively high accuracy. In addition, since the equivalent circuit model is composed of a network of electrical elements, the compatibility with the circuit simulator is good, and the electrical characteristics of the semiconductor circuit including the equivalent circuit model can be easily calculated in the circuit simulator.

  However, the equivalent circuit model has a disadvantage that the correlation between its parameters and the physical structure of the device is low. Also in the above model, the model parameter is a fitting parameter and has no physical meaning. Therefore, it is difficult to calculate the electrical characteristics from the physical structure of the device or to estimate the physical quantity from the value of the model parameter, and it is difficult to feed back to the device development even if the parameter value is known. Further, since the parameter does not have a physical meaning, it is difficult to obtain an appropriate initial value at the time of parameter fitting, and depending on the initial value, there is a possibility that the calculation accuracy is deteriorated due to a local minimum value.

“A Nonlinear GaAs FET Model for Use in the Design of Output Circuits for Power Amplifiers”, IEEE Trans. Microwave Theory Tech., Vol. MTT-33, pp. 1383-1394, Dec. 1985.

  The present invention has been made to solve the above-mentioned problems. Heterojunctions in which parameters have physical meanings, initial values can be easily extracted and feedback to device development can be expressed, and electrical characteristics can be accurately expressed. An object of the present invention is to provide a method for creating an equivalent circuit model of a field effect transistor and a circuit simulator, and contribute to the efficient development of semiconductor devices.

ここで、ドレイン電流のゲート電圧依存性を表すψ（Ｖ_ｇｓ）とドレイン電流の温 度依存性を表すＩ_ｍａｘ（Ｔ_ａ）とは次式で表され、

Ｐ_１は次式で定義され、

ただし、Ｉ_ｄｓ：ドレイン・ソース間電流
Ｖ_ｇｓ：ゲート・ソース間電圧
Ｖ_ｄｓ：ドレイン・ソース間電圧
Ｉ_ｍａｘ：最大ドレイン電流
Ｖ_ｋｎｅｅ：ニー電圧
ｇ_ｍ：相互コンダクタンス
Ｖ_ｐ：ピンチオフ電圧
Ｐ_２：キャリア密度の２次変調係数
Ｐ_３：キャリア密度の３次変調係数
Ｒ_ｔｈ：熱抵抗
Ｔ_ａ： 周囲温度
Ｔ_ｃＩ_ｍａｘ：ドレイン電流の温度係数
非線形ドレイン電流モデルを含む等価回路モデルを準備するステップと、
前記等価回路モデル内のパラメータのうち、Ｉ_ｍａｘ、Ｖ_ｋｎｅｅ、ｇ_ｍ、Ｖ_ｐ、Ｐ_２、Ｐ_３、Ｔ_ｃＩ_ｍａｘをフィッティングパラメータとし、フィッティングにより値を定めるフィッティングステップと
を備えるものである。 The method of creating an equivalent circuit model of a heterojunction field effect transistor according to the present invention is a method of creating an equivalent circuit model of a heterojunction field effect transistor,
The current-effect transistor drain-source current I _ds is defined by the following equation:

Here, ψ (V _gs ) representing the gate voltage dependence of the drain current and I _max (T _a ) representing the temperature dependence of the drain current are represented by the following equations:

P ₁ is defined by the following equation:

Where I _ds : drain-source current
V _gs : Gate-source voltage
V _ds : drain-source voltage
I _max : Maximum drain current
_Vknee : knee voltage
g _m : mutual conductance
V _p : pinch-off voltage
P ₂ : secondary modulation coefficient of carrier density
P ₃ : third-order modulation coefficient of carrier density
R _th : Thermal resistance
T _a : ambient temperature
T _c I _max : preparing an equivalent circuit model including a temperature coefficient nonlinear drain current model of the drain current;
Of the parameters in the equivalent circuit model, I _max , V _knee , g _m , V _p , P ₂ , P ₃ , T _c I _max are used as fitting parameters, and a fitting step for determining a value by fitting is provided. .

ここで、ドレイン電流のゲート電圧依存性を表すψ（Ｖ_ｇｓ）とドレイン電流の温 度依存性を表すＩ_ｍａｘ（Ｔ_ａ）とは次式で表され、

Ｐ_１は次式で定義され、

ただし、Ｉ_ｄｓ：ドレイン・ソース間電流
Ｖ_ｇｓ：ゲート・ソース間電圧
Ｖ_ｄｓ：ドレイン・ソース間電圧
Ｉ_ｍａｘ：最大ドレイン電流
Ｖ_ｋｎｅｅ：ニー電圧
ｇ_ｍ：相互コンダクタンス
Ｖ_ｐ：ピンチオフ電圧
Ｐ_２：キャリア密度の２次変調係数
Ｐ_３：キャリア密度の３次変調係数
Ｒ_ｔｈ：熱抵抗
Ｔ_ａ： 周囲温度
Ｔ_ｃＩ_ｍａｘ：ドレイン電流の温度係数
非線形ドレイン電流モデルを含む。 The circuit simulator according to the present invention is a circuit simulator using an equivalent circuit model of a heterojunction field effect transistor, and expresses a current I _ds between the drain and source of the field effect transistor as the equivalent circuit model. Defined by

Here, ψ (V _gs ) representing the gate voltage dependence of the drain current and I _max (T _a ) representing the temperature dependence of the drain current are represented by the following equations:

P ₁ is defined by the following equation:

Where I _ds : drain-source current
V _gs : Gate-source voltage
V _ds : drain-source voltage
I _max : Maximum drain current
_Vknee : knee voltage
g _m : mutual conductance
V _p : pinch-off voltage
P ₂ : secondary modulation coefficient of carrier density
P ₃ : third-order modulation coefficient of carrier density
R _th : Thermal resistance
T _a : ambient temperature
T _c I _max : Contains a temperature coefficient nonlinear drain current model of the drain current.

  According to the present invention, parameters have physical meanings, initial values can be easily extracted and feedback to device development, and electrical characteristics can be expressed with high accuracy.

It is a block diagram of the equivalent circuit model of the heterojunction FET which concerns on embodiment of this invention. It is explanatory drawing which shows the relationship between the physical parameter of FET equivalent circuit model which concerns on embodiment of this invention, and device structure. It is a flowchart which shows the procedure of the method of producing the FET equivalent circuit model which concerns on embodiment of this invention. Parameter _I max of FET equivalent circuit model according to the embodiment of the present _invention, V p, is an explanatory diagram for the initial value extraction _{g m.} It is explanatory drawing for extraction of the initial value of parameter _Vknee of FET equivalent circuit model concerning an embodiment of this invention. It is a figure which shows the comparison of the calculated value and measured value of IV characteristic by the FET equivalent circuit model which concerns on embodiment of this invention. It is a flowchart which shows the procedure of the development method of FET which concerns on embodiment of this invention. It is a flowchart which shows the procedure of the development method of another FET which concerns on embodiment of this invention. It is a flowchart which shows the procedure of the simulation of the circuit containing the equivalent circuit model which concerns on embodiment of this invention.

  Embodiments of the present invention will be described with reference to the drawings. An equivalent circuit model of the heterojunction FET is shown in FIG. In the equivalent circuit model 1 of the heterojunction FET shown in FIG. 1, the nonlinear drain current model 2 is defined by the following equation.

Here, ψ (V _gs ) indicates the gate voltage dependency of the drain current, and I _max (T _a ) indicates the temperature dependency of the drain current. ψ (V _gs ) is defined by the following equation.

Here, P ₁ is expressed by the following equation.

I _max (T _a ) is defined by the following equation.

Each parameter of Formula (6) is defined as follows.
I _ds : drain-source current
V _gs : Gate-source voltage
V _ds : drain-source voltage
I _max : Maximum drain current
_Vknee : knee voltage
g _m : mutual conductance
V _p : pinch-off voltage
P ₂ : secondary modulation coefficient of carrier density
P ₃ : third-order modulation coefficient of carrier density
R _th : Thermal resistance
T _a : ambient temperature
T _c I _max : Temperature coefficient of drain current

Here, since R _th and T _a can be determined in advance from different measurements, and V _gs and V _ds are control voltages for calculating I _ds , model parameters whose values can be changed among these parameters are: There are seven of I _max , V _knee , g _m , V _p , P ₂ , P ₃ , and T _c I _max .

  The equivalent circuit model according to the present invention uses device parameters as model parameters, and the meaning of the model parameters is clear. Thereby, the parameter initial value can be easily obtained from the measurement result. Here, the device parameter is a parameter representing the electrical characteristics of the semiconductor device including the FET, and indicates, for example, a pinch-off voltage or a knee voltage.

  As described above, the equivalent circuit model can easily understand the device characteristics by looking at the model parameters, and can easily apply feedback to the device design.

  Further, the equivalent circuit model device parameter can be related to the physical parameter. Thereby, it is also possible to predict the electrical characteristics directly from the device structure. Hereinafter, the relationship between device parameters and physical parameters will be described. Here, the physical parameter is a parameter representing the physical structure or physical characteristics of the device, and indicates, for example, the gate length or mobility.

  The relational expressions between device parameters and physical parameters are shown below.

Here, the physical meaning of each parameter is as follows. FIG. 2 shows the relationship between the physical parameters and the device structure.
q: Elementary charge
σ: polarization
v _s : electron saturation speed
μ: Electron mobility
L _SG : Gate-source distance
L _GD : Distance between gate and drain
L _G : Gate length
R _c : contact resistance
d: Electron supply layer thickness
ε ₀ : dielectric constant of vacuum
ε _AG : dielectric constant of electron supply layer
φ _b : barrier height
ΔE _c : difference between the electron supply layer thickness and the conduction band energy of the buffer layer

Among these parameters, L _SG , L _GD , L _G , and d are parameters relating to the physical structure of the device and are uniquely determined. Since q is a physical constant, the value is fixed. Since ε ₀ and ε _AG are material constants, they are determined once the material is determined. Therefore, it is σ, v _s , μ, R _c , φ _b , and ΔE _c that do not have accurate values among these parameters. However, these parameters can be known in advance as long as they are orders of magnitude. These parameters can determine effective values of physical parameters by parameter fitting.

  Thus, the equivalent circuit model according to the present invention can use either a device parameter or a physical parameter as a model parameter.

FIG. 3 shows a procedure for creating an equivalent circuit model in the present invention. First, measurement data of the IV characteristics of the FET is prepared (ST101). Next, prepare the equivalent circuit model (ST 102), the model parameter _{I max, V knee, g m} , V p, the initial value of the _{P 2, P 3, T c} I max (ST103). The IV characteristics are calculated using these parameters (ST104), and the error between the measurement result and the calculation result is calculated (ST105). It is determined whether the error satisfies a predetermined allowable condition (ST106). If not, the parameter is changed (ST107), and ST104 to ST106 are repeated. If the error satisfies an allowable condition, a parameter is determined for that value (ST108), and the process ends.

Error _{E rror} is calculated by the following equation for example, in ST105. Note that i represents a measurement point.

Further, in ST _103, the initial value of _{I max, V knee, g m} , V p is 4, as shown in FIG. 5, it can be easily extracted from the measured results. Since the values of P ₂ , P ₃ , and T _c I _max are usually small, the initial values are set to 0. In addition, I _max , V _knee , g _m , and V _p may be set to initial values obtained by substituting physical parameters into the equations (7), (8), (11), and (10). Parameter fitting may be performed using the parameters themselves as model parameters.

  The following table shows the parameter values determined by the procedure shown in FIG.

  FIG. 6 shows a comparison between a calculation result and a measurement result by the equivalent circuit model according to the present invention using these parameter values. The calculation result and the measurement result are in good agreement, and the effectiveness of the equivalent circuit model according to the present invention can be confirmed.

  In this way, by setting the model parameter = device parameter, an appropriate initial value can be extracted from the measured data of the FET, so that the number of repetitive calculations by parameter fitting can be reduced, and the FET equivalent circuit model can be created in a short time. Can be created. In addition, the possibility that the fitting parameter converges to the local optimum solution can be avoided.

  Next, the procedure of the FET development method according to this embodiment will be described. There are roughly two types of development methods using equivalent circuit models. One is a method of making a prototype of an FET by calculating characteristics using a model before creating the FET, designing an optimum device for the target performance, and making an FET. The other method is to actually measure the characteristics after creating the FET, perform parameter fitting on the measured values, and feed back the obtained values to the device design.

  The former method will be described with reference to FIG. First, an equivalent circuit is prepared (ST301), and physical parameters are input to the model from the device structure and material constants (ST302). Next, desired characteristics such as current and mutual conductance are calculated using the model (ST303), and it is determined whether the calculated characteristics satisfy the target performance (ST304). If not satisfied, the physical parameters of the FET are changed (ST305), and the steps of ST302 to ST304 are repeated. If the target performance is satisfied, an FET is created using the physical parameters (ST306), and this procedure ends. The step of ST306 may be to make a prototype after confirming the characteristics with a device simulator based on the obtained physical parameters.

  Next, the latter method will be described with reference to FIG. First, an FET is created based on a certain physical parameter (ST201). Next, the characteristics of the created FET are measured (ST202), and an equivalent circuit model is prepared (ST203). Next, parameter fitting is performed to obtain a parameter value whose calculation result and measurement result are in good agreement (ST204). Then, it is determined whether or not the device design can be changed based on the obtained parameter value (ST205). If it is determined that at least one of the physical parameters should be changed, the physical parameter of the FET is changed (ST206), and steps ST202 to ST205 are repeated. If it is determined that none of the parameters should be changed, the procedure ends.

  Since the equivalent circuit model according to the present invention can use model parameters as physical parameters, it is possible to determine whether or not a device design can be changed without estimating the physical parameters from values obtained by parameter fitting.

  A procedure of a simulation method for a circuit including an FET according to the present embodiment will be described with reference to FIG. First, a circuit to be simulated including an equivalent circuit model is prepared (ST401). Next, parameters of this equivalent circuit model are determined by parameter fitting, and a model is created (ST402). The characteristics of the circuit including the equivalent circuit model are calculated by circuit simulation (ST403), and this procedure ends. Here, the method of creating an equivalent circuit model in ST402 corresponds to the procedure shown in FIG. The parameter may be either a device parameter or a physical parameter.

  By using an equivalent circuit model in which these parameters have physical meaning, it is possible to calculate the variation in the electrical characteristics of the semiconductor circuit with respect to variations in the gate length, pinch-off voltage, etc., and study a semiconductor circuit with good yield. Development and feedback are possible.

  1 Heterojunction FET equivalent circuit model 2 Non-linear drain current model.

Claims (6)

A method of creating an equivalent circuit model of a heterojunction field effect transistor,
The current-effect transistor drain-source current I _ds is defined by the following equation:

Here, ψ (V _gs ) representing the gate voltage dependence of the drain current and I _max (T _a ) representing the temperature dependence of the drain current are represented by the following equations:

P ₁ is defined by the following equation:

Where I _ds : drain-source current
V _gs : Gate-source voltage
V _ds : drain-source voltage
I _max : Maximum drain current
_Vknee : knee voltage
g _m : mutual conductance
V _p : pinch-off voltage
P ₂ : secondary modulation coefficient of carrier density
P ₃ : third-order modulation coefficient of carrier density
R _th : Thermal resistance
T _a : ambient temperature
T _c I _max : preparing an equivalent circuit model including a temperature coefficient nonlinear drain current model of the drain current;
A heterojunction comprising a fitting step in which I _max , V _knee , g _m , V _p , P ₂ , P ₃ , and T _c I _max are fitting parameters among the parameters in the equivalent circuit model, and a value is determined by fitting. A method for creating an equivalent circuit model of a field effect transistor. In the creation method of the equivalent circuit model of the heterojunction field effect transistor according to claim 1,
The fitting step includes
Setting an initial value for each fitting parameter of the equivalent circuit model;
A simulation step for calculating the characteristic value of the field effect transistor by circuit simulation using the set parameters,
Calculating an error between the characteristic value obtained by the circuit simulation and the characteristic value of the measured field effect transistor prepared in advance;
Repeatedly performing the simulation step and the step of calculating the error while changing the value of each fitting parameter until the error satisfies a predetermined condition;
Applying a set of parameter values obtained at the end of the repetitive step to the equivalent circuit model, thereby creating an equivalent circuit of the heterojunction FET. A method for creating an equivalent circuit model of a transistor. In the creation method of the equivalent circuit model of the heterojunction field effect transistor according to claim 1,
The parameters I _max , V _knee , g _m , V _p of the nonlinear drain current model are defined by the following equations:

Where q: elementary charge
σ: polarization
v _s : electron saturation speed
μ: Electron mobility
L _SG : Gate-source distance
L _GD : Distance between gate and drain
L _G : Gate length
R _c : contact resistance
d: Electron supply layer thickness
ε ₀ : dielectric constant of vacuum
ε _AG : dielectric constant of electron supply layer
φ _b : barrier height
ΔE _c : Equivalent circuit model of heterojunction field-effect transistor, characterized in that differences σ, v _s , μ, R _c , φ _b , ΔE _c between electron supply layer thickness and buffer layer conduction band energy are used as fitting parameters How to create In the creation method of the equivalent circuit model of the heterojunction field effect transistor according to claim 2,
The step of setting the initial value is defined in the method for creating an equivalent circuit model of a heterojunction field effect transistor according to claim 3, with respect to parameters I _max , V _knee , g _m , and V _p of the nonlinear drain current model. A method of creating an equivalent circuit model of a heterojunction field effect transistor, characterized in that a value calculated using the formula obtained is used as an initial value. A circuit simulator using an equivalent circuit model of a heterojunction field effect transistor,
As the equivalent circuit model,
The current-effect transistor drain-source current I _ds is defined by the following equation:

Here, ψ (V _gs ) representing the gate voltage dependence of the drain current and I _max (T _a ) representing the temperature dependence of the drain current are represented by the following equations:

P ₁ is defined by the following equation:

Where I _ds : drain-source current
V _gs : Gate-source voltage
V _ds : drain-source voltage
I _max : Maximum drain current
_Vknee : knee voltage
g _m : mutual conductance
V _p : pinch-off voltage
P ₂ : secondary modulation coefficient of carrier density
P ₃ : third-order modulation coefficient of carrier density
R _th : Thermal resistance
T _a : ambient temperature
T _c I _max : A circuit simulator including a temperature coefficient nonlinear drain current model of the drain current. The circuit simulator according to claim 5, wherein
The parameters I _max , V _knee , g _m , and V _p were defined by the following equations:

Where q: elementary charge
σ: polarization
v _s : electron saturation speed
μ: Electron mobility
L _SG : Gate-source distance
L _GD : Distance between gate and drain
L _G : Gate length
R _c : contact resistance
d: Electron supply layer thickness
ε ₀ : dielectric constant of vacuum
ε _AG : dielectric constant of electron supply layer
φ _b : barrier height
ΔE _c : A circuit simulator characterized by including a non-linear drain current model of the difference between the electron supply layer thickness and the conduction band energy of the buffer layer.

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