CN107171779A - Binary code phase-interpolation circuit for CDR - Google Patents

Binary code phase-interpolation circuit for CDR Download PDF

Info

Publication number
CN107171779A
CN107171779A CN201710338567.3A CN201710338567A CN107171779A CN 107171779 A CN107171779 A CN 107171779A CN 201710338567 A CN201710338567 A CN 201710338567A CN 107171779 A CN107171779 A CN 107171779A
Authority
CN
China
Prior art keywords
phase
semiconductor
oxide
metal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710338567.3A
Other languages
Chinese (zh)
Other versions
CN107171779B (en
Inventor
赵玉月
杨煜
沈广振
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Zhongwei Yixin Co Ltd
Original Assignee
Wuxi Zhongwei Yixin Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Zhongwei Yixin Co Ltd filed Critical Wuxi Zhongwei Yixin Co Ltd
Priority to CN201710338567.3A priority Critical patent/CN107171779B/en
Publication of CN107171779A publication Critical patent/CN107171779A/en
Application granted granted Critical
Publication of CN107171779B publication Critical patent/CN107171779B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal

Abstract

The present invention relates to a kind of binary code phase-interpolation circuit for CDR, it includes decoding circuit, and the output end of the decoding circuit is connected with phase option circuit and phase weighting circuit, and the output end of phase option circuit is connected with phase weighting circuit；Decoding circuit receiving phase controlling bus signal, and phase selection signal and phase weighting signal according to needed for phase control bus signal synchronism output, differential clocks of the phase option circuit according to needed for the phase selection signal selection output that decoding circuit is exported, the clock of phase needed for the differential clocks output for phase weighting signal and the phase option circuit output that phase weighting circuit is exported according to decoding circuit.The present invention can effectively solve interpolation weight electric current due to race hazard caused by switching sequence mismatch and switching current burr, can reduce the complexity of circuit, and wide adaptation range is safe and reliable.

Description

Binary code phase-interpolation circuit for CDR
Technical field
The present invention relates to a kind of phase-interpolation circuit, especially a kind of binary code phase-interpolation circuit for CDR, category In the technical field of integrated circuit.
Background technology
In high speed Gb/s serial communication systems, transmitting terminal only sends high-speed data and does not send high-frequency clock, and receiving terminal is received To the high-speed data with shake jitter and uncertain delay delay, extracted according to local clock and the data received Sampling clock information and correct data, i.e. clock and data recovery clock and data recovery：CDR.
Traditional clock and data recovery circuit based on phase interpolation, due to its is simple in construction and can multichannel multiplexing it is excellent Put and be used widely, it is as shown in Figure 1 using ring feedback system CDR.The circuit contains outside low-speed reference clock (REFCLK) 1, frequency discriminator (FD) 3, analog filter (Analog filter) 6, voltage-controlled oscillator (VCO) (VCO) 8, frequency divider (divider) 5, outside high-speed data (DATA) 2, phase discriminator (bang-bang PD) 4, digital filter (digital Filter) 7 and phase interpolator (PI) 9.The output clock of voltage controlled oscillator 8, which is divided after device 5 is divided, is sent to frequency discriminator 3, reflects Clock after outside input low frequency reference clock 1 and frequency dividing is entered line frequency and compared by frequency device 3, and the output of frequency discriminator 3 is filtered by simulation The work of voltage-controlled oscillator (VCO) 8 is controlled after the filtering process of ripple device 6, FLL can accomplish very wide, effectively to suppress internal voltage-controlled The noise of oscillator 8.After Frequency Locking is reached, voltage controlled oscillator 8 sends out multi-phase clock to phase interpolator 9 and in phase Plug in device 9 and produce sampling clock, the phase difference between input data hopping edge and sampling clock compares generation error signal warp through phase discriminator 4 Cross and clock phase interpolation mould device 9 is controlled after digital filter 7 so that sampling clock gradually approaches the optimal sampled point of data, lock Phase ring can accomplish narrow, effectively filter out external noise.The linearity and precision of phase interpolation mould device 9 determine CDR property High speed circuit communication quality and then can be determined.
For in binary code phase interpolation circuit general at present, N binary codes need N number of switch and N number of electric current Source, circuit structure is simple, but switch dynamic behaviour may cause race hazard (mismatch of switch time) and total current signal Meeting superimposed current burr (Capacitance Coupled), the amplitude of burr, which depends on switching caused by input control code, switches number.
For conventional at present based on thermometer-code phase interpolation circuit, N binary code correspondences 2N- 1 thermometer-code, Each thermometer-code controls a unitary current, i.e., 2 by a switchN- 1 switch and 2N- 1 current source, with based on 31 Exemplified by the phase interpolation circuit in thermometer-code control electric current source, thermometer-code control code only has a current source change when switching, Therefore burr is minimum, but circuit complexity is big, has 5 to 31 decoding circuits, 31 control lines cause circuit and layout design Complicate, especially domain matched design is more complicated.
The content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art there is provided a kind of binary code phase for CDR Interpolation circuit, it can effectively solve interpolation weight electric current due to race hazard caused by switching sequence mismatch and switching current hair Thorn, can reduce the complexity of circuit, wide adaptation range is safe and reliable.
The technical scheme provided according to the present invention, it is described including decoding circuit, the output end and phase of the decoding circuit Selection circuit and the connection of phase weighting circuit, the output end of phase option circuit are connected with phase weighting circuit；
Decoding circuit receiving phase controlling bus signal, and the phase according to needed for phase control bus signal synchronism output Selection signal and phase weighting signal, the phase selection signal selection output institute that phase option circuit is exported according to decoding circuit The differential clocks needed, phase weighting signal and the phase option circuit output that phase weighting circuit is exported according to decoding circuit The clock of phase needed for differential clocks output.
The decoding circuit receiving phase control signal is Q [7:When 0], the decoding circuit includes the first d type flip flop, the 2-D trigger, 3d flip-flop, four d flip-flop, the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop, the 8th D are touched Send out device and the 9th d type flip flop；
The D ends of first d type flip flop receive phase control signal Q7, the Q ends output phase selection signal of the first d type flip flop P7；The D ends of second d type flip flop receive phase control signal Q6, the Q ends output phase selection signal P6 of the second d type flip flop；3rd The D ends of d type flip flop are connected with the output end of the first XOR gate, the first XOR gate receiving phase control signal Q6 and phase controlling letter Number Q5, the Q ends output phase selection signal P5 xor P6 of 3d flip-flop；The D ends of four d flip-flop and the second XOR gate Output end is connected, an input receiving phase control signal Q7 of the second XOR gate, another input connection of the second XOR gate With the output end of door, input receiving phase control signal Q6 and phase control signal Q5 with door, the Q ends of four d flip-flop Output phase selection signal (P5＆P6) xor P7；
The D ends of 5th d type flip flop are connected with the output end of the 3rd XOR gate, and the input of the 3rd XOR gate receives phase respectively Position control signal Q4 and phase control signal Q5, Q ends output phase weighted signal P4 the xor P5, the 5th D of the 5th d type flip flop Trigger /Q ends output phase weighted signal P4 xnor P5；
The D ends of 6th d type flip flop are connected with the output end of the 4th XOR gate, and the input of the 4th XOR gate receives phase respectively Position control signal Q3 and phase control signal Q5, Q ends output phase weighted signal P3 the xor P5, the 6th D of the 6th d type flip flop Trigger /Q ends output phase weighted signal P3 xnor P5；
The D ends of 7th d type flip flop are connected with the output end of the 5th XOR gate, and the input of the 5th XOR gate receives phase respectively Position control signal Q2 and phase control signal Q5, Q ends output phase weighted signal P2 the xor P5, the 7th D of the 7th d type flip flop Trigger /Q ends output phase weighted signal P2 xnor P5；
The D ends of 8th d type flip flop are connected with the output end of the 6th XOR gate, and the input of the 6th XOR gate receives phase respectively Position control signal Q1 and phase control signal Q5, Q ends output phase weighted signal P1 the xor P5, the 8th D of the 8th d type flip flop Trigger /Q ends output phase weighted signal P1 xnor P5；
The D ends of 9th d type flip flop are connected with the output end of the 7th XOR gate, and the input of the 7th XOR gate receives phase respectively Position control signal Q0 and phase control signal Q5, Q ends output phase weighted signal P0 the xor P5, the 9th D of the 9th d type flip flop Trigger /Q ends output phase weighted signal P0 xnor P5.
The phase option circuit include first phase selector, second phase selector, third phase selector and 4th phase selector；
First phase selector receives input clock ± sin (ω t+45), ± sin (ω t+135), and first phase simultaneously Selector receives the phase selection signal P6 of the second d type flip flop output, and output end and the second phase of first phase selector are selected Device connection is selected, second phase selector receives the phase selection signal P7 of the first d type flip flop output, and second phase selector is defeated Go out differential clocks ± sin (ω t+ Φ)；
Third phase selector receives input clock ± sin (ω t), ± sin (ω t+90) simultaneously, and third phase is selected Device receives the spacing selection signal P5 xor P6 of 3d flip-flop output, the output end of third phase selector and the 4th phase Selector is connected, and the 4th phase selector receives phase selection signal (P5＆P6) xor P7 of four d flip-flop output, the 4th Phase selector output difference clock ± sin (ω t+ Ψ).
The phase weighting circuit includes metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2, metal-oxide-semiconductor M1 source terminal, metal-oxide-semiconductor M2 source electrode End is connected with power supply VCC, metal-oxide-semiconductor M1 drain electrode end gate terminal respectively with metal-oxide-semiconductor M1, metal-oxide-semiconductor M3 drain electrode end, metal-oxide-semiconductor M5 Drain electrode end connection, gate terminal, metal-oxide-semiconductor M4 drain electrode end and the metal-oxide-semiconductor M6 of metal-oxide-semiconductor M2 drain electrode end respectively with metal-oxide-semiconductor M2 Drain electrode end connection；Metal-oxide-semiconductor M1 drain electrode end output clock signal-sin (ω t+ Θ), metal-oxide-semiconductor M2 drain electrode end output clock Signal+sin (ω t+ Θ)；Metal-oxide-semiconductor M3 gate terminal receives clock signal+sin (ω t+ Φ), metal-oxide-semiconductor M4 grid termination Clock signal-sin (ω t+ Φ) is received, metal-oxide-semiconductor M5 gate terminal receives clock signal+sin (ω t+ Ψ), metal-oxide-semiconductor M6 grid End receives clock signal-sin (ω t+ Ψ)；
Metal-oxide-semiconductor M3 source terminal, metal-oxide-semiconductor M4 source terminal drain electrode end respectively with metal-oxide-semiconductor M7, metal-oxide-semiconductor M9 drain electrode end, Metal-oxide-semiconductor M11 drain electrode end, metal-oxide-semiconductor M13 drain electrode end, metal-oxide-semiconductor M15 drain electrode end connection, metal-oxide-semiconductor M5 source terminal, metal-oxide-semiconductor M6 source terminal drain electrode end respectively with metal-oxide-semiconductor M8, metal-oxide-semiconductor M10 drain electrode end, metal-oxide-semiconductor M12 drain electrode end, metal-oxide-semiconductor M14 Drain electrode end and metal-oxide-semiconductor M16 drain electrode end connection；
Metal-oxide-semiconductor M7 source terminal, metal-oxide-semiconductor M8 source terminal are grounded by current source I1, metal-oxide-semiconductor M9 source terminal, MOS Pipe M10 source terminal is grounded by current source I2, and metal-oxide-semiconductor M11 source terminal, metal-oxide-semiconductor M12 source terminal pass through current source I3 is grounded, and metal-oxide-semiconductor M13 source terminal, metal-oxide-semiconductor M14 source terminal be grounded by current source I4, metal-oxide-semiconductor M15 source terminal with And metal-oxide-semiconductor M16 source terminal is grounded by current source I5；
Metal-oxide-semiconductor M7 gate terminal receives the phase weighting signal P4 xor P5 of the 5th d type flip flop output, metal-oxide-semiconductor M8 grid The extreme phase weighting signal P4 xnor P5 for receiving the output of the 5th d type flip flop；Metal-oxide-semiconductor M9 gate electrode receives the 6th D triggerings Phase weighting signal P3 the xor P5, metal-oxide-semiconductor M10 of device output gate terminal receive the phase weighting letter of the 6th d type flip flop output Number P3 xnor P5, metal-oxide-semiconductor M11 gate terminal receive the phase weighting signal P2 xor P5 of the 7th d type flip flop output, metal-oxide-semiconductor M12 gate terminal receives the phase weighting signal P2 xnor P5 of the 7th d type flip flop output；Metal-oxide-semiconductor M13 gate terminal receives the Phase weighting signal P1 the xor P5, metal-oxide-semiconductor M14 of the output of eight d type flip flops gate terminal receive the phase of the 8th d type flip flop output Position weighted signal P1 xnor P5；Metal-oxide-semiconductor M15 gate terminal receives the phase weighting signal P0 xor of the 9th d type flip flop output P5, metal-oxide-semiconductor M16 gate terminal receive the phase weighting signal P0 xnor P5 of the 9th d type flip flop output.
The size of the current source I1 is 16*Ibias, current source I2 size is 8*Ibias, current source I3 size is 4* Ibias, current source I4 size is 2*Ibias, current source I5 size is Ibias。
Advantages of the present invention：Decoding circuit receiving phase controlling bus signal, and according to phase control signal synchronism output Phase selection signal and phase weighting signal, required electric current can be carried out according to phase selection signal and phase weighting signal Weighting, can cause total weighted current Isum to be gradually decreased to minimum value again after maximum is progressively increased to from minimum, without big Amount switch instant shut-in action, can effectively solve interpolation weight electric current due to race hazard and switch caused by switching sequence mismatch Current spikes, can reduce the complexity of circuit, and wide adaptation range is safe and reliable.
Brief description of the drawings
Fig. 1 is existing CDR structured flowchart.
Fig. 2 is structured flowchart of the invention.
Fig. 3 is decoding circuit schematic diagram of the invention.
Fig. 4 is the schematic diagram of phase option circuit of the present invention.
Fig. 5 is the schematic diagram of phase weighting circuit of the present invention.
Description of reference numerals：Low-speed reference clock, 2- outsides high-speed data, 3- frequency discriminators, 4- phase discriminators, 5- divide outside 1- Frequency device, 6- analog filters, 7- digital filters, 8- voltage controlled oscillators, 9- phase interpolators, 10- decoding circuits, 11- phases Selection circuit, 12- phase weightings circuit, the d type flip flops of 13- first, the d type flip flops of 14- second, the XOR gates of 15- first, the D of 16- the 3rd Trigger, 17- and door, the XOR gates of 18- second, 19- four d flip-flops, the XOR gates of 20- the 3rd, the d type flip flops of 21- the 5th, 22- 4th XOR gate, the d type flip flops of 23- the 6th, the XOR gates of 24- the 5th, the d type flip flops of 25- the 7th, the XOR gates of 26- the 6th, the D of 27- the 8th The XOR gate of trigger, 28- the 7th, the d type flip flops of 29- the 9th, 30- first phase selector, 31- second phase selector, 32- Three phase selectors and the phase selectors of 33- the 4th.
Embodiment
With reference to specific drawings and examples, the invention will be further described.
As shown in Figure 2：In order to be able to effectively solve interpolation weight electric current due to race hazard caused by switching sequence mismatch and Switching current burr, can reduce the complexity of circuit, and the present invention includes decoding circuit 10, the output end of the decoding circuit 10 with Phase option circuit 11 and phase weighting circuit 12 are connected, and output end and the phase weighting circuit 12 of phase option circuit 11 connect Connect；
The receiving phase control signal of decoding circuit 10, and the Selecting phasing letter according to needed for phase control signal synchronism output Number and phase weighting signal, needed for the phase selection signal selection output that phase option circuit 11 is exported according to decoding circuit 10 Differential clocks, the phase weighting signal and phase option circuit 11 that phase weighting circuit 12 is exported according to decoding circuit 10 be defeated The clock of phase needed for the differential clocks output gone out.
Specifically, decoding circuit 10, phase option circuit 11 and the phase for constituting binary code phase-interpolation circuit Position weighting circuit 12 is the phase interpolator 9 in Fig. 1, and decoding circuit 10 is connected with digital filter 7, phase option circuit 11 It is connected, is connected by phase weighting circuit 12 with phase discriminator 4 with voltage controlled oscillator 8.Wherein, digital filter 7 produces phase control Signal processed, and be loaded into decoding circuit 10, corresponding phase selection signal is produced by decoding circuit 10 and phase weighting is believed Number, phase option circuit 11 receives the input clock that voltage controlled oscillator 8 is transmitted, and produces difference under phase selection signal effect Clock.Due to the synchronism output phase selection signal of decoding circuit 10 and phase weighting signal, accordingly, it is capable to effectively remove decoding fortune The delay difference of each control branch current source unlatching/closing caused by calculating, so as to reduce due to being competed caused by sequential logic mismatch Risk and current spikes.
As shown in figure 3, the receiving phase control signal of decoding circuit 10 is Q [7:When 0], the decoding circuit 10 includes first D type flip flop 13, the second d type flip flop 14,3d flip-flop 16, four d flip-flop 19, the 5th d type flip flop 21, the 6th d type flip flop 23rd, the 7th d type flip flop 25, the 8th d type flip flop 27 and the 9th d type flip flop 29；
The D ends of first d type flip flop 13 receive phase control signal Q7, the Q ends output phase selection letter of the first d type flip flop 13 Number P7；The D ends of second d type flip flop 14 receive phase control signal Q6, the Q ends output phase selection signal of the second d type flip flop 14 P6；The D ends of 3d flip-flop 16 are connected with the output end of the first XOR gate 15, the receiving phase control signal of the first XOR gate 15 Q6 and phase control signal Q5, the Q ends output phase selection signal P5 xor P6 of 3d flip-flop 16；Four d flip-flop 19 D ends be connected with the output end of the second XOR gate 18, an input receiving phase control signal Q7 of the second XOR gate 18, second Another input connection of XOR gate 18 is with the output end of door 17, input receiving phase control signal Q6 and phase with door 17 Control signal Q5, Q ends output phase selection signal (P5＆P6) the xor P7 of four d flip-flop 19；
The D ends of 5th d type flip flop 21 are connected with the output end of the 3rd XOR gate 20, the input difference of the 3rd XOR gate 20 Receiving phase control signal Q4 and phase control signal Q5, the Q ends output phase weighted signal P4 xor of the 5th d type flip flop 21 P5, the 5th d type flip flop 21 /Q ends output phase weighted signal P4 xnor P5；
The D ends of 6th d type flip flop 23 are connected with the output end of the 4th XOR gate 22, the input difference of the 4th XOR gate 22 Receiving phase control signal Q3 and spacing control signal Q5, the Q ends output phase weighted signal P3 xor of the 6th d type flip flop 23 P5, the 6th d type flip flop 23 /Q ends output phase weighted signal P3 xnor P5；
The D ends of 7th d type flip flop 25 are connected with the output end of the 5th XOR gate 24, the input difference of the 5th XOR gate 24 Receiving phase control signal Q2 and phase control signal Q5, the Q ends output phase weighted signal P2 xor of the 7th d type flip flop 25 P5, the 7th d type flip flop 25 /Q ends output phase weighted signal P2 xnor P5；
The D ends of 8th d type flip flop 27 are connected with the output end of the 6th XOR gate 26, the input difference of the 6th XOR gate 26 Receiving phase control signal Q1 and phase control signal Q5, the Q ends output phase weighted signal P1 xor of the 8th d type flip flop 27 P5, the 8th d type flip flop 27 /Q ends output phase weighted signal P1 xnor P5；
The D ends of 9th d type flip flop 29 are connected with the output end of the 7th XOR gate 28, the input difference of the 7th XOR gate 28 Receiving phase control signal Q0 and phase control signal Q5, the Q ends output phase weighted signal P0 xor of the 9th d type flip flop 29 P5, the 8th d type flip flop 27 /Q ends output phase weighted signal P0 xnor P5.
In the embodiment of the present invention, phase control signal Q [7:0] produced by digital filter 7, phase control signal Q [7:0] In the case of can guarantee that the linearity, it is to avoid the excessively complexity of circuit, phase control signal integrally uses Q [7:0], separately with Q7~Q0 Represent.Digital filter 7 produces phase control signal Q [7:0] detailed process is known to those skilled in the art, herein not Repeat again.
First d type flip flop 13, the second d type flip flop 14,3d flip-flop 16, four d flip-flop 19, the 5th d type flip flop 21st, the 6th d type flip flop 23, the 7th d type flip flop 25, the 8th d type flip flop 27 and the corresponding clock end of the 9th d type flip flop 29 are adopted Identical clock is used, thus it is synchronous by clock, can the corresponding phase selection signal of synchronism output and phase weighting signal.
In addition, for the 5th d type flip flop 21, the 6th d type flip flop 23, the 7th d type flip flop 25, the 8th d type flip flop 27 and 9th d type flip flop 29, each trigger produces two complementations opposite phase weighted signal in other words simultaneously, to control corresponding MOS The conducting in turn of pipe.
As shown in figure 4, the phase option circuit 11 includes first phase selector 30, second phase selector 31, the Three phase selectors 32 and the 4th phase selector 33；
First phase selector 30 receives input clock ± sin (ω t+45), ± sin (ω t+135), and the first phase simultaneously Digit selector 30 receives the phase selection signal P6 of the second d type flip flop 14 output, the output end of first phase selector 30 and the Two-phase digit selector 31 is connected, the phase selection signal P7 of reception the first d type flip flop 13 output of second phase selector 31, and the Output difference clock ± the sin (ω t+ Φ) of two-phase digit selector 31；
Third phase selector 32 receives input clock ± sin (ω t), ± sin (ω t+90) simultaneously, and third phase is selected Select device 32 receive 3d flip-flop 16 export spacing selection signal P5 xor P6, the output end of third phase selector 32 with 4th phase selector 33 is connected, and the 4th phase selector 33 receives the phase selection signal (P5＆ that four d flip-flop 19 is exported P6) xor P7, the output difference clock ± sin (ω t+ Ψ) of the 4th phase selector 33.
In the embodiment of the present invention, input clock ± sin (ω t), ± sin (ω t+45), ± sin (ω t+90), ± sin (ω t+135) is produced by voltage controlled oscillator 8, first phase selector 30, second phase selector 31, third phase selector 32 And the 4th phase selector 33 use identical structure, input clock+sin (ω t+45), input clock-sin (ω t+45) Load on the 0th group of input of first phase selector 30, input clock+sin (ω t+135), input clock-sin (ω t+ 135) the 1st group of input of first phase selector 30 is loaded on.When phase selection signal P6 is high level, first phase choosing The input clock that device 30 selects and exports the 1st group of input is selected, when phase selection signal P6 is low level, first phase selection Device 30 selects and exports the input clock of the 0th group of input.The same phase selection output end of first phase selector 30 is respectively with the The in-phase end at 31 liang of group selection ends of two-phase digit selector, end of oppisite phase connection, the anti-phase selection output end of first phase selector 30 End of oppisite phase, the in-phase end with 31 liang of group selection ends of second phase selector are connected respectively.The phase of phase selector 32 and the 4th is selected The connection selected between device 33 coordinates, and the connection that specifically may be referred between first phase selector 30 and second phase selector 31 is said It is bright, know specially described in those skilled in the art, here is omitted.
Ψ, Φ are selected phase, specifically：Phase selection signal P6 is 1, the output of first phase selector 30 clock ± Sin (ω t+135), when phase selection signal P6 is 0, the output clock ± sin of first phase selector 30 (ω t+45) works as phase Selection signal P7 is 0, when phase selection signal P6 is 0：+ sin (ω t+ Ф)=- sin (ω t+45) are Ф=- 45, work as phase Selection signal P7 is 0, when phase selection signal P6 is 1：+ sin (ω t+ Ф)=- sin (ω t+135) are that phase is worked as in Ф=- 135 Selection signal P7 is 1, when phase selection signal P6 is 0：+ sin (ω t+ Ф)=- sin (ω t+45) are Ф=45, work as phase Selection signal P7 is 1, and phase selection signal P6 is 1：+ sin (ω t+ Ф)=sin (ω t+135), i.e. Ф=135；Remaining choosing The process of selecting may be referred to described above, and here is omitted.
As shown in figure 5, the phase weighting circuit 12 include metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2, metal-oxide-semiconductor M1 source terminal, Metal-oxide-semiconductor M2 source terminal is connected with power supply VCC, metal-oxide-semiconductor M1 drain electrode end gate terminal respectively with metal-oxide-semiconductor M1, metal-oxide-semiconductor M3 leakage Extremely, metal-oxide-semiconductor M5 drain electrode end connection, metal-oxide-semiconductor M2 drain electrode end gate terminal respectively with metal-oxide-semiconductor M2, metal-oxide-semiconductor M4 drain electrode end And metal-oxide-semiconductor M6 drain electrode end connection；Metal-oxide-semiconductor M1 drain electrode end output clock signal-sin (ω t+ Θ), metal-oxide-semiconductor M2 drain electrode End output clock signal+sin (ω t+ Θ)；Metal-oxide-semiconductor M3 gate terminal receives clock signal+sin (ω t+ Φ), metal-oxide-semiconductor M4's Gate terminal receive clock signal-sin (ω t+ Φ), metal-oxide-semiconductor M5 gate terminal receives clock signal+sin (ω t+ Ψ), MOS Pipe M6 gate terminal receives clock signal-sin (ω t+ Ψ)；
Metal-oxide-semiconductor M3 source terminal, metal-oxide-semiconductor M4 source terminal drain electrode end respectively with metal-oxide-semiconductor M7, metal-oxide-semiconductor M9 drain electrode end, Metal-oxide-semiconductor M11 drain electrode end, metal-oxide-semiconductor M13 drain electrode end, metal-oxide-semiconductor M15 drain electrode end connection, metal-oxide-semiconductor M5 source terminal, metal-oxide-semiconductor M6 source terminal drain electrode end respectively with metal-oxide-semiconductor M8, metal-oxide-semiconductor M10 drain electrode end, metal-oxide-semiconductor M12 drain electrode end, metal-oxide-semiconductor M14 Drain electrode end and metal-oxide-semiconductor M16 drain electrode end connection；
Metal-oxide-semiconductor M7 source terminal, metal-oxide-semiconductor M8 source terminal are grounded by current source I1, metal-oxide-semiconductor M9 source terminal, MOS Pipe M10 source terminal is grounded by current source I2, and metal-oxide-semiconductor M11 source terminal, metal-oxide-semiconductor M12 source terminal pass through current source I3 is grounded, and metal-oxide-semiconductor M13 source terminal, metal-oxide-semiconductor M14 source terminal be grounded by current source I4, metal-oxide-semiconductor M15 source terminal with And metal-oxide-semiconductor M16 source terminal is grounded by current source I5；
Metal-oxide-semiconductor M7 gate terminal receives the phase weighting signal P4 xor P5 of the 5th d type flip flop 21 output, metal-oxide-semiconductor M8's Gate terminal receives the phase weighting signal P4 xnor P5 of the 5th d type flip flop 21 output；Metal-oxide-semiconductor M9 gate electrode receives the 6th D Phase weighting signal P3 xor P5, metal-oxide-semiconductor M10 that trigger 23 is exported gate terminal receive the phase of the 6th d type flip flop 23 output Position weighted signal P3 xnor P5, metal-oxide-semiconductor M11 gate terminal receive the phase weighting signal P2 of the 7th d type flip flop 25 output Xor P5, metal-oxide-semiconductor M12 gate terminal receive the phase weighting signal P2 xnor P5 of the 7th d type flip flop 25 output；Metal-oxide-semiconductor M13 Gate terminal receive the 8th d type flip flop 27 output phase weighting signal P1 xor P5, metal-oxide-semiconductor M14 gate terminal receive the 8th The phase weighting signal P1 xnor P5 that d type flip flop 27 is exported；Metal-oxide-semiconductor M15 gate terminal receives the output of the 9th d type flip flop 29 Phase weighting signal P0 xor P5, metal-oxide-semiconductor M16 gate terminal receive the phase weighting signal P0 of the 9th d type flip flop 29 output xnor P5。
In the embodiment of the present invention, metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2 are PMOS, and metal-oxide-semiconductor M3~M16 uses NMOS tube, described Current source I1 is 16*Ibias, current source I2 is 8*Ibias, current source I3 is 4*Ibias, current source I4 is 2*Ibias, current source I5 For Ibias, IbiasFor unit bias current, current source I1~current source I5 is used as weight electric current.When specifically used, MOS is utilized Pipe M1 drain electrode end, metal-oxide-semiconductor M2 drain electrode end is connected with phase discriminator 4.
In the embodiment of the present invention, phase weighting signal P4 xor P5, phase weighting signal P3 xor P5, phase weighting letter Number P2 xor P5, phase weighting signal P1 xor P5, phase weighting signal P0 xor P5 difference control weights electric current [16：8： 4：2：1]*Ibias, each branch current collects can be represented for weight electric current Isum, Isum with formula (1), difference corresponding with Isum It is 31*I to divide electric currentbias-Isum。
When phase weighting signal P4 xor P5 are logic 1, P4 xnor P5 are logical zero, metal-oxide-semiconductor M7 conductings, metal-oxide-semiconductor M8 Shut-off, represents current source I1 and adds weight electric current Isum, when phase weighting signal P4 xor P5 are logical zero, represents current source I1 is added without weight electric current Isum, but flows to 31*Ibias-Isum.Following explanations are analogized, and are in particular：
When phase weighting signal P3 xor P5 are logic 1, represent current source I2 and add weight electric current Isum；Work as phase When weighted signal P3 xor P5 are logical zero, represent current source I2 and be added without weight electric current Isum.
When phase weighting signal P2 xor P5 are logic 1, represent current source I3 and add weight electric current Isum, work as phase When weighted signal P2 xor P5 are logical zero, represent current source I3 and be added without weight electric current Isum.
When phase weighting signal P1 xor P5 are logic 1, represent current source I4 and add weight electric current Isum, work as phase When weighted signal P1 xor P5 are logical zero, represent current source I4 and be added without weight electric current Isum.
When phase weighting signal P0 xor P5 are logic 1, represent current source I5 and add weight electric current Isum；Work as phase When weighted signal P0 xor P5 are logical zero, represent current source I5 and be added without weight electric current Isum.
Weight electric current Isum controls proportions of the Ф in Θ, weight electric current 31*Ibias- Isum controls ratios of the Ψ in Θ Weight, output phase Θ can use formula (2) approximate representation.
Total weighted current Isum is：
Isum={ P [4: 0] xorP5 } * Ibias (1)
Output phase Θ is represented by
The receiving phase control signal of decoding circuit 10 of the present invention, and believed according to phase control signal synchronism output Selecting phasing Number and phase weighting signal, required electric current weighting can be carried out according to phase selection signal and phase weighting signal, can be made Obtain weighted current Isum always and be gradually decreased to minimum value again after maximum is progressively increased to from minimum, it is instantaneous without largely switching Switch motion, can effectively solve interpolation weight electric current due to race hazard caused by switching sequence mismatch and switching current burr, The complexity of circuit can be reduced, wide adaptation range is safe and reliable.

Claims (5)

1. a kind of binary code phase-interpolation circuit for CDR, it is characterized in that：Including decoding circuit (10), the decoding electricity The output end on road (10) is connected with phase option circuit (11) and phase weighting circuit (12), phase option circuit (11) it is defeated Go out end to be connected with phase weighting circuit (12)；
Decoding circuit (10) receiving phase controlling bus signal, and the phase according to needed for phase control bus signal synchronism output Selection signal and phase weighting signal, the phase selection signal that phase option circuit (11) is exported according to decoding circuit (10) are selected Select the differential clocks needed for output, phase weighting signal and phase that phase weighting circuit (12) is exported according to decoding circuit (10) The clock of phase needed for the differential clocks output of position selection circuit (11) output.
2. the binary code phase-interpolation circuit according to claim 1 for CDR, it is characterized in that：The decoding circuit (10) receiving phase control signal is Q [7:When 0], the decoding circuit (10) includes the first d type flip flop (13), the 2nd D and triggered Device (14), 3d flip-flop (16), four d flip-flop (19), the 5th d type flip flop (21), the 6th d type flip flop (23), the 7th D Trigger (25), the 8th d type flip flop (27) and the 9th d type flip flop (29)；
The D ends of first d type flip flop (13) receive phase control signal Q7, the Q ends output phase selection letter of the first d type flip flop (13) Number P7；The D ends of second d type flip flop (14) receive phase control signal Q6, the Q ends output phase selection of the second d type flip flop (14) Signal P6；The D ends of 3d flip-flop (16) are connected with the output end of the first XOR gate (15), and the first XOR gate (15) receives phase Position control signal Q6 and phase control signal Q5, the Q ends output phase selection signal P5xor P6 of 3d flip-flop (16)；The The D ends of four d flip-flop (19) are connected with the output end of the second XOR gate (18), and an input of the second XOR gate (18) receives phase Position control signal Q7, another input connection of the second XOR gate (18) is with the output end of door (17), the input with door (17) Receiving phase control signal Q6 and phase control signal Q5, the Q ends output phase selection signal (P5＆ of four d flip-flop (19) P6)xor P7；
The D ends of 5th d type flip flop (21) are connected with the output end of the 3rd XOR gate (20), the input point of the 3rd XOR gate (20) Other receiving phase control signal Q4 and phase control signal Q5, the Q ends output phase weighted signal of the 5th d type flip flop (21) P4xor P5, the 5th d type flip flop (21) /Q ends output phase weighted signal P4xnor P5；
The D ends of 6th d type flip flop (23) are connected with the output end of the 4th XOR gate (22), the input point of the 4th XOR gate (22) Other receiving phase control signal Q3 and phase control signal Q5, the Q ends output phase weighted signal of the 6th d type flip flop (23) P3xor P5, the 6th d type flip flop (23) /Q ends output phase weighted signal P3xnor P5；
The D ends of 7th d type flip flop (25) are connected with the output end of the 5th XOR gate (24), the input point of the 5th XOR gate (24) Other receiving phase control signal Q2 and phase control signal Q5, the Q ends output phase weighted signal of the 7th d type flip flop (25) P2xor P5, the 7th d type flip flop (25) /Q ends output phase weighted signal P2xnor P5；
The D ends of 8th d type flip flop (27) are connected with the output end of the 6th XOR gate (26), the input point of the 6th XOR gate (26) Other receiving phase control signal Q1 and phase control signal Q5, the Q ends output phase weighted signal of the 8th d type flip flop (27) P1xor P5, the 8th d type flip flop (27) /Q ends output phase weighted signal P1xnor P5；
The D ends of 9th d type flip flop (29) are connected with the output end of the 7th XOR gate (28), the input point of the 7th XOR gate (28) Other receiving phase control signal Q0 and phase control signal Q5, the Q ends output phase weighted signal of the 9th d type flip flop (29) P0xor P5, the 9th d type flip flop (29) /Q ends output phase weighted signal P0xnor P5.
3. the binary code phase-interpolation circuit according to claim 2 for CDR, it is characterized in that：The Selecting phasing Circuit (11) includes first phase selector (30), second phase selector (31), third phase selector (32) and the 4th Phase selector (33)；
First phase selector (30) is while receive input clock ± sin (ω t+45), ± sin (ω t+135), and first phase Selector (30) receives the phase selection signal P6 of the second d type flip flop (14) output, the output end of first phase selector (30) It is connected with second phase selector (31), second phase selector (31) receives the Selecting phasing of the first d type flip flop (13) output Signal P7, and second phase selector (31) output difference clock ± sin (ω t+ Φ)；
Third phase selector (32) is while receive input clock ± sin (ω t), ± sin (ω t+90), and third phase is selected Device (32) receives the spacing selection signal P5xor P6 of 3d flip-flop (16) output, the output of third phase selector (32) End is connected with the 4th phase selector (33), and the 4th phase selector (33) receives the phase choosing of four d flip-flop (19) output Select signal (P5＆P6) xor P7, the output difference clock ± sin (ω t+ Ψ) of the 4th phase selector 33.
4. the binary code phase-interpolation circuit according to claim 3 for CDR, it is characterized in that：The phase weighting Circuit (12) includes metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2, and metal-oxide-semiconductor M1 source terminal, metal-oxide-semiconductor M2 source terminal are connected with power supply VCC, Metal-oxide-semiconductor M1 drain electrode end gate terminal respectively with metal-oxide-semiconductor M1, metal-oxide-semiconductor M3 drain electrode end, metal-oxide-semiconductor M5 drain electrode end are connected, MOS The drain electrode end of pipe M2 drain electrode end gate terminal respectively with metal-oxide-semiconductor M2, metal-oxide-semiconductor M4 drain electrode end and metal-oxide-semiconductor M6 is connected；MOS Pipe M1 drain electrode end output clock signal-sin (ω t+ Θ), metal-oxide-semiconductor M2 drain electrode end output clock signal+sin (ω t+ Θ)； Metal-oxide-semiconductor M3 gate terminal receives clock signal+sin (ω t+ Φ), and metal-oxide-semiconductor M4 gate terminal receives clock signal-sin (ω t + Φ), metal-oxide-semiconductor M5 gate terminal receives clock signal+sin (ω t+ Ψ), and metal-oxide-semiconductor M6 gate terminal receives clock signal-sin (ωt+Ψ)；
Drain electrode end, metal-oxide-semiconductor M9 drain electrode end, the MOS of metal-oxide-semiconductor M3 source terminal, metal-oxide-semiconductor M4 source terminal respectively with metal-oxide-semiconductor M7 Pipe M11 drain electrode end, metal-oxide-semiconductor M13 drain electrode end, metal-oxide-semiconductor M15 drain electrode end connection, metal-oxide-semiconductor M5 source terminal, metal-oxide-semiconductor M6 Source terminal drain electrode end respectively with metal-oxide-semiconductor M8, metal-oxide-semiconductor M10 drain electrode end, metal-oxide-semiconductor M12 drain electrode end, metal-oxide-semiconductor M14 drain electrode End and metal-oxide-semiconductor M16 drain electrode end connection；
Metal-oxide-semiconductor M7 source terminal, metal-oxide-semiconductor M8 source terminal are grounded by current source I1, metal-oxide-semiconductor M9 source terminal, metal-oxide-semiconductor M10 source terminal is grounded by current source I2, and metal-oxide-semiconductor M11 source terminal, metal-oxide-semiconductor M12 source terminal pass through current source I3 Ground connection, metal-oxide-semiconductor M13 source terminal, metal-oxide-semiconductor M14 source terminal be grounded by current source I4, metal-oxide-semiconductor M15 source terminal and Metal-oxide-semiconductor M16 source terminal is grounded by current source I5；
Metal-oxide-semiconductor M7 gate terminal receives the phase weighting signal P4xor P5 of the 5th d type flip flop (21) output, metal-oxide-semiconductor M8 grid The extreme phase weighting signal P4xnor P5 for receiving the output of the 5th d type flip flop (21)；Metal-oxide-semiconductor M9 gate electrode receives the 6th D and touched The gate terminal for sending out phase weighting signal the P3xor P5, metal-oxide-semiconductor M10 of device (23) output receives the output of the 6th d type flip flop (23) Phase weighting signal P3xnor P5, metal-oxide-semiconductor M11 gate terminal receive the phase weighting signal of the 7th d type flip flop (25) output P2xor P5, metal-oxide-semiconductor M12 gate terminal receive the phase weighting signal P2xnor P5 of the 7th d type flip flop (25) output；Metal-oxide-semiconductor The gate terminal that M13 gate terminal receives phase weighting the signal P1xor P5, metal-oxide-semiconductor M14 of the 8th d type flip flop (27) output is received The phase weighting signal P1xnor P5 of 8th d type flip flop (27) output；Metal-oxide-semiconductor M15 gate terminal receives the 9th d type flip flop (29) phase weighting signal the P0xor P5, metal-oxide-semiconductor M16 of output gate terminal receive the phase of the 9th d type flip flop (29) output Weighted signal P0xnor P5.
5. the binary code phase-interpolation circuit according to claim 3 for CDR, it is characterized in that：The current source I1 Size be 16*Ibias, current source I2 size is 8*Ibias, current source I3 size is 4*Ibias, current source I4 size is 2*Ibias, current source I5 size is Ibias。
CN201710338567.3A 2017-05-12 2017-05-12 Binary code phase interpolation circuit for CDR Active CN107171779B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710338567.3A CN107171779B (en) 2017-05-12 2017-05-12 Binary code phase interpolation circuit for CDR

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710338567.3A CN107171779B (en) 2017-05-12 2017-05-12 Binary code phase interpolation circuit for CDR

Publications (2)

Publication Number Publication Date
CN107171779A true CN107171779A (en) 2017-09-15
CN107171779B CN107171779B (en) 2019-12-20

Family

ID=59816010

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710338567.3A Active CN107171779B (en) 2017-05-12 2017-05-12 Binary code phase interpolation circuit for CDR

Country Status (1)

Country Link
CN (1) CN107171779B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112350695A (en) * 2020-11-23 2021-02-09 海光信息技术股份有限公司 Phase interpolator system, chip and electronic device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7020227B1 (en) * 2002-05-31 2006-03-28 Acard Technology Corporation Method and apparatus for high-speed clock data recovery using low-speed circuits
CN101577617A (en) * 2008-05-08 2009-11-11 台湾积体电路制造股份有限公司 Fast locking clock and data recovery
CN101729234A (en) * 2008-10-20 2010-06-09 台湾积体电路制造股份有限公司 Phase interpolation controller
US20110068836A1 (en) * 2009-09-23 2011-03-24 Gang Wang Spread-spectrum clock acquisition and tracking
CN202713274U (en) * 2012-06-29 2013-01-30 无锡思泰迪半导体有限公司 Structure of high speed clock data recovery system
CN103490775A (en) * 2013-09-03 2014-01-01 电子科技大学 Clock data recovery controller based on dual-loop structure
CN105991112A (en) * 2015-07-06 2016-10-05 龙迅半导体（合肥）股份有限公司 Data clock recovery circuit and phase interpolator thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7020227B1 (en) * 2002-05-31 2006-03-28 Acard Technology Corporation Method and apparatus for high-speed clock data recovery using low-speed circuits
CN101577617A (en) * 2008-05-08 2009-11-11 台湾积体电路制造股份有限公司 Fast locking clock and data recovery
CN101729234A (en) * 2008-10-20 2010-06-09 台湾积体电路制造股份有限公司 Phase interpolation controller
US20110068836A1 (en) * 2009-09-23 2011-03-24 Gang Wang Spread-spectrum clock acquisition and tracking
CN202713274U (en) * 2012-06-29 2013-01-30 无锡思泰迪半导体有限公司 Structure of high speed clock data recovery system
CN103490775A (en) * 2013-09-03 2014-01-01 电子科技大学 Clock data recovery controller based on dual-loop structure
CN105991112A (en) * 2015-07-06 2016-10-05 龙迅半导体（合肥）股份有限公司 Data clock recovery circuit and phase interpolator thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
高宁: "高性能过采样时钟数据恢复电路的研究与设计", 《中国优秀硕士学位论文全文数据库（信息科技辑）》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112350695A (en) * 2020-11-23 2021-02-09 海光信息技术股份有限公司 Phase interpolator system, chip and electronic device
CN112350695B (en) * 2020-11-23 2022-07-01 海光信息技术股份有限公司 Phase interpolator system, chip and electronic device

Also Published As

Publication number Publication date
CN107171779B (en) 2019-12-20

Similar Documents

Publication Publication Date Title
US11804845B2 (en) Multi-modal data-driven clock recovery circuit
US11632114B2 (en) Data-driven phase detector element for phase locked loops
US10686584B2 (en) Quadrature and duty cycle error correction in matrix phase lock loop
US20190363868A1 (en) High performance phase locked loop
US6002279A (en) Clock recovery circuit
US8228126B2 (en) Multi-band burst-mode clock and data recovery circuit
CN102820885B (en) A kind of clock recovery control unit
CN101277178A (en) Jitter-tolerance-enhanced cdr using a gdco-based phase detector
CN103001628B (en) Phase detection and starting circuit used in multiphase clock generating circuit of high-speed serial interface
EP2804322A1 (en) Systems and methods for tracking a received data signal in a clock and data recovery circuit
CN107171779A (en) Binary code phase-interpolation circuit for CDR
CN110212915A (en) A kind of manifold type frequency multiplication delay locked-loop circuit of uniform split-phase output
CN107565956A (en) Applied to the VCO frequency bands switching circuit and its loop switching method in double loop clock data recovery circuit
CN100431268C (en) A phase locked loop (PLL) using unbalanced quadricorrelator
US20020126785A1 (en) Method for recovering a clock signal in a telecommunications system and circuit thereof
CA2296420A1 (en) Voltage controlled oscillator
CN110995248A (en) Method for improving clock frequency coverage
US20140333352A1 (en) Systems and methods for acquiring a received data signal in a clock and data recovery circuit
Xia et al. A 10-GHz low-power serial digital majority voter based on moving accumulative sign filter in a PS-/PI-based CDR
CN115441865A (en) Phase interpolator and phase interpolation method of clock signal
CN108599759B (en) Clock CDR circuit based on embedded clock bit and control device
CN102811052A (en) Phase-locked loop circuit
US11601116B2 (en) System and method for generating sub harmonic locked frequency division and phase interpolation
Lin et al. Phase interpolation technique based on high-speed SERDES chip CDR
Snehalatha et al. Comparative Analysis of Phase Locked Loop with Different Phase Frequency Detectors using 90nm Technology

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant