CN110995248A - Method for improving clock frequency coverage - Google Patents
Method for improving clock frequency coverage Download PDFInfo
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- CN110995248A CN110995248A CN201911322905.XA CN201911322905A CN110995248A CN 110995248 A CN110995248 A CN 110995248A CN 201911322905 A CN201911322905 A CN 201911322905A CN 110995248 A CN110995248 A CN 110995248A
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000006243 chemical reaction Methods 0.000 claims description 16
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
Abstract
The invention provides a method for improving the coverage range of clock frequency, which comprises the following steps: performing signal frequency division processing on an oscillator signal output by an oscillator to form a frequency division signal, wherein the phase number of the frequency division signal is the same as that of a target output signal; and multiplexing the frequency division signal and the oscillator signal to form a target output signal. The method for improving the clock frequency coverage range can realize a larger frequency coverage range by adopting a single oscillator, reduce the area and the power consumption of a chip and reduce the cost of the chip.
Description
Technical Field
The invention relates to the technical field of clocks, in particular to a method for improving the coverage range of clock frequency.
Background
In order to meet various different application environments, the high-speed interface chip requires to continuously improve the output frequency coverage range of a single interface, a wide frequency range can be realized in a low-frequency range by utilizing a high-speed clock to carry out different frequency division ratios, and the wide frequency range is usually covered by utilizing two or more VCOs in a high-frequency range due to the limited tuning range of the VCOs.
In order to realize low phase noise and low power consumption current, a high-frequency VCO usually adopts an LC oscillator as the VCO, but in order to meet the VCO linearity requirement, the tuning range of the LC VCO is small, usually about ± 20%, so in order to improve the clock frequency coverage, two or more VCOs are usually required, and the output is subjected to Multiplexing (MUX), and the implementation method of the VCO is taken as an example below.
In applications such as CDR, adaptive CTLE, etc., the output clock is required to be a quadrature four-phase clock. In order to realize the four-phase clock with the output frequency of f 1-f 3, the QVCO1 with the working frequency covering f 1-f 2 and the QVCO2 with the working frequency covering f 2-f 3 are adopted, and the four-phase clock with the frequency of f 1-f 3 is output by combining with the MUX. Wherein the QVCO1, QVCO2 can realize the output of the quadrature clock through an LC oscillator of anti-phase structure, but not limited thereto.
Disclosure of Invention
The method for improving the coverage range of the clock frequency can improve the coverage range of the clock frequency.
The invention provides a method for improving the coverage range of clock frequency, which comprises the following steps:
performing signal frequency division processing on an oscillator signal output by an oscillator to form a frequency division signal, wherein the phase number of the frequency division signal is the same as that of a target output signal;
and multiplexing the frequency division signal and the oscillator signal to form a target output signal.
Optionally, the signal frequency division processing includes:
carrying out multi-phase conversion processing on the oscillator signals, wherein the number of phases of the signals after multi-phase conversion is twice that of the target output signals;
and carrying out 1.5 frequency division processing on the multiphase converted signals to form frequency division signals.
Optionally, the output signal of the oscillator has two paths of signals, wherein one path of signal is subjected to signal frequency division processing, the other path of signal is an original signal, and the two paths of signals are subjected to multiplexing processing to form an output signal.
Optionally, the signal frequency division processing includes:
the oscillator signals comprise two paths of signals, and the two paths of signals are respectively subjected to multiphase conversion processing so that the two paths of signals form to-be-processed signals with the phase number being twice of the phase number of the target output signals;
and carrying out frequency division processing on the signal to be processed by 1.5 to form a frequency division signal.
Optionally, the signal to be processed and one of the signals are multiplexed.
Optionally, the signal frequency division processing includes:
carrying out multi-phase conversion processing on the oscillator signal to form a signal to be processed with the same phase number as that of the target output signal;
performing frequency division processing on the signal to be processed by 1.5, wherein the phase number of the signal subjected to the frequency division processing by 1.5 is 1/2 of the phase number of the target output signal;
and carrying out low-pass filtering processing and multiphase conversion processing on the signal subjected to the frequency division processing of 1.5 to form a frequency division signal.
Optionally, the signal to be processed and the frequency-divided signal are multiplexed.
Optionally, before the 1.5 frequency division processing, CML level-to-CMOS level processing is further included;
and the signal frequency division processing also comprises the processing of converting the CMOS level into the CML level.
Optionally, the duty ratio of the signal after the frequency division processing of 1.5 is 50%.
Optionally, the signal frequency division processing adopts a double-edge triggered frequency divider or a rising-edge triggered frequency divider.
The method for improving the coverage of the clock frequency adopts a mode of carrying out frequency division processing on the oscillator signal and then carrying out multiplexing selection on the oscillator signal, and can use a single oscillator to cover a larger clock frequency, thereby reducing the occupied area of a chip and reducing the production cost of the chip. Meanwhile, the consumption of power consumption can be reduced due to the fact that the number of oscillators is reduced.
Drawings
FIG. 1 is a flowchart illustrating a method for improving clock frequency coverage to output two-phase clock signals according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for increasing clock frequency coverage to achieve four-phase clock signal output according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for improving clock frequency coverage for four-phase clock signal output according to another embodiment of the present invention;
FIG. 4 is a circuit diagram of a double edge sampling 1.5 frequency division circuit according to an embodiment of the method for improving clock frequency coverage;
FIG. 5 is a circuit diagram of a single edge sampling 1.5 frequency division circuit according to an embodiment of the method for improving clock frequency coverage of the present invention;
FIG. 6 is a circuit diagram of a frequency division circuit with eight-phase double edge sampling 1.5 according to an embodiment of the method for increasing clock frequency coverage;
fig. 7 is a circuit diagram of a frequency division circuit of 1.5 sampling with eight phases and single edge according to an embodiment of the method for improving the coverage of clock frequency.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
The embodiment provides a method for improving a clock frequency coverage range, which comprises the following steps:
performing signal frequency division processing on an oscillator signal output by an oscillator to form a frequency division signal, wherein the phase number of the frequency division signal is the same as that of a target output signal;
and multiplexing the frequency division signal and the oscillator signal to form a target output signal.
Optionally, the signal frequency division processing includes:
carrying out multi-phase conversion processing on the oscillator signals, wherein the number of phases of the signals after multi-phase conversion is twice that of the target output signals;
and carrying out 1.5 frequency division processing on the multiphase converted signals to form frequency division signals.
Optionally, the output signal of the oscillator has two paths of signals, wherein one path of signal is subjected to signal frequency division processing, the other path of signal is an original signal, and the two paths of signals are subjected to multiplexing processing to form an output signal.
Specifically, as shown in fig. 1, a VCO with frequency coverage of f2 to f3 obtains a four-phase quadrature clock through a multi-phase converter, then the clock signal with frequency coverage of f1 to f2(f2/1.5 is not more than f1) can be realized through 1.5 frequency division, and then the clock signal and the clock signal can realize clock output with frequencies of f1 to f3 through a MUX, so that a large amount of current is consumed in realizing DIV1.5 in a CML level range under a part of processes, and a CML-CMOS converter and a CMOS-CML converter can be added, so that the clock signal is subjected to frequency division in the CMOS level range.
As one of the 1.5 divided two-phase clock implementations of the present embodiment; as shown in figure 4 of the accompanying drawings: a circuit for realizing a 1.5 frequency divider by using a double-edge trigger type DFF is characterized in that orthogonal clocks CLKI and CLKQ are input, a 1.5 frequency division signal CLKI _ DIV1.5 with the duty ratio (DCC) of 1/3 is obtained by using the double-edge trigger type DFF and a NOR GATE (NOR GATE) circuit through CLKIP triggering, and a 1.5 frequency division signal CLKI _ DIV1.5 with the DCC of 1/3 is obtained by using CLKQP (or CLKI _ DIV1.5 is adopted by using the CLKQ double edges) and then the two are subjected to OR to obtain the CLK _ DIV1.5 with the DCC of 0.5.
As another implementation of the divided two-phase clock of embodiment 1.5; as shown in figure 5 of the accompanying drawings: in order to realize a circuit of a 1.5 frequency divider by using a rising edge triggered DFF, orthogonal clocks CLKI and CLKQ are input, CLKIP is used for obtaining a three-frequency-divided signal CLKIP _ DIV3 with DCC of 1/3 through DFF and NOR GATE circuits, CLKIN is used for synchronizing CLKIP _ DIV3 to obtain a three-frequency-divided signal CLKIN _ DIV3 with DCC of 1/3, CLKI and CLKIP are used for obtaining or obtaining a three-frequency-divided signal CLKI _ DIV3 with DCC of 0.5, CLKIN is used for synchronizing CLKIP and CLKIP _ DIV3 to obtain CLKQN _ DIV3, CLKIP and CLKI are used for synchronizing and then are obtained or are obtained with CLKI _ DIV3 to obtain a three-frequency-divided signal CLKI _ DIV3 with DCC of 0.5, and the difference between the CLKI and the CLKI _ DIV3 is 0.
In the method for improving the coverage of the clock frequency, a mode of performing frequency division processing on the oscillator signal and then performing multiplexing selection on the oscillator signal is adopted, and a single oscillator can be used for covering a larger clock frequency, so that the occupied area of a chip can be reduced, and the production cost of the chip can be reduced. Meanwhile, the consumption of power consumption can be reduced due to the fact that the number of oscillators is reduced.
Example 2
The embodiment provides a method for improving a clock frequency coverage range, which comprises the following steps:
performing signal frequency division processing on an oscillator signal output by an oscillator to form a frequency division signal, wherein the phase number of the frequency division signal is the same as that of a target output signal;
and multiplexing the frequency division signal and the oscillator signal to form a target output signal.
Optionally, the signal frequency division processing includes:
the oscillator signals comprise two paths of signals, and the two paths of signals are respectively subjected to multiphase conversion processing so that the two paths of signals form to-be-processed signals with the phase number being twice of the phase number of the target output signals;
and carrying out frequency division processing on the signal to be processed by 1.5 to form a frequency division signal.
Optionally, the signal to be processed and one of the signals are multiplexed.
Specifically, as shown in fig. 2: a VCO with frequency coverage of f 2-f 3 is used for realizing four-phase orthogonal clocks CLKIP (0 degree), CLKKQP (-90 degree), CLKIN (-180 degree) and CLKQN (-270 degree) with frequencies of f 2-f 3 through a multi-phase converter 1, meanwhile, another group of four-phase orthogonal clocks CLKKJP (-45 degree), CLKRRP (-135 degree), CLKJN (-225 degree and CLKQN (-315 degree) are realized through a multi-phase converter 2, eight-phase clocks obtain four-phase orthogonal signals with the frequencies of f 1-f 2 through DIV1.5, and then the four-phase orthogonal signals with the frequencies of f 2-f 3 and the eight-phase clocks can realize clock output with the frequencies of f 1-f 3 through MUX.
As a four-phase clock implementation of the present embodiment with frequency division of 1.5, as shown in fig. 6: a circuit of the 1.5 frequency divider is realized by using a double-edge triggering type DFF and a four-select-MUX, eight-phase clocks CLKIP, CLKKP, CLKIN, CLKQN and CLKIP, CLKRP, CLKNN and CLKRN are input, I, Q groups of clocks pass through the MUX, a gray code counter is triggered by double edges, and the counter outputs a selection signal which is used as J, R groups of clocks and corresponds to the MUX; after J, R group clocks are correspondingly utilized to pass through the MUX, the counter is triggered by double edges, and the selection signal corresponding to the MUX is output as the I/Q group clock. The selection time sequence is as follows: and selecting RP on the IP rising edge, selecting QP on the RP rising edge, selecting JN on the QP falling edge, selecting IN on the JN falling edge, selecting RN on the IN rising edge, selecting JP on the QN falling edge on the RN rising edge, and selecting IP on the JP falling edge. The final two MUX outputs are the divided-by-1.5 quadrature clocks CLKIDIV1.5 and CLKQDIV1.5, respectively.
As another implementation of the divided-by-1.5 four-phase clock of this embodiment, since the first implementation of the divided-by-1.5 four-phase clock requires that the delay of the DFF plus the MUX is within 1/8 × f3, which is more demanding on the process rate, this embodiment also provides another implementation with lower demand on the process rate, as shown in fig. 7: the two sets of quadrature clocks are respectively divided by 1.5 to obtain a four-phase quadrature clock circuit, where div1.5 may select any one of the two 1.5-division clock implementations in embodiment 1.
In the method for improving the coverage of the clock frequency, a mode of performing frequency division processing on the oscillator signal and then performing multiplexing selection on the oscillator signal is adopted, and a single oscillator can be used for covering a larger clock frequency, so that the occupied area of a chip can be reduced, and the production cost of the chip can be reduced. Meanwhile, the consumption of power consumption can be reduced due to the fact that the number of oscillators is reduced.
Example 3
The embodiment provides a method for improving a clock frequency coverage range, which comprises the following steps:
performing signal frequency division processing on an oscillator signal output by an oscillator to form a frequency division signal, wherein the phase number of the frequency division signal is the same as that of a target output signal;
and multiplexing the frequency division signal and the oscillator signal to form a target output signal.
Optionally, the signal frequency division processing includes:
carrying out multi-phase conversion processing on the oscillator signal to form a signal to be processed with the same phase number as that of the target output signal;
performing frequency division processing on the signal to be processed by 1.5, wherein the phase number of the signal subjected to the frequency division processing by 1.5 is 1/2 of the phase number of the target output signal;
and carrying out multiphase conversion processing on the signal subjected to the frequency division processing of 1.5 to form a frequency division signal.
Optionally, the signal to be processed and the frequency-divided signal are multiplexed.
Specifically, the implementation manner of outputting the four-phase clock in the present embodiment is shown in fig. 3: a VCO with frequency coverage of f 2-f 3 is used for obtaining a four-phase quadrature clock through a multi-phase converter 1, then 1.5 frequency division is carried out to obtain a two-phase clock signal with frequency coverage of f 1-f 2(f2/1.5 is not more than f1), the two-phase clock signal passes through a multi-phase converter 2 with the working frequency range of f 1-f 2 to obtain a four-phase quadrature clock, and the four-phase quadrature clock signal and the four-phase quadrature signal with the frequency of f 2-f 3 are subjected to MUX to realize clock output with the frequency of f 1-f 3.
Div1.5 in the above example can select any of the two 1.5 divided clock implementations in embodiment 1. In addition, if div1.5 is implemented in CMOS level, an additional LPF is added before the phase converter 2 to filter out the higher harmonics of the clock signal in the CMOS logic, so that the output of the multiphase converter 2 has good linearity.
In the method for improving the coverage of the clock frequency, a mode of performing frequency division processing on the oscillator signal and then performing multiplexing selection on the oscillator signal is adopted, and a single oscillator can be used for covering a larger clock frequency, so that the occupied area of a chip can be reduced, and the production cost of the chip can be reduced. Meanwhile, the consumption of power consumption can be reduced due to the fact that the number of oscillators is reduced.
In the embodiments, the output frequency range of one VCO is the same as that of two VCOs, and due to the reduction of the number of the VCOs, the area and the power consumption of the chip are greatly reduced, and the preparation cost of the chip is also reduced; the above embodiments generate a differential clock with a duty ratio of 50% by a 1.5 frequency division circuit; a differential clock employing a single VCO output 4 phase is also implemented.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for improving clock frequency coverage, comprising: the method comprises the following steps:
performing signal frequency division processing on an oscillator signal output by an oscillator to form a frequency division signal, wherein the phase number of the frequency division signal is the same as that of a target output signal;
and multiplexing the frequency division signal and the oscillator signal to form a target output signal.
2. The method of improving clock frequency coverage of claim 1, wherein: the signal frequency division processing comprises the following steps:
carrying out multi-phase conversion processing on the oscillator signals, wherein the number of phases of the signals after multi-phase conversion is twice that of the target output signals;
and carrying out 1.5 frequency division processing on the multiphase converted signals to form frequency division signals.
3. The method of improving the always-on frequency coverage of claim 2, wherein: the oscillator output signal has two paths of signals, wherein one path of signal is subjected to signal frequency division processing, the other path of signal is an original signal, and the two paths of signals are subjected to multiplexing processing to form an output signal.
4. The method of improving clock frequency coverage of claim 1, wherein: the signal frequency division processing comprises the following steps:
the oscillator signals comprise two paths of signals, and the two paths of signals are respectively subjected to multiphase conversion processing so that the two paths of signals form to-be-processed signals with the phase number being twice of the phase number of the target output signals;
and carrying out frequency division processing on the signal to be processed by 1.5 to form a frequency division signal.
5. The method of improving clock frequency coverage of claim 4, wherein: and multiplexing the signal to be processed and one of the signals.
6. The method of improving clock frequency coverage of claim 1, wherein: the signal frequency division processing comprises the following steps:
carrying out multi-phase conversion processing on the oscillator signal to form a signal to be processed with the same phase number as that of the target output signal;
performing frequency division processing on the signal to be processed by 1.5, wherein the phase number of the signal subjected to the frequency division processing by 1.5 is 1/2 of the phase number of the target output signal;
and carrying out low-pass filtering processing and multiphase conversion processing on the signal subjected to the frequency division processing of 1.5 to form a frequency division signal.
7. The method of improving clock frequency coverage of claim 6, wherein: and multiplexing the signal to be processed and the frequency division signal.
8. A method for improving clock frequency coverage as claimed in any one of claims 2 to 7, wherein: before the 1.5 frequency division processing, CML level conversion to CMOS level processing is also included;
and the signal frequency division processing also comprises the processing of converting the CMOS level into the CML level.
9. A method for improving clock frequency coverage as claimed in any one of claims 2 to 7, wherein: the duty ratio of the signal after the frequency division processing of 1.5 is 50%.
10. The method of improving clock frequency coverage of claim 1, wherein: the signal frequency division processing adopts a double-edge triggered frequency divider or a rising edge triggered frequency divider.
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| CN201911322905.XA CN110995248A (en) | 2019-12-19 | 2019-12-19 | Method for improving clock frequency coverage |
| PCT/CN2020/103278 WO2021120617A1 (en) | 2019-12-19 | 2020-07-21 | Method for improving clock frequency coverage |
| KR1020227019665A KR20220101139A (en) | 2019-12-19 | 2020-07-21 | How to improve clock frequency coverage |
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| CN201911322905.XA CN110995248A (en) | 2019-12-19 | 2019-12-19 | Method for improving clock frequency coverage |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021120617A1 (en) * | 2019-12-19 | 2021-06-24 | 深圳市紫光同创电子有限公司 | Method for improving clock frequency coverage |
| CN116405025A (en) * | 2023-03-30 | 2023-07-07 | 上海物骐微电子有限公司 | Local oscillation signal generating circuit, local oscillation signal generating method and wireless communication system |
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| US10298382B2 (en) * | 2016-06-23 | 2019-05-21 | Omnivision Technologies, Inc. | 1-16 and 1.5-7.5 frequency divider for clock synthesizer in digital systems |
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| CN110011659B (en) * | 2019-04-15 | 2021-01-15 | 上海安路信息科技有限公司 | Frequency divider and chip thereof |
| CN110995248A (en) * | 2019-12-19 | 2020-04-10 | 深圳市紫光同创电子有限公司 | Method for improving clock frequency coverage |
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- 2019-12-19 CN CN201911322905.XA patent/CN110995248A/en active Pending
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2020
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021120617A1 (en) * | 2019-12-19 | 2021-06-24 | 深圳市紫光同创电子有限公司 | Method for improving clock frequency coverage |
| CN116405025A (en) * | 2023-03-30 | 2023-07-07 | 上海物骐微电子有限公司 | Local oscillation signal generating circuit, local oscillation signal generating method and wireless communication system |
| CN116405025B (en) * | 2023-03-30 | 2024-03-29 | 上海物骐微电子有限公司 | Local oscillation signal generating circuit, local oscillation signal generating method and wireless communication system |
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| WO2021120617A1 (en) | 2021-06-24 |
| KR20220101139A (en) | 2022-07-19 |
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