CN108736882B

CN108736882B - Fractional frequency division circuit and radio frequency terminal

Info

Publication number: CN108736882B
Application number: CN201710265613.1A
Authority: CN
Inventors: 黄福青; 赖玠玮
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2017-04-21
Filing date: 2017-04-21
Publication date: 2021-12-14
Anticipated expiration: 2037-04-21
Also published as: CN108736882A

Abstract

A fractional frequency division circuit and a radio frequency terminal, the fractional frequency division circuit includes: the N frequency division circuit is used for realizing N frequency division by taking 4 xM input clock signals with the same frequency and the phases sequentially spaced by 90 DEG/M as input signals to obtain 4 xM frequency division clock signals, the [ (ixN)% (4 xM) +1] input clock signals are input to the (i + 1) th input end of the N frequency division circuit, i is a positive integer and is not less than 0 and not more than 4 xM-1, the frequency division clock signals correspond to the input clock signals one by one, and the 4 xM frequency division clock signals with the same frequency and the phases sequentially spaced by 90 DEG/M; and the logic addition circuit is used for respectively carrying out OR operation on the 4 groups of frequency division clock signals to obtain a group of orthogonal differential clock signals, each group of frequency division clock signals comprises M frequency division clock signals, the phases of the frequency division clock signals are sequentially spaced by 360 degrees/M, M and N are positive integers, and M/N is a fraction less than 2. The scheme of the invention can reduce the cost, area and power consumption of the circuit and optimize the electromagnetic compatibility.

Description

Fractional frequency division circuit and radio frequency terminal

Technical Field

The invention relates to the field of radio frequency circuit design, in particular to a fractional frequency division circuit and a radio frequency terminal.

Background

With the progress of integrated circuit technology, in a radio Frequency terminal, radio Frequency transceiver circuits, Frequency Synthesizer (Frequency Synthesizer) circuits, Digital Signal Processing (DSP) circuits, and the like may be integrated on the same chip, but different circuit modules in the same chip may interfere with each other. For example, on a chip, a Voltage-controlled oscillator (VCO) in a frequency synthesizer is easily pulled by a signal emitted from a radio frequency Power Amplifier (RF Power Amplifier) and its harmonics, which affects the phase noise performance of the frequency synthesizer. In order to reduce interference between different circuit modules, their operating frequencies may be offset from each other. It is often necessary to fractionally divide the operating frequency of the voltage controlled oscillator to generate the local carrier signal to deviate from the operating frequency of the radio frequency power amplifier and its harmonic frequencies.

Fig. 1 is a schematic diagram of a mixing-based fractional frequency division circuit in the prior art. The fractional division circuit 100 shown in fig. 1 may include a divide-by-K divider 101, a mixer 102, and a divide-by-L divider 103. Voltage controlled oscillatorNumber CKvco (frequency F)_VCO) Itself and a divided-K signal CKvco/K obtained by dividing K by the divided-K frequency divider 101 are mixed at the mixer 102 to generate a mixed signal CKmix with a frequency F_mixComprises the following steps:

then, the mixed signal CKmix is divided by L by the divide-by-L frequency divider 103 to obtain IQ quadrature signals I, Q, IB and QB, the phases of which are sequentially spaced by 90 °, and the frequency F of the IQ quadrature signal_outComprises the following steps:

wherein K and L are positive integers; the IQ quadrature signal may be used as a carrier signal in a radio frequency terminal.

However, the fractional frequency division circuit 100 based on the frequency mixing method needs to use an inductor-capacitor resonant network as a load to filter out the stray generated in the frequency mixing process, wherein the inductor has a winding so that the area and the power consumption of the inductor are both large; in addition, the inductor is easily magnetically coupled with other circuit modules to be interfered or to be an Interference source, so that the Electromagnetic Susceptibility (EMS) and the Electromagnetic Interference (EMI) of the fractional frequency divider circuit 100 are strong, that is, the Electromagnetic Compatibility (EMC) is poor. In addition, the above-mentioned fractional frequency division circuit 100 based on the mixing method has a complex scheme and a high cost.

Disclosure of Invention

The invention solves the technical problem of how to reduce the cost, the area and the power consumption of the fractional frequency division circuit and optimize the electromagnetic compatibility of the circuit.

To solve the above technical problem, an embodiment of the present invention provides a fractional frequency division circuit, including: the N frequency division circuit is used for realizing N frequency division by taking 4 xM input clock signals as input signals to obtain 4 xM frequency division clock signals, wherein the 4 xM input clock signals have the same frequency and the phases are sequentially spaced by 90 DEG/M, the [ (ixN)% (4 xM) +1] th input clock signal is input to the (i + 1) th input end of the N frequency division circuit, i is a positive integer and is not less than 0 and not more than 4 xM-1, the frequency division clock signals are in one-to-one correspondence with the input clock signals, and the 4 xM frequency division clock signals have the same frequency and the phases are sequentially spaced by 90 DEG/M; and the logic adding circuit is suitable for respectively carrying out OR operation on the 4 groups of frequency division clock signals to obtain a group of orthogonal differential clock signals, wherein each group of frequency division clock signals comprises M frequency division clock signals, the phases are sequentially spaced by 360 DEG/M, M and N are positive integers, and M/N is a fraction less than 2.

Optionally, the set of quadrature differential clock signals comprises: the phase of the clock signal is sequentially spaced by 90 degrees, namely an in-phase clock signal, a quadrature clock signal, an inverted signal of the in-phase clock signal and an inverted signal of the quadrature clock signal.

Optionally, the divide-by-N circuit includes: the clock end of the (i + 1) th first D flip-flop is connected into the [ (i × N)% (4 × M) +1] th input clock signal in the 4 × M input clock signals, the positive output end of the former first D flip-flop is coupled with the data input end of the latter first D flip-flop, and the positive output ends of the 4 × M first D flip-flops respectively output frequency division clock sub-signals; and the duty ratio adjusting circuit is connected with the 4 xM frequency division clock sub-signals and is suitable for adjusting the duty ratios of the 4 xM frequency division clock sub-signals respectively to obtain the 4 xM frequency division clock signals.

Optionally, the duty cycle adjusting circuit includes: the clock ends and the reset ends of the 4 × M second D flip-flops are coupled to the clock ends of the 4 × M first D flip-flops in a one-to-one correspondence manner, the data input ends of the 4 × M second D flip-flops are coupled to the positive output ends of the 4 × M first D flip-flops in a one-to-one correspondence manner, and the positive output end of each second D flip-flop outputs the frequency-divided clock signal.

Optionally, a holding time of the high level of the frequency-divided clock signal in each period is equal to a holding time of the high level of the input clock signal in each period.

Optionally, the first D flip-flop is falling edge triggered, the second D flip-flop is rising edge triggered, and the second D flip-flop is reset when the input clock signal is at a logic low level.

Optionally, the first D flip-flop is rising edge triggered, the second D flip-flop is falling edge triggered, and the second D flip-flop is reset when the input clock signal is at a logic high level.

Optionally, the logical sum circuit includes: and four OR gates respectively connected into the 4 groups of frequency division clock signals.

Optionally, the fractional division circuit further includes: a phase shift circuit adapted to access and phase shift one of the 4 × M input clock signals to obtain the other of the 4 × M input clock signals.

In order to solve the above technical problem, an embodiment of the present invention further provides a radio frequency terminal, where the radio frequency terminal includes the fractional frequency division circuit.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

the fractional frequency division circuit of the embodiment of the invention can comprise an N frequency division circuit and a logic addition circuit, wherein the N frequency division circuit realizes N frequency division by taking 4 xM input clock signals as input signals to obtain 4 xM frequency division clock signals, the 4 xM input clock signals have the same frequency and have the phases sequentially spaced by 90 degrees/M, the [ (ixN)% (4 xM) +1] input clock signals are input to the i +1 input end of the N frequency division circuit, i is a positive integer and has the phase not less than 0 and not more than 4 xM-1, the frequency division clock signals correspond to the input clock signals one by one, and the 4 xM frequency division clock signals have the phase sequentially spaced by 90 degrees/M; the logical sum circuit is adapted to or 4 groups of the divided clock signals, respectively, to obtain a group of quadrature differential clock signals. Firstly, the scheme of the invention adopts a digital logic mode to realize the N/M frequency division of the input clock signal, and can flexibly configure the fractional frequency division ratio through the configuration of M and N. And compared with the scheme in the prior art, the scheme provided by the invention has the advantages of low cost, small area and good electromagnetic compatibility. And thirdly, the scheme of the invention realizes N/M frequency division only by one N frequency division circuit and one logic addition circuit, and has simple structure and lower power consumption. In addition, the scheme of the invention can also directly generate a group of orthogonal differential clock signals which can be directly used as carrier signals of the radio frequency terminal.

Furthermore, the N-division circuit can comprise 4 xM first D triggers and a duty ratio adjusting circuit which are sequentially connected in series to form a ring, and the circuit is simple in structure and easy to implement.

Drawings

Fig. 1 is a schematic diagram of a mixing-based fractional frequency division circuit in the prior art.

Fig. 2 is a schematic structural diagram of a fractional frequency division circuit according to an embodiment of the present invention.

Fig. 3 is a circuit diagram of a fractional frequency division circuit according to an embodiment of the present invention.

Fig. 4 is a circuit diagram of a fractional division circuit with a division ratio of 3/2 according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of an operation waveform of the fractional division circuit shown in fig. 4.

Detailed Description

As described in the background section, in a fractional frequency division circuit based on a frequency mixing method in the prior art, an inductance-capacitance resonant network is used as a load, so that both the area and the power consumption of the circuit are large, and Electromagnetic Compatibility (EMC) is weak. In addition, the above fractional frequency division circuit scheme based on the mixing mode is complex and has high cost.

The embodiment of the invention provides a fractional frequency division circuit, which is based on digital logic, realizes N frequency division by taking 4 xM input clock signals as input signals to obtain 4 xM frequency division clock signals, and obtains a group of orthogonal differential clock signals based on the 4 xM frequency division clock signals.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 2, a fractional division circuit 200 of an embodiment of the present invention may include a divide-by-N circuit 201 and a logical sum circuit 202.

The N-division circuit 201 divides the input signal by N using 4 × M input clock signals (see CK < [ (0.,. 4 × M-1) × N ]% (4 × M) >, i.e., CK <0>, CK < N% (4 × M) >, CK < (2 × N) > (4 × M) >, CK < (3 × N) > (4 × M) >, CK < (4 × N) > (4 × M) >, CK < (5 × N)% (4 × M) >, … …, and CK < (4 × M × N-N) > (4 × M) >, so as to obtain 4 × M divided clock signals (see Q < [ (0.,. 4 × M-1) × N ]% (4 × M) > (4 × M) > (3 × N) > (4 × M) > (S, Q) > (Q < [ (0) > (3 × M) > (3 × N) > (4 × N) > (3683) >, of the input signal, thereby obtaining 4 × M divided clock signals (see Q < [ (4 × M) > (3 × M) >) Q < (4 × N)% (4 × M) > -S, Q < (5 × N)% (4 × M) > -S, … …, and Q < (4 × M × N-N) > (4 × M) > -S), said M and N being positive integers, and M/N being a fraction less than 2. It should be noted that,% represents a remainder operation, or a modulo operation.

Wherein, the 4 × M input clock signals CK < [ (0.,. 4 × M-1) × N ]% (4 × M) > are of the same frequency and have phases sequentially spaced by 90 °/M, the [ (i × N)% (4 × M) +1] input clock signals are input to the i +1 input terminal of the N-division circuit, i is a positive integer and is greater than or equal to 0 and less than or equal to 4 × M-1, that is, the input clock signals CK <0>, CK < N% (4 × M) >, CK < (2 × N)% (4 × M) >, CK < (3 × N) > (4 × M) >, CK < (4 × N) >, CK < (5 × N) > (4 × M) > (… …, and CK < (4 × M-N) > (4 × M) > (201 are respectively input to the first input terminal, the second input terminal, the fourth input terminal, and the fourth input terminal of the N-division circuit 201, A fifth input terminal, a sixth input terminal … …, and a 4 xm input terminal.

The frequency-divided clock signal Q < [ (0..4 × M-1) × N ]% (4 × M) > < S corresponds to the input clock signal CK < [ (0..4 × M-1) × N ]% (4 × M) > one-to-one, that is, the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, the fifth output terminal, the sixth output terminal … … and the 4 × M output terminal of the N frequency-dividing circuit 201 respectively output the frequency-divided clock signal Q <0> _ S, Q < N% (4 × M) > < S, Q > < (2 × N)% (4 × M) > < S, Q < (3 × N) > (4 × M) > (4 × N) > (4 × M) > < S, … … and Q < (4 × M-N) > (4 × M) > < S, … … and Q < (4 × M × N-N) > (4 × M) > < S, further, the frequency division clock signals arranged according to the sequence have the same frequency and the phases are sequentially spaced by 90 degrees/M.

The 4 × M divided clock signals Q < [ (0..4 × M-1) × N ]% (4 × M) > -S may be divided into 4 groups. The logical sum circuit 202 is adapted to perform an or operation on 4 sets of frequency-divided clock signals, i.e., implement a logical sum, to obtain a set of quadrature differential clock signals (not shown), wherein each set of frequency-divided clock signals includes M frequency-divided clock signals, and phases are sequentially spaced by 360 °/M.

In a specific implementation, the logic summing circuit 202 may preferably include four or gates (see a first or gate G _1, a second or gate G _2, a third or gate G _3, and a fourth or gate G _4 in fig. 3) respectively accessing the 4 groups of frequency-divided clock signals. Optionally, the 1 st component frequency clock signal is Q <0> _ S, Q < (4 × N)% (4 × M) > _ S, >.. and Q < (4 × M × N-4 × N)% (4 × M) > _ S, which is or-operated by the first or gate G _ 1; the 2 nd component frequency clock signal is Q < N% (4 × M) > -S, Q < (5 × N)% (4 × M) > -S, >. and Q < (4 × M × N-3 × N)% (4 × M) > -S, which is or-operated by the second or gate G _ 2; the 3 rd component frequency clock signal is Q < (2 × N)% (4 × M) > -S, Q < (6 × N) > -S, > -and Q < (4 × M × N-2 × N) > (4 × M) > -S, which is OR-ed by a third OR gate G _ 3; the 4 th component frequency clock signal is Q < (3 × N)% (4 × M) > -S, Q < (7 × N) > -S, >. and Q < (4 × M × N-N) > (4 × M) > -S, which are or-operated by the fourth or gate G _ 4.

Those skilled in the art will appreciate that in digital logic design, the or operation on signals can also be implemented by using other combinations of logic devices besides or gates, which are not illustrated here.

In a specific implementation, the set of quadrature differential clock signals may include four signals, which are: the phase of the in-phase clock signal I, the quadrature clock signal Q, the inverted signal IB of the in-phase clock signal, and the inverted signal QB of the quadrature clock signal, which are sequentially spaced by 90 ° in phase, i.e., assuming that the phase of the in-phase clock signal I is 0 °, the phases of the quadrature clock signal Q, the inverted signal IB of the in-phase clock signal, and the inverted signal QB of the quadrature clock signal are 90 °, 180 °, and 270 °, respectively.

The fractional frequency division circuit 200 of the embodiment of the present invention is based on a multi-phase signal, and implements N/M frequency division of the input clock signal CK < [ (0..4 × M-1) × N ]% (4 × M) > in a digital logic manner, and can flexibly configure a fractional frequency division ratio by configuring M and N. Compared with the fractional frequency division circuit based on frequency mixing in the prior art (see fig. 1), the fractional frequency division circuit 200 has the advantages of low circuit cost, small area and good electromagnetic compatibility.

Further, the fractional division circuit 200 realizes the N/M division only by one N division circuit 201 and one logic addition circuit 202, and has a simple structure. In addition, since the operating frequency of the frequency divider circuit is generally equal to the frequency of the input clock signal, in a radio frequency communication system, this is usually the output frequency of a Voltage-controlled oscillator (VCO), which reaches several GHz or even higher, and the power consumption of the frequency divider circuit is significantly increased. However, since the fractional division circuit 200 includes only one N-division circuit 201 and has a simple structure, the power consumption of the fractional division circuit 200 can be reduced.

Further, the fractional division circuit 200 can generate the set of quadrature differential clock signals while achieving the N/M division. Since radio frequency terminals generally perform communication by quadrature modulation and demodulation, a quadrature differential clock signal is generally used as a carrier signal. With the scheme of the embodiment, no additional circuit for generating quadrature differential clock signals needs to be designed.

Fig. 3 is a circuit diagram of a fractional frequency division circuit according to an embodiment of the present invention. Referring to fig. 2 and fig. 3 together, in the fractional division circuit 200, preferably, the divide-by-N circuit 201 may include 4 × M first D flip-flops (see the first D flip-flops D1_0, D1_1, D1_2, D1_3, D1_4, D1_5 … … and D1_4M-1 in the figure) connected in series in a ring, and a duty ratio adjustment circuit 2011, and the circuit structure is simple and easy to implement.

The i +1 th input end of the divide-by-N circuit 201 corresponds to the data input end of the i +1 th first D flip-flop D1 — i. Among the 4 XM first D flip-flops D1_0 to D1_4M-1, a clock terminal of an i +1 th first D flip-flop D1_ i

Switching in the 4 xM input clock signals CK<[(0..4×M-1)×N]％(4×M)>The [ (i.times.N)% (4. times.M) +1 of (b)]An input clock signal CK<(i×N)％(4×M)>The positive output terminal Q of the previous first D flip-flop is coupled to the data input terminal D of the next first D flip-flop, and the positive output terminals of the 4 XM first D flip-flops D1_0 to D1_4M-1 respectively output the frequency-divided clock sub-signals (see Q in the figure)<[(0..4×M-1)×N]％(4×M)>I.e. Q<0>、Q<N％(4×M)>、Q<(2×N)％(4×M)>、Q<(3×N)％(4×M)>、Q<(4×N)％(4×M)>、Q<(5×N)％(4×M)>… … and Q<(4×M×N-N)％(4×M)>). Since the structure and operation principle of the D flip-flop are well known to those skilled in the art, the operation principle of the 4 × M first D flip-flops D1_0 to D1_4M-1 will not be described herein.

In order to ensure the accuracy of the logical sum circuit 202 when performing or operation on the 4 groups of frequency division clock signals, the duty ratio adjustment circuit 2011 is provided. The duty ratio adjusting circuit 2011 is connected to 4 × M frequency division clock sub-signals Q < [ (0..4 × M-1) × N ]% (4 × M) >, and is adapted to adjust the duty ratios of the 4 × M frequency division clock sub-signals, respectively, to obtain the 4 × M frequency division clock signals Q < [ (0..4 × M-1) × N ]% (4 × M) > _ S.

In the present embodiment, the fractional division ratio can be flexibly configured by the configuration of M and N. Specifically, after the values of M and N are determined, the number of input signals of the divide-by-N circuit 201 and the sum of the values are determinedPhase interval between; then configuring the 4 xM input clock signals CK<[(0..4×M-1)×N]％(4×M)>Clock terminals connected to the 4 xM first D flip-flops D1_0 to D1_4M-1

To realize the N-division corresponding to different values N.

For example, when M is 2 and N is 3, the fractional division circuit 200 implements 3/2 division, the number of input signals of the N division circuit 201 is 8, and the phases of the input signals are separated by 45 °; the divide-by-N circuit 201 includes 8 first D flip-flops having clock terminals thereof

Sequentially accessing input clock signal CK<0>、CK<3>、CK<6>、CK<1>、CK<4>、CK<7>、CK<2>And CK<5>And 4 groups of component frequency clock signals are respectively as follows: CK (CK)<0>And CK<4>，CK<3>And CK<7>，CK<6>And CK<2>，CK<1>And CK<5>。

For another example, when M is 3 and N is 5, the fractional division circuit 200 implements 5/3 division, the number of input signals of the N division circuit 201 is 12, and the phase intervals between the input signals are 30 °; the divide-by-N circuit 201 includes 12 first D flip-flops having clock terminals thereof

Sequentially accessing input clock signal CK<0>、CK<5>、CK<10>、CK<3>、CK<8>、CK<1>、CK<6>、CK<11>、CK<4>、CK<9>、CK<2>And CK<7>And 4 groups of component frequency clock signals are respectively as follows: CK (CK)<0>、CK<8>And CK<4>；CK<5>、CK<1>And CK<9>；CK<10>、CK<6>And CK<2>；CK<3>、CK<11>And CK<7>。

For another example, when M is 6, N is 5, and the fractional division circuit 200 implements 5/6 frequency division, the number of input signals of the N-division circuit 201 is 24, and the phase intervals between the input signals are equal to15 degrees; the divide-by-N circuit 201 includes 24 first D flip-flops having clock terminals thereof

Sequentially accessing input clock signal CK<0>、CK<5>、CK<10>、CK<15>、CK<20>、CK<2>、CK<7>、CK<12>、CK<17>、CK<22>、CK<4>、CK<9>、CK<14>、CK<19>、CK<1>、CK<6>、CK<11>、CK<16>、CK<21>、CK<3>、CK<8>、CK<13>、CK<18>And CK<23>And 4 groups of component frequency clock signals are respectively as follows: CK (CK)<0>、CK<20>、CK<17>、CK<14>、CK<11>And CK<8>；CK<5>、CK<2>、CK<22>、CK<19>、CK<16>And CK<13>；CK<10>、CK<7>、CK<4>、CK<1>、CK<21>And CK<18>；CK<15>、CK<12>、CK<9>、CK<6>、CK<3>And CK<23>。

In a specific implementation, the duty ratio adjustment circuit 2011 may include 4 × M second D flip-flops (see the second D flip-flops D2_0, D2_1, D2_2, D2_3, D2_4, D2_5 … … and D2_4M-1 in the figure), the clock terminals clk and reset terminals rst of the 4 × M second D flip-flops D2_0 to D2_4M-1 and the clock terminals rst of the 4 × M first D flip-flops D1_0 to D1_4M-1

The data input terminals D of the 4 xm second D flip-flops D2_0 to D2_4M-1 are coupled to the positive output terminals D of the 4 xm first D flip-flops D1_0 to D1_4M-1 in a one-to-one correspondence, and the positive output terminal Q of each of the second D flip-flops outputs the frequency-divided clock signal.

The high-level maintaining time of the frequency-divided clock signal Q < [ (0..4 xM-1) × N ]% (4 xM) > -S in each period is equal to the high-level maintaining time of the input clock signal CK < [ (0..4 xM-1) × N ]% (4 xM) > in each period.

In a specific implementation, the first D flip-flops D1_0 to D1_4M-1 are triggered by a falling edge, the second D flip-flops D2_0 to D2_4M-1 are triggered by a rising edge, and the second D flip-flops D2_0 to D2_4M-1 are reset when the input clock signal CK < [ (0..4 × M-1) × N ]% (4 × M) > is logic low.

Alternatively, in a specific implementation, the first D flip-flops D1_0 to D1_4M-1 are triggered by rising edges, the second D flip-flops D2_0 to D2_4M-1 are triggered by falling edges, and the second D flip-flops D2_0 to D2_4M-1 are reset when the input clock signal CK < [ (0..4 × M-1) × N ]% (4 × M) > is at a logic high level.

Those skilled in the art will appreciate that a D flip-flop is rising or falling edge triggered, meaning that the positive output of the D flip-flop is at the same logic level as its data input on either a rising or falling edge. In addition, the positive output of the D flip-flop outputs a default logic level, typically a logic low level, when it is reset.

In a specific implementation, the fractional frequency division circuit 200 according to an embodiment of the present invention may further include: a phase shift circuit (not shown) adapted to receive and phase shift one (for example, but not limited to, CK <0 >) of the 4 xM input clock signals CK < [ (0..4 xM-1) × N ]% (4 xM) > to obtain other input clock signals of the 4 xM input clock signals CK < [ (0..4 xM-1) × N ]% (4 xM) > such that the phases of the 4 xM input clock signals CK < [ (0..4 xM-1) × N ]% (4 xM) > are sequentially spaced by 90 °/M.

The following describes details of the scheme of the embodiment of the present invention with reference to the frequency division ratio of 3/2 as an example.

The fractional division circuit 300 shown in fig. 4, which realizes a frequency division ratio of 3/2 (M-2, N-3), may include an N-division circuit 301 and a logical sum circuit 302. The divide-by-N circuit 302 includes 8 first D flip-flops D1_0 to D1_7 and 8 second D flip-flops D2_0 to D2_ 7. The number of input signals of the divide-by-N circuit 301 is 8 and the phase intervals between them are 45 °. Setting the first D flip-flops D1_ 0-D1 _7 to be falling edge triggered, the second D flip-flops D2_ 0-D2 _7 to be rising edge triggered, the second D flip-flops D2_ 0-D2 _7 to be reset when the input clock signal CK <0..7> is a logic low level.

Clock terminals of the first D flip-flops D1_0 to D1_7

The clock terminal clk and the reset terminal rst of the second D flip-flops D2_0 to D2_7 are sequentially connected to an input clock signal CK<0>、CK<3>、CK<6>、CK<1>、CK<4>、CK<7>、CK<2>And CK<5>And 4 groups of component frequency clock signals are respectively as follows: CK (CK)<0>And CK<4>，CK<3>And CK<7>，CK<6>And CK<2>，CK<1>And CK<5>They are ored by a first or gate G _1, a second or gate G _2, a third or gate G _3 and a fourth or gate G _4, respectively, to obtain a set of quadrature differential clock signals.

Fig. 5 is a schematic diagram of an operation waveform of the fractional division circuit 300. In fig. 5, the time length between each two dotted lines corresponds to a phase difference of 45 °, i.e. the sequential phase intervals of the input clock signal CK <0..7 >. Referring to fig. 4 and 5 together, a logic low level is represented by "0" and a logic high level is represented by "1". When the falling edge 1 of the first D flip-flop D1_1 comes, since the divided clock sub-signal Q <0> is "1", the divided clock sub-signal Q <3> changes from "0" to "1", when the falling edge 2 comes, the divided clock sub-signal Q <3> changes from "1" to "0", when the falling edge 3 comes, the divided clock sub-signal Q <3> maintains "0", when the falling edge 4 comes, the divided clock sub-signal Q <3> changes from "0" to "1", and the reasoning on other divided clock signals is similar to this, and will not be described again. The frequency of the frequency-division clock sub-signal Q <0..7> is 3 times of the frequency of the input clock signal CK <0..7>, and the phases of the frequency-division clock sub-signal Q <0..7> are sequentially spaced by 135 degrees.

The principle of adjusting the duty ratio of the divided clock sub-signal Q <0..7> will be described by taking the input clock signal CK <0> and the divided clock sub-signal Q <0> as an example. At the arrival of the rising edge 5, the divided clock sub-signal Q <0> is "1", and therefore, the divided clock signal Q <0> _ S changes from "0" to "1", at the arrival of the falling edge 6, the second D flip-flop D2_0 is reset, and the divided clock signal Q <0> _ S changes from "1" to "0", at the arrival of the rising edges 7 and 9, respectively, the divided clock signal Q <0> _ S is maintained at "0" because the divided clock sub-signal Q <0> is "0", and at the arrival of the falling edges 8 and 10, the second D flip-flop D2_0 is reset, and the divided clock signal Q <0> _ S is maintained at "0", and at the arrival of the rising edge 11, the divided clock signal Q <0> is "1", and therefore, the divided clock signal Q <0> _ S changes from "0" to "1", and repeats. Therefore, the high-level sustain time TQSH of the divided clock signal Q <0> _ S in each period is equal to the high-level sustain time TinH of the input clock signal CK <0> in each period to indirectly reduce the duty ratio of the divided clock sub-signal Q <0 >. The duty cycle procedure for the divided clock sub-signal Q <1..7> is similar to the above procedure, and is not described herein again.

Then, four or gates perform or operation on the 4 groups of frequency division clock signals to obtain an in-phase clock signal I, a quadrature clock signal Q, an inverted signal IB of the in-phase clock signal, and an inverted signal QB of the quadrature clock signal.

It should be noted that, although the duty ratio of the input clock signal CK <0..7> shown in fig. 5 is preferably 50%, in the embodiment of the present invention, the duty ratio of the input clock signal is not particularly limited.

It should be noted that "logic high level" and "logic low level" in this document are relative logic levels. Here, the "logic high level" refers to a level range that can be recognized as a digital signal "1", and the "logic low level" refers to a level range that can be recognized as a digital signal "0", and the specific level range thereof is not particularly limited.

The embodiment of the invention also discloses a radio frequency terminal which can comprise the fractional

frequency division circuit

200 or 300 shown in fig. 2, fig. 3 and fig. 4. In particular implementations, the rf terminal may include, but is not limited to, a computer, a mobile phone, a tablet computer, and the like.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A fractional division circuit, comprising:

the N frequency division circuit is used for realizing N frequency division by taking 4 xM input clock signals as input signals to obtain 4 xM frequency division clock signals, wherein the 4 xM input clock signals have the same frequency and the phases are sequentially spaced by 90 DEG/M, the [ (ixN)% (4 xM) +1] th input clock signal is input to the (i + 1) th input end of the N frequency division circuit, i is a positive integer and is not less than 0 and not more than 4 xM-1, the frequency division clock signals are in one-to-one correspondence with the input clock signals, and the 4 xM frequency division clock signals have the same frequency and the phases are sequentially spaced by 90 DEG/M;

and the logic adding circuit is suitable for respectively carrying out OR operation on the 4 groups of frequency division clock signals to obtain a group of orthogonal differential clock signals, wherein each group of frequency division clock signals comprises M frequency division clock signals, the phases are sequentially spaced by 360 DEG/M, M and N are positive integers, and M/N is a fraction less than 2.

2. The fractional division circuit of claim 1, wherein the set of quadrature differential clock signals comprises: the phase of the clock signal is sequentially spaced by 90 degrees, namely an in-phase clock signal, a quadrature clock signal, an inverted signal of the in-phase clock signal and an inverted signal of the quadrature clock signal.

3. The fractional division circuit of claim 1, wherein the divide-by-N circuit comprises:

the clock end of the (i + 1) th first D flip-flop is connected into the [ (i × N)% (4 × M) +1] th input clock signal in the 4 × M input clock signals, the positive output end of the former first D flip-flop is coupled with the data input end of the latter first D flip-flop, and the positive output ends of the 4 × M first D flip-flops respectively output frequency division clock sub-signals;

and the duty ratio adjusting circuit is connected with the 4 xM frequency division clock sub-signals and is suitable for adjusting the duty ratios of the 4 xM frequency division clock sub-signals respectively to obtain the 4 xM frequency division clock signals.

4. The fractional division circuit of claim 3, wherein the duty cycle adjustment circuit comprises:

the clock ends and the reset ends of the 4 × M second D flip-flops are coupled to the clock ends of the 4 × M first D flip-flops in a one-to-one correspondence manner, the data input ends of the 4 × M second D flip-flops are coupled to the positive output ends of the 4 × M first D flip-flops in a one-to-one correspondence manner, and the positive output end of each second D flip-flop outputs the frequency-divided clock signal.

5. The fractional division circuit of claim 4, wherein the hold time of the high level of the divided clock signal in each cycle is equal to the hold time of the high level of the input clock signal in each cycle.

6. The fractional division circuit of claim 4, wherein the first D flip-flop is falling edge triggered, wherein the second D flip-flop is rising edge triggered, and wherein the second D flip-flop is reset when the input clock signal is a logic low level.

7. The fractional division circuit of claim 4, wherein the first D flip-flop is rising edge triggered, wherein the second D flip-flop is falling edge triggered, and wherein the second D flip-flop is reset when the input clock signal is at a logic high level.

8. The fractional division circuit of claim 1, wherein the logical addition circuit comprises: and four OR gates respectively connected into the 4 groups of frequency division clock signals.

9. The fractional division circuit of any of claims 1-8, further comprising: a phase shift circuit adapted to access and phase shift one of the 4 × M input clock signals to obtain the other of the 4 × M input clock signals.

10. A radio frequency terminal comprising the fractional division circuit of any of claims 1 to 9.