CN107169404A - Distributed mode processor containing three-dimensional memory array - Google Patents

Distributed mode processor containing three-dimensional memory array Download PDF

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Publication number
CN107169404A
CN107169404A CN201710130887.XA CN201710130887A CN107169404A CN 107169404 A CN107169404 A CN 107169404A CN 201710130887 A CN201710130887 A CN 201710130887A CN 107169404 A CN107169404 A CN 107169404A
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mode
processor
arrays
storage
processing circuit
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CN201710130887.XA
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CN107169404B (en
Inventor
张国飙
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Hangzhou Haicun Information Technology Co Ltd
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Hangzhou Haicun Information Technology Co Ltd
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Priority to CN201710460363.7A priority Critical patent/CN107357828A/en
Priority to CN202010416492.8A priority patent/CN111384052B/en
Application filed by Hangzhou Haicun Information Technology Co Ltd filed Critical Hangzhou Haicun Information Technology Co Ltd
Priority to CN202010416480.5A priority patent/CN111446247B/en
Priority to CN201710460362.2A priority patent/CN107393537A/en
Priority to CN202010416491.3A priority patent/CN111446250A/en
Priority to US15/452,728 priority patent/US20170255834A1/en
Priority to CN201710461215.7A priority patent/CN107392017A/en
Priority to CN202010416475.4A priority patent/CN111446246B/en
Priority to CN201710460367.5A priority patent/CN107316014B/en
Priority to CN202010416473.5A priority patent/CN111463203A/en
Priority to CN201710459978.8A priority patent/CN107317803A/en
Priority to CN202010416482.4A priority patent/CN111384051B/en
Priority to CN201710459997.0A priority patent/CN107358100A/en
Priority to CN201710460366.0A priority patent/CN107358254A/en
Priority to CN202010486964.7A priority patent/CN111627909A/en
Priority to CN202010416474.XA priority patent/CN111384050A/en
Priority to CN202010416486.2A priority patent/CN111446248B/en
Priority to CN202010416487.7A priority patent/CN111446249A/en
Priority to CN201710461236.9A priority patent/CN107301222B/en
Publication of CN107169404A publication Critical patent/CN107169404A/en
Priority to US15/729,643 priority patent/US10489590B2/en
Priority to US15/729,640 priority patent/US10560475B2/en
Priority to US15/784,074 priority patent/US20180189586A1/en
Priority to US15/784,065 priority patent/US20180189585A1/en
Priority to US15/973,526 priority patent/US20180260344A1/en
Priority to US15/974,659 priority patent/US20180261226A1/en
Priority to US15/974,655 priority patent/US20180260477A1/en
Priority to US15/974,656 priority patent/US20180260449A1/en
Priority to US15/975,748 priority patent/US20180260644A1/en
Priority to US15/984,358 priority patent/US20180268235A1/en
Priority to US15/989,059 priority patent/US20180270255A1/en
Priority to US15/988,030 priority patent/US20180268900A1/en
Priority to US16/046,956 priority patent/US20180330087A1/en
Priority to US16/248,914 priority patent/US20190158510A1/en
Priority to US16/258,667 priority patent/US20190220680A1/en
Priority to US16/258,666 priority patent/US20190171815A1/en
Priority to US16/371,075 priority patent/US20190230096A1/en
Priority to US16/435,494 priority patent/US20190327247A1/en
Priority to US16/543,554 priority patent/US20190370465A1/en
Priority to US16/594,070 priority patent/US20200036733A1/en
Priority to US16/595,462 priority patent/US20200050565A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention proposes a kind of containing three-dimensional storage（3D‑M）The distributed mode processor of array.It contains multiple storage processing units, 3D M array of each unit containing a mode processing circuit and an at least one storage at least pattern.The 3D M arrays are stacked on above mode processing circuit.By using extensive parallel computing, distributed mode processor can realize that quick mode is handled to large-scale pattern base.

Description

Distributed mode processor containing three-dimensional memory array
Technical field
The present invention relates to integrated circuit fields, more precisely, being related to distributed mode processor.
Background technology
Pattern match and pattern-recognition refer in target pattern（The pattern being retrieved, target pattern）Middle lookup and inspection Rope pattern（For the pattern of retrieval, search pattern）Identical or close pattern.Wherein, pattern match requirement is found Identical pattern, pattern-recognition, which is required nothing more than, finds close pattern.Except special instruction, this specification does not differentiate between pattern match And pattern-recognition, and it is referred to as with mode treatment the various operations carried out to pattern.
Mode treatment（Including pattern match and pattern-recognition）It is widely used.Conventional mode treatment includes character string Match somebody with somebody, code matches, speech recognition and image recognition etc..String matching is widely used in big data analysis（Such as finance data analysis, Electric quotient data analysis, bioinformatics）Deng field：From big data（It is generally at present text database, contains target string）In Searching character string is searched, and carries out statistical analysis.Code matches are widely used in anti-Malware（Anti-malware, such as network Safety, computer antivirus）Deng field：Virus identifications are searched from network packet（virus signature）Or check network Whether packet meets the network standard（network rules）, so as to determine whether network packet is safe.Speech recognition will be logical Cross speech transducer and collect or be stored in voice signal in audio file storehouse and acoustic model repository and language model storehouse Match somebody with somebody.Image recognition will be collected or stored to the picture signal in image file storehouse and iconic model storehouse by imaging sensor Matching.
With the arrival in big data epoch, traditional pattern base（Including search modes storehouse and target pattern storehouse）Turn into big Type database（TB grades to PB grades, or even EB grades）：Search modes storehouse（Including all patterns for being used to retrieve）Data volume It is very big, and target pattern storehouse（Including all patterns being retrieved, usually customer data base）Data volume it is then more huge.Mesh The von Neumann frameworks that preceding computer is used can not meet requirement of the big data epoch to mode treatment.In von In Neumann frameworks, the processor for tupe and the memory for memory module are separation：Memory（As firmly Disk, CD, tape etc.）Memory module data are used only as, and any mode treatment can not be carried out to it；All mode treatments are all By external processor（Such as CPU, GPU）To complete.It is well known that bandwidth is limited between the processor and memory of separation, just All data are read in slave pattern storehouse and are accomplished by time a couple of days, Treatment Analysis still more is carried out to them.Therefore, to large-scale pattern The mode treatment in storehouse needs to expend for a long time.
The content of the invention
The main object of the present invention is to realize that quick mode is handled to large-scale pattern base.
Memory module data it can largely can be carried out again at quick mode it is a further object of the present invention to provide one kind The memory of reason, and the cost of memory is not expensive.
In order to realize these and other purpose, the present invention proposes a kind of containing three-dimensional storage（three-dimensional Memory, referred to as 3D-M）The distributed mode processor of array：It can not only memory module data, moreover it is possible to implement mould to it Formula processing.One schema processor chip contains multiple storage processing units, each unit containing a mode processing circuit and An at least one storage at least pattern（Including target pattern and search modes）3D-M arrays.3D-M arrays and mode processing circuit Vertical collection bring many advantages：Because 3D-M arrays do not account for Substrate Area, it can be integrated on mode processing circuit, this Memory capacity can be increased, chip area is reduced.Importantly, because 3D-M arrays and mode processing circuit are in same chip In and can realize a big bandwidth electrical connection apart from close, between them.By using extensive parallel computing（Each distribution mould Formula processor chips can contain up to ten thousand storage processing units）, distributed mode processor can be realized fast to large-scale pattern base Fast mode processing.
Correspondingly, the present invention proposes a kind of distributed mode processor (200), it is characterised in that contain：One transmission first The input bus (110) of pattern；Semi-conductive substrate (0) and multiple storage processing units (100aa-100mn), it is the multiple to deposit Storage processing unit is coupled with the input bus (110), and each storage processing unit (100ij) contains at least one three-dimensional storage (3D-M) array (170) and a mode processing circuit (180), wherein：The 3D-M arrays (170) are stacked on the substrate (0) Side, the 3D-M arrays (170) storage at least second mode；The mode processing circuit (180) is located in the substrate (0), should Mode processing circuit (180) carries out pattern-recognition or pattern match to the first mode and the second mode；The 3D-M arrays And the mode processing circuit (180) realizes that a big bandwidth is electrically connected by multiple contact access openings (1av, 3av) (170) (160)。
Brief description of the drawings
Fig. 1 is a kind of circuit block diagram of distributed mode processor.
Fig. 2A-Fig. 2 C are the circuit block diagrams of three kinds of storage processing units；
Fig. 3 A are a kind of three-dimensional writable memories（Three-dimensional writable memory, referred to as 3D-W）And The sectional view of storage processing unit based on 3D-W；Fig. 3 B are that a kind of three-dimensional print records reservoir（three-dimensional Printed memory, referred to as 3D-P）And the sectional view of the storage processing unit based on 3D-P.
Fig. 4 is a kind of perspective view of storage processing unit.
Fig. 5 A- Fig. 5 C are the substrate circuitry layouts of three kinds of storage processing units.
It is noted that these accompanying drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and be convenient, in figure Portion size and structure may be zoomed in or out.In different embodiments, the letter suffix behind numeral represents same class The different instances of structure；Identical number prefix represents same or similar structure.In this manual, "/" represent " and/ Or ".
Embodiment
Fig. 1 represents a kind of distributed mode processor chips 200, and it contains m x n storage processing units 100aa- 100mn.These storage processing units 100aa-100mn is both formed on substrate 0.Input bus 110 and each storage processing are single Member coupling, output bus 120 is coupled with each storage processing unit.It is noted that distributed mode processor chips 200 can contain There are up to ten thousand storage processing unit 100aa-100mn.So large number of storage processing unit 100aa-100mn can ensure Extensive parallel computing, to realize that fast mode is handled.
Each storage processing unit 100ij stores an at least pattern containing a mode processing circuit 170 and at least one 3D-M arrays 180.Fig. 2A-Fig. 2 C are three kinds of storage processing unit 100ij circuit block diagrams.In these embodiments, a mould Formula process circuit 180 services for the 3D-M arrays 170 of varying number.Mode processing circuit 180 in Fig. 2A is one 3D-M gusts Row 170 are serviced：The mode data being stored in 3D-M arrays 170 electrically connects 160 by big bandwidth（Referring to Fig. 3 A- Fig. 4）Feeding Mode processing circuit 180, carries out pattern match or pattern-recognition, and produce output mode data with input pattern data 110 120.Mode processing circuit 180 in Fig. 2 B is four storage array 170A-170D services：It is stored in 3D-M arrays 170A- Mode data in 170D electrically connects 160A-160D by big bandwidth（Referring to Fig. 3 A- Fig. 4）Mode processing circuit 180 is sent into, and Pattern match or pattern-recognition are carried out with input pattern data 110.Mode processing circuit 180 in Fig. 2 C is eight storage arrays 170A-170D and 170W-170Z services：The mode data being stored in 3D-M arrays 170A-170D and 170W-170Z passes through big Bandwidth electrically connects 160A-160D and 160W-160Z（Referring to Fig. 3 A- Fig. 4）Send into mode processing circuit 180, and and input pattern Data 110 carry out pattern match or pattern-recognition.It can be seen that what is serviced for more 3D-M arrays from later Fig. 5 A- Fig. 5 C Mode processing circuit 180 has bigger area and stronger function.
Fig. 3 A- Fig. 3 B represent two kinds of typical case 3D-M.Fig. 3 A are a kind of sections of the storage processing unit 100ij based on 3D-W Figure.The information of 3D-W storages uses electrical programming typing.Common 3D-W has 3D-XPoint.Other 3D-W include memristor, Resistance-variable storing device（RRAM）, phase transition storage（PCM）、programmable metallization cell（PMC）、 conductive bridging random-access memory （CBRAM）Deng.According to its programmable number of times, 3D-W is again It is divided into three-dimensional one-time programming memory（Three-dimensional one-time-programmable memory, referred to as 3D-OTP）With three-dimensional repeatedly programmable memory（three-dimensional multiple-time-programmable Memory, referred to as 3D-MTP）.As its name suggests, 3D-OTP can be programmed once, and 3D-MTP can be programmed repeatedly（Including repeating to compile Journey）.3D-OTP technical maturities, it can memory scan pattern base（Such as virus identifications storehouse, network standard storehouse, acoustic model repository, language Model library etc.）, the mode data in these pattern bases, which only increases, not to be changed.3D-MTP is a kind of general-purpose storage, and it can be used to Objective model storage storehouse, such as user data（Including personal code work）Deng.
Storage processing unit 100ij based on 3D-W contains substrate circuitry layer 0K of the formation on substrate 0.Accumulation layer 16A is stacked on substrate circuitry 0K, and accumulation layer 16B is stacked on accumulation layer 16A.Substrate circuitry layer 0K contains accumulation layer 16A, 16B peripheral circuit, it includes transistor 0t and interconnection line 0M.Each accumulation layer（Such as 16A）Contain a plurality of first address Line（Such as 2a, in the y-direction）, a plurality of second address wire（Such as 1a, in the x-direction）Member is stored with multiple 3D-W（Such as 1aa）.Accumulation layer 16A, 16B are coupled by contacting access opening 1av, 3av with substrate 0 respectively.
3D-W storages member 5aa contains one layer of programming layer diode film 14 of film 12 and one.It can be antifuse film to program film 12 （For 3D-OTP）Or other multiple programming films（For 3D-MTP）.Diode film 14 has following generalized character： Under read voltage, its resistance is smaller；When applied voltage is less than read voltage or is in opposite direction with read voltage, its resistance is larger. Diode film can be P-i-N diode or metal oxide（Such as TiO2）Diode etc..
Fig. 3 B are a kind of sectional views of the storage processing unit 100ij based on 3D-P.The information of 3D-P storages is in factory Using mode of printing typing in production process（Print record method）.These information are permanently fixed, and can not be changed after dispatching from the factory.Print record Method can be photoetching（photo-lithography）, nano-imprint method（nano-imprint）, electron beam scanning exposure（e- beam lithography）, DUV scan exposures, laser scanning exposure (laser programming) etc..Common 3D-P has Three-dimensional masking film program read-only memory（3D-MPROM）, it passes through masking film program logging data by photoetching process.3D-P reading speed Degree is faster than 3D-W, and it is adapted to the fixed pattern base of storage（Such as acoustic model repository and language model storehouse）, and realize high-performance mould Formula processing（Such as realize natural language processing and real-time language translation）.
3D-P contains at least two storage member 5aa, 6aa.Storage member 6aa is a kind of low-resistance storage member, and storage member 5aa is A kind of high resistant storage member.Low-resistance storage member 6aa contains a layer diode film 14, and it is more than low-resistance storage member 6aa that high resistant stores member 5aa Containing one layer of high resistance film 12.As a simply example, high resistance film 12 can be layer of silicon dioxide film.The high resistance film 12 is in work In skill flow using print record method storage member 6aa at be physically removed.
In Fig. 3 A- Fig. 3 B 3D-M（Including 3D-W and 3D-P）In, each accumulation layer contains multiple 3D-M arrays.3D-M gusts Row are the set of all storage members that have shared at least one address wire in an accumulation layer.In a 3D-M array, institute It is continuous to have address wire, does not share any address wire from different 3D-M arrays.On the other hand, a 3D-M chip contains many Individual 3D-M modules.Each 3D-M modules contain all accumulation layers in 3D-M, and it pushes up accumulation layer only containing a 3D-M array, and Projection of the 3D-M arrays on substrate determines the border of the 3D-M modules.
Fig. 4 discloses storage processing unit 100ij structure from another angle.The heap of 3D-M arrays 170 of memory module The top of substrate 0 is stacked in, the mode processing circuit 180 of tupe is located in substrate 0, and by 3D-M arrays 170 at least partly Covering.By by largely contacting the big bandwidth that access opening 1av, 3av are constituted between 3D-M arrays 170 and mode processing circuit 180 Communication is realized in electrical connection 160.Because contact access opening 1av, 3av are large number of（Can be with up to ten thousand）And length is very short（Micron Level）, communication bandwidth of the bandwidth far above chip chamber of the interior electrical connection 160 of chip.
The Vertical collection of 3D-M arrays 170 and mode processing circuit 180 brings many advantages：Due to 3D-M arrays 170 not Substrate Area 0 is accounted for, it can be integrated on mode processing circuit 180, this can increase memory capacity, reduce chip area.It is heavier Want, because 3D-M arrays 170 and mode processing circuit 180 are in same chip 200 and apart from close, energy between them Realize large bandwidth.By using extensive parallel computing, distributed mode processor 200 can be realized quick to large-scale pattern base Mode treatment.
Fig. 5 A- Fig. 5 C disclose the specific implementation of three kinds of storage processing units.Fig. 5 A embodiment corresponds to Fig. 2A Middle storage processing unit 100ij.Mode processing circuit 180 is that a 3D-M array 170 is serviced, and it is complete by 3D-M arrays 170 Covering.In this embodiment, 3D-M arrays 170 contain four peripheral circuits, including X-decoder 15,15` and Y-decoder（Including Reading circuit）17th, 17`, mode processing circuit 180 is located between this four peripheral circuits.In fig. 5, due to 3D-M arrays 170 are located above substrate circuitry 0K, and not in substrate circuitry 0K, its projection on substrate 0 is represented by dashed line herein.
In the present embodiment, mode processing circuit 180 is limited between four peripheral circuits, and its area is no more than The area of 3D-M arrays 170, therefore its area is smaller, function is limited.The embodiment is well suited to realize better simply mode treatment（Such as String matching and code matches）.It is obvious that more complicated mode treatment（Such as speech recognition, image recognition）Need bigger Circuit, this needs vacate bigger Substrate Area under 3D-M arrays 170, so as to the layout of mode processing circuit 180.Fig. 5 B- Fig. 5 C, which disclose two kinds, has more large area and more powerful mode processing circuit 180.
Fig. 5 B embodiment corresponds to storage processing unit 100ij in Fig. 2 B.In this embodiment, a mode treatment electricity Road 180 is four 3D-M arrays 170A-170D services.Each 3D-M arrays（Such as 170A）Only two peripheral circuits（Such as X decodings Device 15A and Y-decoder 17A）.Below this four 3D-M arrays 170A-170D, substrate circuitry 0K can be formed with free surface jet One mode processing circuit 180.It is obvious that the mode processing circuit 180 in Fig. 5 B can be four times of Fig. 5 A big, it can realize compared with Complicated mode treatment function.
Fig. 5 C embodiment corresponds to storage processing unit 100ij in Fig. 2 C.In this embodiment, a mode treatment electricity Road 180 is eight 3D-M arrays 170A-170D and 170W-170Z services.This eight 3D-M arrays are divided into two groups of 150A, 150B. Every group（Such as 150A）Including four 3D-M arrays（Such as 170A-170D）.In first group of 150A four 3D-M arrays 170A-170D Lower section, substrate circuitry can form first mode process circuit component A 180A with free surface jet.Similarly, in second group of 150B Four 3D-M arrays 170W-170Z below, substrate circuitry can also free surface jet, form second mode process circuit component B 180B.First mode process circuit component 180A and second mode process circuit component 180B constitutes mode processing circuit 180. In the present embodiment, between adjacent peripheral circuit（Between such as adjacent X-decoder 15A, 15C；In adjacent Y-decoder 17A, Between 17B；Between adjacent Y-decoder 17C, 17D）Leave gap（Such as G）, to form wiring channel 190Xa, 190Ya, 190Yb, is communicated for realizing between different mode process circuit component 150A, 150B or between different mode process circuit.Very Substantially, the mode processing circuit 180 in Fig. 5 C can be the octuple big of Fig. 5 A, and it can realize more complicated mode treatment function.
In some embodiments of the invention, mode processing circuit 180 only needs to complete partial mode processing function.Such as Say, mode processing circuit 180 only needs to complete simple mode processing（Such as the extraction and processing of simple feature）.By the simple mode Pattern after processing screening will further be sent to more powerful external processor by output bus 120（Such as CPU, GPU）In it is complete Into final mode treatment.Because most of pattern in pattern base can be screened out by simple mode processing, the pattern of output is only accounted for The fraction of pattern base, this can reduce the bandwidth pressure of output bus 120.
In distributed mode processor 200, storage processing unit 100ij can use both of which processing mode --- Class processor mode and class memory mode.For class processor mode, storage processing unit 100ij to external world for just as one The individual search modes storehouse that can be carried with it carries out the processor of mode treatment to external user data.Particularly, storage is handled The unit 100ij memory scan database of 3D-M arrays 170；Storage processing unit 100ij input data 110 is user data （Including personal code work）, these user data generally produce in real time, such as network packet；Storage processing unit User data 110 and search modes storehouse are carried out pattern match or pattern-recognition by 100ij.At 3D-M arrays 170 and pattern There is big bandwidth connection 160, this mode treatment mode is stored in separation and deposited than traditional, search modes stock between reason device 180 The mode treatment mode efficiency high of reservoir.
For class memory mode, storage processing unit 100ij to external world for as one be mainly used in store number of users According to and can utilize carry mode processing circuit carry out mode treatment memory.Particularly, user data is stored in for a long time In the 3D-M arrays 170 for storing up processing unit 100ij；Storage processing unit 100ij input data 110 is search modes data； Search modes data 110 and its user data are carried out pattern match or pattern-recognition by storage processing unit 100ij.It is noted that The distributed mode processor chips 200 of multiple use class memory modes can be packaged into storage card as flash chip （Such as SD card, TF cards）And solid state hard disc, the user data for storing magnanimity（Such as user data archives）.Due to each distribution Each storage processing unit 100ij in schema processor chip 200 carries a mode processing circuit 180, this pattern Process circuit 180 only needs to handle the data that 3D-M arrays 170 are stored in storage processing unit 100ij.Therefore, no matter storage card Have much with the capacity of solid state hard disc, the time of its mode treatment all handles coupled close to single-mode process circuit 180 3D-M arrays 170 in time of data for storing.This big advantage is unimaginable for conventional processors.
In class memory mode, storage processing unit 100ij is the final memory device of user data.This and tradition , processor containing in-line memory it is different：In-line memory only interim storage user data in conventional processors, The final memory device or external memory of user data（Such as hard disk, CD, tape）.If user data is stored for a long time In conventional processors, then the conventional processors are only capable of as these data, services, and can not be other data, services.Namely Say, a large number of users data need to use many processors.Because conventional processors are very expensive, this processing mode cost is excessively It is high.Compare therewith, in storage processing unit 100ij proposed by the present invention, mode processing circuit 180 is integrated in 3D-M arrays 170 lower sections, the peripheral circuit with 3D-M arrays（Such as decoder）Formed simultaneously.Because 3D-M will natively form peripheral circuit, And peripheral circuit only accounts for very little area on substrate 0（Referring to Fig. 5 A- Fig. 5 C）, most of Substrate Area can be for rock mechanism Process circuit 180, mode processing circuit 180 is free for 3D-M.Therefore, in distributed mode processor chips A large amount of approximate free mode processing circuits 180 can be formed on 200, each mode processing circuit 180 is specific data（Deposit Storage is in 3D-M arrays 170 coupled thereto）Service.
A simple introduction is done in the application with regard to distributed mode processor below.It is used as an example, distributed mode processing Device 200 is an anti-Malware（anti-malware）Processor, it is mainly used in network security and computer antivirus.Network is pacified Class processor mode can be used entirely：The input data 110 of distributed mode processor 200 is network packet, 3D-M arrays 170 Network standard storehouse and virus identifications storehouse are stored, mode processing circuit 180 carries out pattern match to them.Computer antivirus can be used Class processor mode and class memory mode：For class processor mode, the user data stored in computer is used as input number Transmitted according to 110 to distributed mode processor 200, the storage virus identifications of 3D-M arrays 170 storehouse, mode processing circuit 180 is to it Carry out pattern match；For class memory mode, virus identifications are sent to distributed mode processor as input data 110 200, user data is stored in 3D-M arrays 170, and mode processing circuit 180 carries out pattern match to them.In class processor In mode, 3D-M can be 3D-OTP or 3D-MTP, and it is used to store network standard storehouse and virus identifications storehouse.In class memory side In formula, 3D-M is preferably 3D-MTP, and it stores customer data base.
As another example, distributed mode processor 200 is analyzed available for big data（Such as finance data analysis, electricity Quotient data analysis, bioinformatics）.Big data analysis is related to unstructured data or semi-structured data.It is traditional, using pass It is type database（relational database）Analysis method it is helpless to this.Distributed mode processor 200 can be carried Tall and big data analysis capabilities.In order to improve efficiency, preferably with class memory mode：Big data is as archives storage at 3D-M gusts In row 170, the keyword for data analysis is delivered at distributed mode processor 200, pattern as input pattern data 110 Manage circuit 180 and pattern match is carried out to them.In big data analysis, 3D-M is preferably 3D-MTP, and it is used to store number of users According to.
Distributed mode processor 200 can be also used for speech recognition and/or image recognition., can be with identification process Using class processor mode and class memory mode.For class processor mode, voice/view data that user produces is as defeated Enter data 110 and deliver to distributed mode processor 200,3D-M arrays 170 store various identification model storehouses（Such as acoustic model repository, Language model storehouse, iconic model storehouse etc.）, afterwards schema processor 180 be identified.To class memory mode, what user produced Voice/view data is as archives storage, it is necessary to which the speech signal or picture signal searched are used as input in 3D-M arrays 170 Data 110 deliver to distributed mode processor 200, and mode processing circuit 180 is identified and searched afterwards.In class processor side In formula, 3D-M can be 3D-P, 3D-OTP or 3D-MTP, and it stores acoustic model repository, language model storehouse, iconic model storehouse etc.. In class memory mode, 3D-M is preferably 3D-MTP, its storaged voice/image file storehouse.
It should be appreciated that on the premise of not away from the spirit and scope of the present invention, can be to form and details of the invention It is modified, spirit of their application present invention of this and without prejudice to.Therefore, except the spirit according to appended claims, The present invention should not be restricted by any limitation.

Claims (10)

1. a kind of distributed mode processor (200), it is characterised in that contain：
The input bus (110) of one transmission first mode；
Semi-conductive substrate (0) and multiple storage processing units (100aa-100mn), the multiple storage processing unit are defeated with this Enter bus (110) coupling, each storage processing unit (100ij) contains at least one three-dimensional storage (3D-M) array (170) and one Mode processing circuit (180), wherein：
The 3D-M arrays (170) are stacked on above the substrate (0), the 3D-M arrays (170) storage at least second mode；
The mode processing circuit (180) is located in the substrate (0), and the mode processing circuit (180) is to the first mode and is somebody's turn to do Second mode carries out pattern-recognition or pattern match；
The 3D-M arrays (170) and the mode processing circuit (180) are realized by multiple contact access openings (1av, 3av) One big bandwidth electrical connection (160).
2. distributed mode processor (200) according to claim 1, is further characterized in that：The 3D-M is that three-dimensional can Write storage member（3D-W）.
3. distributed mode processor (200) according to claim 1, is further characterized in that：The 3D-M prints to be three-dimensional Address book stored member（3D-P）.
4. distributed mode processor (200) according to claim 1, is further characterized in that：The 3D-M arrays (170) cover At least partly described mode processing circuit (180) of lid.
5. distributed mode processor (200) according to claim 1, is further characterized in that：The mode processing circuit (180) covered by least two 3D-M arrays (170A, 170B).
6. distributed mode processor according to claim 1 is that (200) are a big data processor, its feature also exists In：The first mode is a search modes, and the second mode is a target pattern, and the 3D-M arrays storage is at least partly The big data, the mode processing circuit (180) carries out string matching.
7. distributed mode processor (200) according to claim 1 is an anti-Malware（ani-malware）Processing Device, is further characterized in that：The first mode is a target pattern, and the second mode is a search modes, described 3D-M gusts Arrange (170) storage at least virus identifications（virus signature）And/or the network standard（network rule）.
8. distributed mode processor (200) according to claim 1 is an antivirus processor, it is further characterized in that：Institute First mode is stated for a search modes, the second mode is a target pattern, 3D-M arrays (170) storage is at least partly User data.
9. distributed mode processor (200) according to claim 1 is one voice/image recognition processor, its feature Also reside in：The first mode is a target pattern, and the second mode is a search modes, and the 3D-M arrays storage is at least Part acoustic model repository, language model storehouse and/or iconic model storehouse.
10. distributed mode processor according to claim 1 is that (200) are one voice/image recognition processor, its It is further characterized in that：The first mode is a search modes, and the second mode is a target pattern, the 3D-M arrays storage At least part user voice/image file storehouse.
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CN202010416473.5A CN111463203A (en) 2016-03-07 2017-03-07 Memory with image recognition function
CN202010416482.4A CN111384051B (en) 2016-03-07 2017-03-07 Memory with speech recognition function
CN202010416492.8A CN111384052B (en) 2016-03-07 2017-03-07 Distributed mode processor with three-dimensional memory array
CN202010416491.3A CN111446250A (en) 2016-03-07 2017-03-07 Processor for enhancing network security
US15/452,728 US20170255834A1 (en) 2016-03-07 2017-03-07 Distributed Pattern Processor Comprising Three-Dimensional Memory Array
CN201710461215.7A CN107392017A (en) 2016-03-07 2017-03-07 Have the memory of virus investigation function concurrently
CN202010416475.4A CN111446246B (en) 2016-03-07 2017-03-07 Memory with data analysis function
CN201710460367.5A CN107316014B (en) 2016-03-07 2017-03-07 Memory with image recognition function
CN201710460363.7A CN107357828A (en) 2016-03-07 2017-03-07 Have the memory of speech identifying function concurrently
CN201710460362.2A CN107393537A (en) 2016-03-07 2017-03-07 Processor for speech recognition
CN202010416480.5A CN111446247B (en) 2016-03-07 2017-03-07 Memory with virus checking function
CN201710459997.0A CN107358100A (en) 2016-03-07 2017-03-07 Strengthen the processor of computer security
CN201710460366.0A CN107358254A (en) 2016-03-07 2017-03-07 Processor for image recognition
CN202010486964.7A CN111627909A (en) 2016-03-07 2017-03-07 Processor with efficient retrieval function
CN202010416474.XA CN111384050A (en) 2016-03-07 2017-03-07 Processor for image recognition
CN202010416486.2A CN111446248B (en) 2016-03-07 2017-03-07 Processor for speech recognition
CN202010416487.7A CN111446249A (en) 2016-03-07 2017-03-07 Processor for enhancing computer security
CN201710461236.9A CN107301222B (en) 2016-03-07 2017-03-07 Big data memory with data analysis function
CN201710459978.8A CN107317803A (en) 2016-03-07 2017-03-07 Strengthen the processor of network security
US15/729,640 US10560475B2 (en) 2016-03-07 2017-10-10 Processor for enhancing network security
US15/729,643 US10489590B2 (en) 2016-03-07 2017-10-10 Processor for enhancing computer security
US15/784,074 US20180189586A1 (en) 2016-03-07 2017-10-13 Storage with In-situ String-Searching Capabilities
US15/784,065 US20180189585A1 (en) 2016-03-07 2017-10-13 Storage with In-situ Anti-Malware Capabilities
US15/973,526 US20180260344A1 (en) 2016-03-07 2018-05-07 Distributed Pattern Storage-Processing Circuit Comprising Three-Dimensional Vertical Memory Arrays
US15/974,659 US20180261226A1 (en) 2016-03-07 2018-05-08 Speech-Recognition Processor
US15/974,655 US20180260477A1 (en) 2016-03-07 2018-05-08 Audio Storage with In-Situ Audio-Searching Capabilities
US15/974,656 US20180260449A1 (en) 2016-03-07 2018-05-08 Distributed Pattern Storage-Processing Circuit Comprising Three-Dimensional Memory Arrays
US15/975,748 US20180260644A1 (en) 2016-03-07 2018-05-09 Data Storage with In-situ String-Searching Capabilities Comprising Three-Dimensional Vertical Memory Arrays
US15/984,358 US20180268235A1 (en) 2016-03-07 2018-05-20 Image-Recognition Processor
US15/989,059 US20180270255A1 (en) 2016-03-07 2018-05-24 Processor Comprising Three-Dimensional Vertical One-Time-Programmable Memory for Enhancing Network Security
US15/988,030 US20180268900A1 (en) 2016-03-07 2018-05-24 Data Storage with In-situ String-Searching Capabilities Comprising Three-Dimensional Vertical One-Time-Programmable Memory
US16/046,956 US20180330087A1 (en) 2016-03-07 2018-07-26 Image Storage with In-Situ Image-Searching Capabilities
US16/248,914 US20190158510A1 (en) 2016-03-07 2019-01-16 Monolithic Three-Dimensional Pattern Processor
US16/258,667 US20190220680A1 (en) 2016-03-07 2019-01-27 Distributed Pattern Processor Package
US16/258,666 US20190171815A1 (en) 2016-03-07 2019-01-27 Multi-Level Distributed Pattern Processor
US16/371,075 US20190230096A1 (en) 2016-03-07 2019-03-31 Monolithic Three-Dimensional Pattern Processor Supporting Massive Parallelism
US16/435,494 US20190327247A1 (en) 2016-03-07 2019-06-08 Monolithic Three-Dimensional Pattern Processor Comprising Many Storage-Processing Units
US16/543,554 US20190370465A1 (en) 2016-03-07 2019-08-17 Searchable Storage
US16/594,070 US20200036733A1 (en) 2016-03-07 2019-10-06 Processor For Enhancing Network Security
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CN201710460363.7A Division CN107357828A (en) 2016-03-07 2017-03-07 Have the memory of speech identifying function concurrently
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CN111384051B (en) 2022-09-27
CN107392017A (en) 2017-11-24
CN111446246A (en) 2020-07-24
CN111627909A (en) 2020-09-04
CN107301222B (en) 2020-11-10
CN107317803A (en) 2017-11-03
CN111446247A (en) 2020-07-24

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