JP5996324B2 - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device that uses a nonvolatile variable resistance element in which a variable resistor made of a metal oxide or metal oxynitride is sandwiched between a first electrode and a second electrode for storing information. In particular, the present invention relates to a structure of a three-dimensional memory cell array in which a plurality of such variable resistance elements are arranged in a three-dimensional matrix.

  With the spread of mobile devices such as portable electronic devices, flash memory is widely used as a large-capacity and inexpensive non-volatile memory capable of holding stored data even when the power is turned off. However, in recent years, the limit of miniaturization of flash memory has become apparent, and non-volatile such as MRAM (Magnetic Resistance Change Memory), PCRAM (Phase Change Memory), CBRAM (Solid Electrolyte Memory), RRAM (Resistance Change Memory) (registered trademark) Active memory has been actively developed. Among these nonvolatile memories, the RRAM can be rewritten at high speed, and can be easily manufactured because a simple binary transition metal oxide can be used as a material, and has high compatibility with an existing CMOS process. It is attracting attention.

  In a memory device composed of memory cells using a two-terminal variable resistance element such as an RRAM, the combination of the memory cell structure and the memory cell array structure that can maximize the capacity is composed of a single variable resistance element. This is a cross-point type memory cell array in which 1R type memory cells are formed at the intersections of mutually orthogonal wirings. In such a 1R type memory cell, there is no element that limits the current flowing through the variable resistance element in the memory cell. Therefore, a three-dimensional memory cell array is easily formed by stacking a plurality of cross-point type memory cell arrays on the top and bottom. (For example, see Patent Document 1 below). However, since there is no current limiting element in the 1R type memory cell, a parasitic current (sneak current) passes through the memory cell connected to the non-selected wiring other than the memory cell formed between the two selected wirings. Therefore, there is a problem that such a parasitic current is superimposed on the read current flowing through the selected memory cell, making it difficult or impossible to determine the read current.

  As a countermeasure against the parasitic current in the 1R type memory cell, a transistor is connected in series to the variable resistance element to form a 1T1R type memory cell structure, or a current limiting element such as a diode or a varistor is connected in series to the variable resistance element. There is a method of using a 1D1R type memory cell structure. The 1T1R type memory cell can control the magnitude and direction of the current flowing through the variable resistance element and has excellent controllability. However, since the occupied area is large and a multi-layer structure cannot be easily formed, the memory capacity is as large as the chip area. Limited to design rules. On the other hand, the 1D1R type memory cell can be easily formed with a minimum area unit element having a cross-point structure by optimizing the manufacturing process. Suitable for capacity.

  However, when forming a three-dimensional memory cell array by multilayering a conventional cross-point memory cell array, the number of photolithography processes by an expensive state-of-the-art exposure apparatus for forming a minimum size pattern increases in proportion to the number of stacked layers. The cost merit is limited.

  In order to realize a large-capacity and inexpensive RRAM, Patent Documents 2 and 3 propose a cylindrical stacked structure as a novel memory cell array structure that does not increase the number of mask processes due to multilayering. This structure is shown in the cross-sectional structure diagram of FIG.

  As shown in FIG. 23, a flat plate electrode 45 formed of a flat conductor is laminated in two or more layers via an interlayer insulating film 46, and a through-hole penetrating the flat plate electrode 45 and the interlayer insulating film 46 is formed. A plurality of layers are formed in each layer of the plate electrode. The columnar electrode 41 (41a, 41b) passes through the through hole without contacting the flat plate electrode 45, and the variable resistor material 42 is formed in the annular portion 47 sandwiched between the flat plate electrode 45 and the columnar electrode 41. Each of the annular portions is formed in an annular shape. Thus, the outer peripheral surface of the annular variable resistor material 42 is electrically connected to the plate electrode 45, the inner peripheral surface is electrically connected to the columnar electrode 41, and variable resistance elements are provided at the respective connection points. A memory cell 47 is formed. The columnar electrode 41 is connected to the drain region of the MOS transistor formed below.

  Patent Document 2 shows a cylindrical stacked structure using 1D1R type as a memory unit, and Patent Document 3 shows a stacked structure using 1R type and 1R connected in series with a bidirectional rectifying element as a memory unit.

  However, as described above, the 1R type requires countermeasures for circuit current against the sneak current.

  On the other hand, a metal oxide resistance change element can be a unipolar switch that causes a continuous resistance change with a voltage in one direction, but in terms of stable and high-speed switching, voltages with different polarities are applied for writing and erasing. The bipolar switch is excellent. In a 1D1R type memory using a PN junction diode as a rectifying element as disclosed in Patent Document 2, such a variable resistance element exhibiting the characteristics of a bipolar switch cannot be operated satisfactorily.

  On the other hand, Patent Document 3 discloses a memory structure that can cope with a bipolar variable resistance element by inserting a bidirectional rectifying element between a variable resistance element and an electrode.

  In Patent Document 4, it is necessary to obtain non-linear voltage-current characteristics when a metal / insulator / metal (MIM) type two-terminal element is used as a bidirectional rectifying element in order to suppress a sneak current. The relationship between the work function of a simple metal, the band structure of the insulator, and the film thickness of the insulator is shown.

US Patent Application Publication No. 2005/0230724 JP 2008-181978 A JP 2010-287872 A JP 2011-90758 A

  FIG. 24 shows an example of a specific structure of a memory cell including a bidirectional rectifying element and a variable resistance element disclosed in Patent Document 3. Bidirectional rectification between the variable resistor material 42 and the plate electrode 45 (FIG. 24A) or between the variable resistor material 42 and the columnar electrodes 41 (41a, 41b) (FIG. 24B). An insulating film 44 is inserted. FIG. 25 shows ideal voltage-current characteristics of the bidirectional rectifying device.

  The problem with the structure shown in FIG. 24 is that the variable resistor material and the bidirectional rectifying material (insulating film) are directly connected without a metal electrode, as will be described in detail below.

  FIG. 26A conceptually simplifies the structure shown in FIG. FIG. 26B is an enlarged view focusing on one memory cell of FIG.

  In the element shown in FIG. 26, when the resistance change of the variable resistor 42 occurs uniformly, the voltage distribution is uniform at the interface where the bidirectional rectifier material 44 and the variable resistor material 42 are in contact with each other. The ideal voltage-current characteristics shown in

  However, as shown in the enlarged view of FIG. 26B, when the resistance change occurs in a limited region such as the filament 48 formed in the variable resistor material 42, the bidirectional rectifying material 44 and The voltage is unevenly distributed at the interface where the variable resistor material 42 contacts, and the bidirectional rectifying element does not exhibit ideal voltage-current characteristics.

  In view of the above problems in the prior art, the present invention includes a three-dimensional memory cell array in which memory cells in which bidirectional rectifying elements having uniform bidirectional rectifying characteristics and variable resistance elements are connected in series are three-dimensionally integrated. An object of the present invention is to provide a nonvolatile semiconductor memory device having a large capacity and high reliability and a method for manufacturing the same.

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention has a first direction in which two-terminal type memory cells each having a nonvolatile variable resistance element whose resistance characteristics change by voltage application are orthogonal to each other. A non-volatile semiconductor memory device having a plurality of three-dimensional memory cell arrays arranged in a three-dimensional matrix, respectively in the second direction and the third direction,
The three-dimensional memory cell array
A first electrode extending in at least one of the first direction and the second direction, wherein the first electrode is laminated in the third direction by two or more layers through an interlayer insulating film;
A plurality of through holes penetrating in the third direction through the stacked two or more first electrodes and the interlayer insulating film therebetween, the through holes being two-dimensional in the first direction and the second direction; Arranged
A plurality of second electrodes configured by columnar conductors extending in the third direction and filling the through holes without contacting the first electrodes;
The memory cell is
An annular third electrode, an annular variable resistor that is in contact with either the inner peripheral side surface or the outer peripheral side surface of the third electrode, and an inner peripheral side surface or the outer peripheral side surface of the third electrode are in contact with each other An annular insulating film,
The first electrode is electrically connected to an outer peripheral side surface of the variable resistor and the annular insulating film that is not in contact with the third electrode, and the second electrode is connected to the variable resistor. An annular memory cell is formed by electrically connecting the inner peripheral side surface of the body and the annular insulating film that is not in contact with the third electrode,
The third electrode is formed separately in the third direction between the memory cells connected to the same second electrode.

  According to the nonvolatile semiconductor memory device of the present invention having the above characteristics, the annular insulating film constituting the bidirectional rectifying element and the variable resistor are connected via the third electrode, and the third electrode is the third electrode. Since it is electrically separated in the direction (axial direction of the through hole), a memory cell in which a stable and uniform bidirectional rectifying element and a variable resistance element are connected in series is arranged three-dimensionally, A high-capacity, inexpensive, and highly reliable nonvolatile semiconductor memory device can be realized.

  Here, the “annular” memory cell is not limited to the case where the shape of the memory cell is an annular shape, and a ring having a square shape, a triangular shape, or other various shapes is conceivable depending on the shape of the through hole.

  FIG. 27 shows a simplified schematic diagram of the memory cell structure of the present invention in comparison with FIG. In FIG. 27, an intermediate electrode 43 is inserted as a third electrode between the variable resistor material 42 and the bidirectional rectifying material 44. Thereby, since the voltage distribution at the interface between the electrode 43 and the bidirectional rectifying material is uniform, the bidirectional rectifying element can exhibit ideal voltage-current characteristics shown in FIG.

  In the nonvolatile semiconductor memory device according to the present invention having the above characteristics, the first electrode is electrically connected to an outer peripheral side surface of the annular insulating film, and the second electrode is an inner periphery of the variable resistor. It can be set as the structure electrically connected with the side surface.

The nonvolatile semiconductor memory device according to the present invention having the above characteristics further includes the variable resistor, the third electrode, and one of the first electrode and the second electrode connected to the variable resistor. , Constituting the variable resistance element,
The annular insulating film, the third electrode, and the other electrode connected to the annular insulating film among the first electrode and the second electrode can constitute a two-terminal bidirectional rectifier. .

  In the nonvolatile semiconductor memory device according to the present invention having the above characteristics, the variable resistor is further electrically separated in the third direction between the memory cells connected to the same second electrode. Two features.

The nonvolatile semiconductor memory device according to the present invention having the above characteristics further includes:
Select transistors are arranged in a plurality of two-dimensional matrices in the first direction and the second direction, respectively, adjacent to the arrangement direction of the three-dimensional memory cells in the third direction,
It is preferable that the second electrode is connected to one of the input / output terminal pairs of the selection transistor at a top surface or a bottom surface thereof.

  In the nonvolatile semiconductor memory device according to the present invention having the above characteristics, it is preferable that the variable resistor is made of a transition metal oxide, an aluminum oxide, or an oxynitride of a transition metal.

In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes:
A method of manufacturing a nonvolatile semiconductor memory device according to the present invention having the above characteristics,
A step of alternately depositing a first electrode material and an interlayer insulating film on a substrate to form a laminated structure of the first electrode material and the interlayer insulating film;
Forming a plurality of through holes penetrating the laminated structure in the laminated structure so as to be two-dimensionally arranged in a first direction and a second direction parallel to the substrate surface and orthogonal to each other;
Etching and removing the first electrode material exposed on the side wall of the through hole by a predetermined thickness, and forming a recess on the side wall of the through hole;
Depositing an insulating film material to be a nonlinear tunnel film and a third electrode material so as to cover the side wall surface including the concave portion of the through hole, respectively;
Removing the third electrode material formed on the side wall surface excluding the concave portion of the through hole, and leaving the third electrode material in the concave portion of the through hole;
Depositing a variable resistor material so as to cover a side wall surface of the through hole;
A step of filling the through hole with a second electrode material.

In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes:
A method of manufacturing a nonvolatile semiconductor memory device according to the present invention having the above characteristics,
A step of alternately depositing dummy films and interlayer insulating films on the substrate to form a laminated structure of the dummy films and the interlayer insulating films;
Forming a plurality of through holes penetrating the laminated structure in the laminated structure so as to be two-dimensionally arranged in a first direction and a second direction parallel to the substrate surface and orthogonal to each other;
Etching the dummy film exposed on the side wall of the through hole by a predetermined thickness and forming a recess on the side wall of the through hole;
A step of sequentially depositing an insulating film material and a third electrode material to be a nonlinear tunnel film so as to cover a side wall surface including the concave portion of the through hole;
Removing the third electrode material formed on the side wall surface excluding the concave portion of the through hole, and leaving the third electrode material in the concave portion of the through hole;
Depositing a variable resistor material so as to cover a side wall surface of the through hole;
Filling the through hole with a second electrode material;
Forming an opening for processing adjacent to the through hole in a portion where the dummy film of the stacked structure remains;
Removing the dummy film sandwiched between the interlayer insulating films through the opening;
Depositing and embedding a first electrode material in the region where the dummy film has been removed;
Filling the opening with an insulating film after removing the first electrode material deposited on the side wall of the opening until the interlayer insulating film is exposed on the side wall surface of the opening. Is the second feature.

In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes:
A method of manufacturing a nonvolatile semiconductor memory device according to the present invention having the above characteristics,
A step of alternately depositing dummy films and interlayer insulating films on the substrate to form a laminated structure of the dummy films and the interlayer insulating films;
Forming a plurality of through holes penetrating the laminated structure in the laminated structure so as to be two-dimensionally arranged in a first direction and a second direction parallel to the substrate surface and orthogonal to each other;
Etching the dummy film exposed on the side wall of the through hole by a predetermined thickness and forming a recess on the side wall of the through hole;
Depositing a third electrode material so as to cover a side wall surface including the concave portion of the through hole;
Removing the third electrode material formed on the side wall surface excluding the concave portion of the through hole, and leaving the third electrode material in the concave portion of the through hole;
Depositing a variable resistor material so as to cover a side wall surface of the through hole;
Filling the through hole with a second electrode material;
Forming an opening for processing adjacent to the through hole in a portion where the dummy film of the stacked structure remains;
Removing the dummy film sandwiched between the interlayer insulating films through the opening;
Depositing an insulating film material to be a nonlinear tunnel film and a first electrode material in order in the region from which the dummy film has been removed, and filling the region from which the dummy film has been removed with the first electrode material;
Filling the opening with an insulating film after removing the first electrode material deposited on the side wall of the opening until the insulating film material is exposed on the side wall surface of the opening. Is the third feature.

The method of manufacturing the nonvolatile semiconductor memory device according to the third aspect of the present invention further includes:
The dummy film is a precursor material that is a precursor of the third electrode material;
Forming the recess on the side wall of the through hole, depositing the third electrode material so as to cover the side wall surface including the recess of the through hole, and on the side wall surface of the through hole excluding the recess. A fourth feature is that, instead of the step of removing the formed third electrode material, there is a step of changing a part of the dummy film exposed on the side wall of the through hole to the third electrode material. .

In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes:
A method of manufacturing a nonvolatile semiconductor memory device according to the present invention having the above characteristics,
A step of alternately depositing a first dummy film and an interlayer insulating film on a substrate to form a laminated structure of the first dummy film and the interlayer insulating film;
Forming a plurality of through holes penetrating the laminated structure in the laminated structure so as to be two-dimensionally arranged in a first direction and a second direction parallel to the substrate surface and orthogonal to each other;
Filling the through hole with a second dummy film;
Forming an opening for processing in the vicinity of the through hole in a portion where the first dummy film of the stacked structure remains;
Removing the first dummy film sandwiched between the interlayer insulating films through the opening until the second dummy film is exposed;
In the region from which the first dummy film has been removed, a precursor material that is a precursor of a third electrode material, an insulating film material that becomes a nonlinear tunnel film, and a first electrode material are sequentially deposited, and the first dummy film Filling the region from which the first electrode material is removed with the first electrode material;
Filling the opening with an insulating film after removing the first electrode material deposited on the side wall of the opening until the insulating film material is exposed on the side wall surface of the opening; and
Removing the second dummy film filling the through hole;
Changing a part of the precursor material exposed on the side wall of the through hole to the third electrode material;
Depositing a variable resistor material so as to cover a side wall surface of the through hole;
And filling the through-hole with a second electrode material.

The method for manufacturing the nonvolatile semiconductor memory device according to the fourth or fifth feature of the present invention further includes:
The precursor material is polycrystalline silicon;
A sixth feature is that the step of changing a part of the precursor material into the third electrode material is a step of siliciding the polycrystalline silicon exposed on the side wall of the through hole.

The method for manufacturing the nonvolatile semiconductor memory device according to the fourth or fifth feature of the present invention further includes:
The precursor material is a metal oxide film of an oxidizable metal;
The step of changing a part of the precursor material to the third electrode material changes the metal oxide film exposed on the side wall of the through hole to the metal to be oxidized by reduction treatment, or is a conductive material having many oxygen vacancies. A seventh feature is that the process is a process of changing to a conductive film.

The method for manufacturing a nonvolatile semiconductor memory device according to the present invention having any one of the first to seventh features further includes a step of forming selection transistors in a matrix on the substrate.
The step of forming the through hole is preferably a step of forming the through hole in which the source region or the drain region of the selection transistor is exposed on the bottom surface.

The method for manufacturing a nonvolatile semiconductor memory device according to the present invention having any one of the first to seventh characteristics further includes:
A forming step of applying a voltage between the first electrode material formed between the interlayer insulating films and the second electrode material formed in the through hole;
In the forming step, the resistance state of the portion of the variable resistor material that contacts the third electrode material is reduced, and the resistance state is changed from an initial high resistance state to a variable resistance state that changes due to voltage application, The portion of the variable resistor material that has changed to the variable resistance state functions as a variable resistor, and the portion of the variable resistor material that contacts the interlayer insulating film remains in the initial high resistance state. An eighth feature is that the variable resistor is electrically separated and formed in the third direction.

  According to the method for manufacturing a nonvolatile semiconductor memory device of the present invention having any one of the first to eighth features, the third electrode that connects the variable resistor and the annular insulating film that forms the bidirectional rectifying element. Can be electrically separated and formed in the third direction (the axial direction of the through hole). As a result, a large-capacity, inexpensive, and highly reliable non-volatile semiconductor comprising a three-dimensional array of stable and uniform bidirectional rectifying elements and variable resistance elements connected in series A storage device can be manufactured.

  According to the present invention, it becomes possible to three-dimensionally integrate memory cells having a simple structure in which a bidirectional rectifying element and a variable resistance element are integrated, and the manufacturing cost of a nonvolatile semiconductor memory device can be greatly reduced. Can do. In the present invention, since the bidirectional rectifying element is connected to the third electrode (intermediate electrode) formed separately in the third direction, it has a stable and uniform bidirectional rectifying characteristic. Thus, a nonvolatile semiconductor memory device having a large capacity, low cost, and high reliability is realized.

1 is a structural cross-sectional view showing a schematic configuration of a three-dimensional memory cell array used in a nonvolatile semiconductor memory device according to an embodiment of the present invention. 1 is an equivalent circuit diagram showing a schematic configuration of a three-dimensional memory cell array used in a nonvolatile semiconductor memory device according to an embodiment of the present invention. Process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device concerning 2nd Embodiment of this invention Process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device concerning 2nd Embodiment of this invention Process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device concerning 2nd Embodiment of this invention FIG. 7 is a layout diagram showing an example of the arrangement of through holes and processing openings in the method for manufacturing a nonvolatile semiconductor memory device according to the embodiment of the present invention. Process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device concerning 2nd Embodiment of this invention Structural sectional view showing a schematic configuration of a three-dimensional memory cell array of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. Sectional drawing explaining structure of an example of a connection method between a three-dimensional memory cell array and a decoder in a nonvolatile semiconductor memory device according to a second embodiment of the present invention Structural sectional view showing a schematic configuration of a three-dimensional memory cell array of a nonvolatile semiconductor memory device according to a third embodiment of the present invention. Sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 3rd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 3rd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 3rd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device concerning 4th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device concerning 4th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device concerning 4th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device concerning 4th Embodiment of this invention Structural sectional view showing a schematic configuration of a three-dimensional memory cell array of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention. FIG. 6 is a layout diagram illustrating another example of the arrangement of through holes and processing openings in the method for manufacturing a nonvolatile semiconductor memory device according to the embodiment of the present invention. Structural sectional view showing an example of a configuration of a conventional three-dimensional memory cell array Structural sectional view showing an example of a configuration of a conventional three-dimensional memory cell array including a bidirectional rectifying element Graph showing voltage-current characteristics of bidirectional rectifier Schematic diagram for explaining the problems of the configuration of a conventional three-dimensional memory cell array including a bidirectional rectifying element Schematic diagram of the configuration of the memory cell of the present invention having a bidirectional rectifying element

<First Embodiment>
Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention (hereinafter, appropriately referred to as “device 1 of the present invention”) and a manufacturing method thereof will be described with reference to the drawings. In the structural cross-sectional views shown below, the essential parts are appropriately emphasized, and the scales of the dimensions of each component on the drawings do not necessarily match the scales of the actual dimensions. The same applies to each of the following embodiments.

  FIG. 1 shows a sectional view of the structure of a three-dimensional memory cell array of the device 1 of the present invention. On the semiconductor substrate 20, select transistors 21 are arranged in a plurality of two-dimensional matrices in a first direction (X direction) and a second direction (Y direction) that are parallel to the substrate and perpendicular to each other. In the present embodiment, the selection transistor 21 is a vertical transistor, and the source region 23 and the drain region 24 are arranged vertically so that the channel region 25 is sandwiched therebetween. The channel region 25 is surrounded by the gate electrode 22 with the gate insulating film 26 interposed therebetween. The gate electrode 22 extends in the second direction (Y direction) so as to connect the gate electrodes 22 of selection transistors having the same position in the first direction (X direction) to each other. On the other hand, the source region 23 extends in the first direction (X direction) so that the source regions 23 of the selection transistors having the same position in the second direction (Y direction) are connected to each other.

  On the drain region 24 of each select transistor, a through-hole penetrating the laminated structure of the plate electrode (first electrode) 15 and the interlayer insulating film 16 extending in a plane in the X direction and the Y direction is provided. A plurality of annular memory cells 17 are formed in the third direction (Z direction) along the inner peripheral side surface of the through hole.

  The memory cell 17 includes an annular variable resistor material 12, an annular intermediate electrode (third electrode) 13, and an annular insulating film or semiconductor film (bidirectional rectifying film) 14 having bidirectional rectification, The inner peripheral side surface of the annular intermediate electrode 13 is electrically connected to the outer peripheral side surface of the variable resistor material 12, and the outer peripheral side surface of the annular intermediate electrode 13 is electrically connected to the inner peripheral side surface of the bidirectional rectifying film 14. ing. The outer peripheral side surface of the bidirectional rectifying film 14 is electrically connected to the plate electrode 15, and the inner peripheral side surface of the variable resistor material 12 is electrically connected to the columnar electrode (second electrode) 11, thereby A memory cell 17 is configured in which an element and a bidirectional rectifying element are connected in series. The variable resistor material 12, and the columnar electrode 11 and the intermediate electrode 13 in contact with the variable resistor material 12 constitute a variable resistance element. The insulating film or semiconductor film 14, and the flat plate electrode 15 and the intermediate electrode 13 in contact with the insulating film or the semiconductor film 14 constitute a bidirectional rectifying element.

  Here, as shown in FIG. 1, the intermediate electrode 13 is formed so as to be separated in the third direction for each memory cell 17 without extending in the third direction in the through hole.

  As the bidirectional rectifying film 14, it is preferable to use a film having a relatively low energy at the bottom of the conduction band, such as a Si nitride film or ZnO, because it is easy to obtain nonlinear voltage-current characteristics. Here, the work function of the electrode material, the thickness of the bidirectional rectifying film 14 and the band structure can be set so as to exhibit nonlinear voltage-current characteristics by satisfying the conditions shown in Patent Document 4. The film thickness of the bidirectional rectifying film 14 is preferably about 1 nm to 5 nm.

  The variable resistor material 12 is made of a metal oxide material or a metal oxynitride material. Specifically, as the variable resistor material 12, for example, hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), tantalum oxide (TaOx), and tungsten oxide (WOx) having an affinity with a semiconductor process. Aluminum oxide (AlOx), hafnium oxynitride (HfOxNy), zirconium oxynitride (ZrOxNy), titanium oxynitride (TiOxNy), tantalum oxynitride (TaOxNy), tungsten oxynitride (WOxNy), aluminum oxynitride (AlOxNy), etc. Can be used. Alternatively, an oxide or oxynitride of a transition metal element selected from nickel (Ni), vanadium (V), cobalt (Co), zinc (Zn), iron (Fe), and copper (Cu) is included. Materials. Alternatively, a stacked structure in which a plurality of these materials are stacked may be used. However, the present invention is not limited to this. Any material can be used for the variable resistor material 12 as long as an element whose resistance characteristics change in response to voltage application can be realized.

  When the variable resistance element is configured by using the metal oxide or the metal oxynitride as the variable resistance material 12, the variable resistance element in the initial state immediately after manufacture is changed into a high resistance state and a low resistance state by electrical stress. In order to make it possible to switch between the two (variable resistance state), before use, a voltage pulse having a larger voltage amplitude and longer pulse width than the voltage pulse used for normal rewrite operation is applied to the variable resistance element. It is necessary to form a current path (filament) in which resistance switching occurs. Such voltage application processing is called forming processing. And the part in which a filament is formed by this forming process in the variable resistor material 12 functions as a variable resistor. It is known that the filament formed by the forming process determines the electrical characteristics (switching characteristics) of subsequent elements.

For the electrode material (in this embodiment, the columnar electrode (first electrode) 11 and the intermediate electrode (third electrode) 13) sandwiching the variable resistor material 12, for example, Ti, Ta, Hf, Zr, Examples thereof include metal materials made of TiN, Pt, Ru, and W, or conductive oxides such as RuO ₂ , IrO ₂ , and ITO (Indium Tin Oxide). The material of both electrodes is not particularly limited as long as it is an element in which the electrical resistance between both electrodes changes according to the application of a voltage between both electrodes.

In particular, the resistance change is considered to occur at the interface between the electrode side having a large potential barrier and a large work function and the metal oxide or metal oxynitride. Therefore, of the two electrodes sandwiching the variable resistor material 12, one electrode is made of a conductive material having a large work function so as to be in Schottky junction with the variable resistor material 12, and the other electrode is It is preferable to configure the conductive material with a small function so as to be in ohmic contact with the variable resistor material 12. With this configuration, it is known that the variable resistance element exhibits stable resistance switching. Specifically, one electrode is selected from a conductive material having a work function smaller than 4.5 eV (for example, Ti, Ta, Hf, Zr, etc.), and the other electrode has a work function of 4.5 eV or more. It is preferable to select from conductive materials (eg, Pt, TiN, Ru, RuO ₂ , ITO, etc.).

  In the present embodiment, the columnar electrode 11 has a two-layer structure of a peripheral electrode 11a in contact with the variable resistor material 12 and an internal electrode 11b that covers the peripheral electrode 11a and fills the through hole. The peripheral electrode 11a in contact with the variable resistor material 12 is preferably made of a metal that is easily oxidized such as Ti, Hf, Zr, and Ta. This is to facilitate the movement of oxygen from the variable resistor material 12 in a forming process to be described later. Since these metals have a low work function, it is preferable to use a material having a high work function as the intermediate electrode 13. Specifically, for example, TiN, TaN, Ru, Ir or the like is preferably used. On the other hand, for example, TiN can be used as the internal electrode 11b. Further, as the plate electrode 15, for example, TiN, TaN or the like can be used.

  As shown in FIG. 1, the three-dimensional memory cell array of the device 1 of the present invention has a plurality of through holes arranged in the first direction (X direction) and the second direction (Y direction) on the drain region 24 of the selection transistor 21. As a result, the annular memory cells 17 are separately formed in the third direction (Z direction) along the inner peripheral side surface of the through hole, thereby forming a three-dimensional memory cell array. A source region 23 (first selection line) extending in the second direction (Y direction), a wiring (second selection line) extending in the first direction (X direction) connecting the gate electrodes 22 to each other, and a plate electrode ( The position of the memory cell to be operated in the three-dimensional memory cell array is specified by the wiring (third selection line) connected to the first electrode 15 separately. The first selection line is connected to a first decoder (not shown), the second selection line is connected to a second decoder (not shown), and the third selection line is connected to a third decoder (not shown).

  FIG. 2 shows an equivalent circuit diagram by extracting a memory cell array (hereinafter referred to as “two-dimensional XZ memory cell array”) 18 having the same position in the Y direction connected to the same second selection line in FIG. . The two-dimensional XZ memory cell array 18 is equivalent to a 1D1R type memory cell array including a bidirectional rectifying element. The two-dimensional XZ memory cell array 18 of the three-dimensional memory cell array is selected by bringing the selection transistors 21 having the same position in the Y direction into the conductive state via the second selection line. Furthermore, by applying a voltage separately to the columnar electrode (second electrode) 11 via the first selection line and applying a voltage separately to the plate electrode (first electrode) 15 via the third selection line, The X-direction and Z-direction positions of the memory cells to be operated in the selected two-dimensional XZ memory cell array 18 can be selected.

  The device 1 of the present invention further includes a voltage generation circuit for generating voltages necessary for memory cell rewriting and reading memory operations and a forming process, the first to third decoders, and the voltage generation circuit. A control circuit for controlling the memory operation of the selected memory cell in the three-dimensional memory cell array, and a read circuit for determining the storage state (resistance state) of the selected memory cell during the read operation. It is prepared for. Since a known configuration can be used for the voltage generation circuit, the control circuit, and the readout circuit, detailed description thereof is omitted.

  Below, the manufacturing method of the device 1 of the present invention will be described in detail with reference to the drawings. 3 to 5 are schematic structural cross-sectional views in each step when manufacturing the element 1 of the present invention.

  First, a plate electrode (first electrode material) 15 and an interlayer are formed on a substrate in which selection transistors 21 are two-dimensionally arranged in a first direction (X direction) and a second direction (Y direction) that are parallel to the substrate and orthogonal to each other. Insulating films 16 are alternately deposited to form a laminated structure of the first electrode material 15 and the interlayer insulating film 16. The film thickness of the interlayer insulating film 16 is about 30 nm to 100 nm, and the film thickness of the first electrode material 15 is also about the same as 30 nm to 100 nm. After that, a plurality of through holes 31 penetrating the stacked structure are formed by etching directly above the drain region 24 of the select transistor 21 to a depth at which the drain region 24 of the select transistor 21 is exposed at the bottom of the through hole. A structural sectional view of this state is shown in FIG. FIG. 3A shows an example in which the first electrode material 15 is stacked in four stages in the third direction (Z direction). In the present embodiment, the cross-sectional shape of the through hole 31 is a circle having a diameter of 30 nm, but the present invention is not limited to this.

  Next, the flat plate electrode (first electrode material) 15 exposed on the side wall of the through hole 31 is selectively etched away by a predetermined thickness to form a recess on the side wall of the through hole 31. A structural sectional view of this state is shown in FIG.

  Thereafter, the bidirectional rectifying film 14 serving as a nonlinear tunnel film and the metal film 13 serving as an intermediate electrode material are respectively formed in the through holes 31 by using an isotropic film forming method such as ALD (Atomic Layer Deposition). It deposits so that the side wall surface containing the recessed part may be covered. The thickness of the deposited metal film 13 is preferably about 10 nm. A sectional view of the structure in this state is shown in FIG.

Thereafter, the metal film 13 is etched, and the metal film 13 formed on the side wall surface (that is, the side wall surface facing the interlayer insulating film 16) excluding the concave portion of the through hole 31 is removed. This etching can be performed, for example, by plasma etching using a chlorine-based gas (Cl ₂ , BCl ₃ , CCl _4, etc.). At this time, the metal film 13 at the bottom of the through hole 31 is also removed at the same time. Thereby, the metal film 13 remains only in the recess, and the intermediate electrode (third electrode) is formed separately in the axial direction (third direction) of the through hole 31. A sectional view of the structure in this state is shown in FIG.

  Thereafter, the bidirectional rectifying film 14 remaining at the bottom is removed, and the variable resistor material 12 is deposited so as to cover the side wall surface of the through hole 31. A structural cross-sectional view of this state is shown in FIG.

  Thereafter, the variable resistor material 12 remaining at the bottom of the through hole 31 is removed by, for example, RIE (reactive ion etching), and the drain region 24 of the selection transistor 21 is exposed at the bottom of the through hole 31. Is filled with the second electrode material 11 to form a columnar second electrode. Thereafter, the second electrode material deposited on the upper surface is removed until the interlayer insulating film 16 is exposed. Thereby, a three-dimensional memory cell array is manufactured.

  Thereafter, by forming peripheral circuits of the three-dimensional memory cell array, the inventive device 1 shown in FIG. 1 is manufactured.

  Subsequently, preferably, a forming step of applying a voltage between the plate electrode (first electrode) 15 and the columnar electrode (second electrode) 11 of the device 1 of the present invention may be provided. As a result, the resistance state of the portion of the variable resistor material 12 in contact with the intermediate electrode (third electrode) 13 changes from the initial high resistance state to the variable resistance state in which the resistance characteristics change due to voltage application as the filament is formed. Reduce resistance. The portion of the variable resistor material that has changed to such a variable resistance state functions as a variable resistor. On the other hand, the portion of the variable resistor material 12 that does not contact the intermediate electrode (third electrode) 13 (that is, the portion that contacts the interlayer insulating film 16) remains in the initial high resistance state. Does not contribute. As a result, the variable resistor is formed by being electrically separated in the third direction only at the portion where the variable resistor is in contact with the intermediate electrode 13.

Second Embodiment
Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention (hereinafter, appropriately referred to as “present invention device 2”) and a manufacturing method thereof will be described with reference to the drawings. 6 to 8 and FIG. 10 are schematic structural cross-sectional views in respective steps when the device 2 of the present invention is manufactured.

  First, the dummy film 32 and the interlayer insulating film 16 are alternately arranged on the substrate on which the selection transistors 21 are two-dimensionally arranged in the first direction (X direction) and the second direction (Y direction) which are parallel to the substrate and orthogonal to each other. By depositing, a laminated structure of the dummy film 32 and the interlayer insulating film 16 is formed. The film thickness of the interlayer insulating film 16 is about 30 nm, and the film thickness of the first electrode material 15 is also about 30 nm. After that, a plurality of through holes 31 penetrating the stacked structure are formed by etching directly above the drain region 24 of the select transistor 21 to a depth at which the drain region 24 of the select transistor 21 is exposed at the bottom of the through hole. A structural sectional view of this state is shown in FIG.

  Next, the dummy film 32 exposed on the side wall of the through hole 31 is selectively etched away by a predetermined film thickness to form a recess on the side wall of the through hole 31. A structural sectional view of this state is shown in FIG.

  Thereafter, the bidirectional rectifying film 14 serving as a nonlinear tunnel film and the metal film 13 serving as an intermediate electrode material are respectively formed in the through holes 31 by using an isotropic film forming method such as ALD (Atomic Layer Deposition). It deposits so that the side wall surface containing the recessed part may be covered. The thickness of the deposited metal film 13 is preferably about 10 nm. A structural cross-sectional view of this state is shown in FIG.

Thereafter, the metal film 13 is etched, and the metal film 13 formed on the side wall surface (that is, the side wall surface facing the interlayer insulating film 16) excluding the concave portion of the through hole 31 is removed. This etching can be performed, for example, by plasma etching using a chlorine-based gas (Cl ₂ , BCl ₃ , CCl _4, etc.). At this time, the metal film 13 at the bottom of the through hole 31 is also removed at the same time. Thereby, the metal film 13 remains only in the recess, and the intermediate electrode (third electrode) is formed separately in the axial direction (third direction) of the through hole 31. A structural cross-sectional view of this state is shown in FIG.

  Thereafter, the bidirectional rectifying film 14 remaining at the bottom is removed, and the variable resistor material 12 is deposited so as to cover the side wall surface of the through hole 31. A sectional view of the structure in this state is shown in FIG.

  Thereafter, the variable resistor material 12 remaining at the bottom of the through hole 31 is removed by, for example, RIE (reactive ion etching), and the drain region 24 of the selection transistor 21 is exposed at the bottom of the through hole 31. Filled with the second electrode material 11 to form a columnar second electrode. Thereafter, the second electrode material deposited on the upper surface is removed until the interlayer insulating film 16 is exposed. A structural sectional view of this state is shown in FIG. This is a state in which a dummy film 32 is deposited instead of the plate electrode 15 in FIG.

  Thereafter, a processing opening 33 is formed in the portion where the dummy film 32 of the laminated structure remains at a depth penetrating the lowermost dummy film 32 in the vicinity of the through hole 31, and the opening 33 is interposed through the opening 33. Then, the dummy film 32 sandwiched between the interlayer insulating films 16 is removed. Etching with a chemical solution is used to remove the dummy film 32. A sectional view of the structure after etching is shown in FIG. FIG. 10 is a cross-sectional view in the A-A ′ direction of FIG. 9.

  FIG. 9 shows an example of an arrangement layout of the through holes 31 and the openings 33. When the minimum processing dimension of the exposure apparatus is 30 nm, the diameter of the through holes 31 is 30 nm, the distance between the through holes 31 is the direction in which the opening (here, the groove) 33 is sandwiched between the through holes 31 (X direction) ) Can be reduced to 60 nm and 30 nm in the direction in which the opening 33 is not sandwiched between the through holes 31 (Y direction). In FIG. 9, the through hole 31 is shown as a square pattern. However, if the dimension of the through hole 31 is close to the minimum processing dimension, the pattern after exposure etching is close to a circle even if the mask pattern is square. Further, in FIG. 9, as many contact plugs 37a to 37d as the number of stacked layers of the dummy films 32 are provided (see FIG. 12).

  Thereafter, the first electrode material 15 is deposited in the region from which the dummy film 32 has been removed via the opening 33, and the region from which the dummy film has been removed is filled with the first electrode material 15. Thereafter, the first electrode material 15 deposited on the side wall of the opening 33 is removed until the interlayer insulating film 16 is exposed on the side wall surface of the opening 33. After the removal, the opening 33 is filled with an insulating film. Thereby, a three-dimensional memory cell array is manufactured.

  Thereafter, by forming the peripheral circuit of the three-dimensional memory cell array, the inventive device 2 shown in FIG. 11 is manufactured. It is preferable to perform a separate forming step after the production of the device 2 of the present invention.

  In the manufacturing method of the present embodiment, the first electrode 15 is not two-dimensionally formed in a flat plate shape, and a plurality of first electrodes 15 that are separated in the Y direction by the opening 33 and extend in the X direction are formed. Each of the first electrodes 15 can be individually connected to a decoder (YZ decoder: not shown) via a metal wiring. In this case, the YZ decoder selects the position in the Y direction and the Z direction of the operation target memory cell in the three-dimensional memory cell array. At this time, the selection transistors 21 having the same position in the Y direction of the memory cells to be operated are brought into conduction via the second selection line. Similar to the first embodiment, a first decoder (not shown) selects a position in the X direction of the memory cell to be operated.

  Alternatively, the first electrodes 15 having the same position in the Z direction may be connected to the same metal wiring, and the metal wiring may be connected to a decoder (third decoder: not shown). The circuit configuration of the three-dimensional memory cell array in this case is equivalent to that in FIG. 2, and the method for selecting the memory cell to be operated in the three-dimensional memory cell array is the same as in the first embodiment.

  FIG. 12 shows an example of connection between the three-dimensional memory cell array of the device 2 of the present invention and metal wiring connected to the decoder. FIG. 12 is a structural cross-sectional view in the B-B ′ direction of FIG. 9, and shows a state of a peripheral portion connected to a peripheral circuit of the three-dimensional memory cell array of the device 2 of the present invention. The first electrode 15 is patterned stepwise so that the extending range in the Y direction becomes longer toward the lower layer, and each layer of the first electrode 15 extends in the X direction via the contact plugs 37a to 37d. It is connected to the metal wirings 38a to 38d separately. Each of the metal wirings 38a to 38d extends in the Y direction, connects the first electrodes 15 of the same layer (the same position in the Z direction) through contact plugs, and a third decoder (not shown). Connecting.

  The manufacturing method of this embodiment is the manufacturing method of the device 1 of the present invention according to the first embodiment when it is difficult to selectively etch the first electrode material to form a recess (FIG. 3B). The formation of the intermediate electrode (third electrode) 13 separated in the third direction is facilitated by depositing the interlayer insulating film 16 and a material having high etching selectivity as a dummy film to facilitate formation of the recess. Can be made easy.

  In the above embodiment, after forming the recesses (FIG. 6B), both the bidirectional rectifying film 14 and the intermediate electrode material 13 serving as the nonlinear tunnel film are covered with the side wall surface including the recesses of the through holes 31. Then, the intermediate electrode 13 formed on the side wall surface excluding the concave portion of the through hole 31 is removed, and the intermediate electrode is formed only in the concave portion in the third direction. (FIG. 7B). However, here, after forming the recesses (FIG. 6B), only the metal film 13 as the intermediate electrode material is deposited so as to cover the side wall surface including the recesses of the through holes 31, and then on the side wall surfaces excluding the recesses. The formed metal film 13 is removed, and for the bidirectional rectifying film 14, the first electrode material 15 is deposited in the region where the dummy film 32 is removed after the dummy film 32 is removed (FIG. 10). Prior to this, the bidirectional rectifying film 14 may be deposited. In this case, the structure of the three-dimensional memory cell array is substantially the same as that of the nonvolatile semiconductor memory device (see FIG. 13) according to a third embodiment described later.

<Third Embodiment>
Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention (hereinafter, appropriately referred to as “present invention device 3”) and a manufacturing method thereof will be described with reference to the drawings. A cross-sectional view of the structure of the three-dimensional memory cell array of the device 3 of the present invention is shown in FIG. 14 to 16 show schematic structural cross-sectional views in each process when manufacturing the device 3 of the present invention.

  First, the dummy film 34 and the interlayer insulating film 16 are alternately arranged on the substrate on which the selection transistors 21 are two-dimensionally arranged in the first direction (X direction) and the second direction (Y direction) which are parallel to the substrate and orthogonal to each other. By depositing, a laminated structure of the dummy film 34 and the interlayer insulating film 16 is formed. The film thickness of the interlayer insulating film 16 is preferably about 30 nm, and the film thickness of the dummy film 34 is preferably about 40 nm. After that, a plurality of through holes 31 penetrating the stacked structure are formed by etching directly above the drain region 24 of the select transistor 21 to a depth at which the drain region 24 of the select transistor 21 is exposed at the bottom of the through hole. A sectional view of the structure in this state is shown in FIG.

  In the present embodiment, the material of the dummy film 34 is polycrystalline silicon or a metal oxide such as nickel, cobalt, copper, ruthenium. These metal oxides are characterized by being easily reduced to metals in a reducing atmosphere. For polycrystalline silicon, the electrode portion can be easily formed by silicidation.

  Thereafter, a part of the dummy film 34 exposed on the side wall of the through hole 31 is changed to an intermediate electrode. A cross-sectional view of the structure in this state is shown in FIG.

  If the dummy film 34 is polycrystalline silicon, silicide can be formed on the exposed surface in a self-aligned manner using a known silicidation process. As the silicide material, a material having good compatibility with the Si process such as nickel silicide and cobalt silicide and having a large work function is preferable because the switching operation of the variable resistance element can be stably performed. On the other hand, in the case where a metal oxide film is used as the dummy film 34, the exposed surface is reduced by heat treatment in a hydrogen atmosphere and changed to a metal electrode, or oxygen vacancies in the metal oxide are not necessarily metal. Can be made conductive and used as an electrode. Note that nickel, cobalt, and copper oxides can be reduced with hydrogen at about 400 ° C. This process is performed until an intermediate electrode having a depth of about 10 nm from the exposed surface of the dummy film 34 is formed.

  Thereafter, the variable resistor material 12 is deposited so as to cover the side wall surface of the through hole 31. A sectional view of the structure in this state is shown in FIG.

  Thereafter, the variable resistor material 12 remaining at the bottom of the through hole 31 is removed by, for example, RIE (reactive ion etching), and the drain region 24 of the selection transistor 21 is exposed at the bottom of the through hole 31. Filled with the second electrode material 11 to form a columnar second electrode. Thereafter, the second electrode material deposited on the upper surface is removed until the interlayer insulating film 16 is exposed. A structural cross-sectional view of this state is shown in FIG.

  After that, a processing opening 33 (here, a groove) is formed in the vicinity of the through hole 31 at a depth that penetrates the lowermost dummy film 34 in a portion where the dummy film 34 of the laminated structure remains, The dummy film 34 sandwiched between the interlayer insulating films 16 is removed through the opening 33. Etching with a chemical solution is used to remove the dummy film 34. For the arrangement of the through holes 31 and the openings 33, for example, an arrangement layout similar to that shown in FIG. 9 can be used. At this time, the etching time is adjusted so that the metallized intermediate electrode 13 remains.

For example, when the dummy film 34 is polysilicon, the interlayer insulating film 16 is a silicon oxide film, and the intermediate electrode (metal film 13) is silicide, for example, etching with a known XeF ₂ gas or NF ₃ , SF ₆ is used. The dummy film 34 can be selectively removed by plasma etching. FIG. 16 shows a cross-sectional view of the structure after etching at this time. FIG. 16 is a cross-sectional view in the AA ′ direction of FIG.

  Thereafter, the bidirectional rectifying material 14 is deposited through the opening 33 in the region where the dummy film 34 has been removed. Thereafter, the first electrode material 15 is further deposited, and the region from which the dummy film has been removed is filled with the first electrode material 15. Thereafter, the first electrode material 15 deposited on the side wall of the opening 33 is removed until at least the bidirectional rectifying material 14 is exposed on the side wall surface of the opening 33. After the removal, the opening 33 is formed of an insulating film. Fill. Thereby, a three-dimensional memory cell array is manufactured.

  Thereafter, by forming peripheral circuits of the three-dimensional memory cell array, the inventive device 3 shown in FIG. 13 is manufactured. It is preferable to perform a separate forming step after the production of the device 3 of the present invention.

  In the manufacturing method of the device 3 of the present invention, the intermediate electrode 13 separated in the third direction in a self-aligned manner is formed through the processing opening 33 instead of forming the recess in the through hole 31 by etching. can do.

<Fourth embodiment>
Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention (hereinafter, appropriately referred to as “present invention device 4”) and a manufacturing method thereof will be described with reference to the drawings. 17 to 20 are schematic structural cross-sectional views in each step when manufacturing the device 4 of the present invention.

  First, the dummy film 35 and the interlayer insulating film 16 are alternately arranged on the substrate on which the selection transistors 21 are two-dimensionally arranged in the first direction (X direction) and the second direction (Y direction) which are parallel to the substrate and orthogonal to each other. The stacked structure of the dummy film 35 and the interlayer insulating film 16 is formed. The film thickness of the interlayer insulating film 16 is preferably about 30 nm, and the film thickness of the dummy film 35 is preferably about 60 nm. As the dummy film 35, for example, polycrystalline silicon can be used. After that, a plurality of through holes 31 penetrating the stacked structure are formed by etching directly above the drain region 24 of the select transistor 21 to a depth at which the drain region 24 of the select transistor 21 is exposed at the bottom of the through hole. A sectional view of the structure in this state is shown in FIG.

  Thereafter, the formed through hole 31 is filled with the second dummy material 36. As the dummy material 36, for example, a silicon nitride film can be used. A structural sectional view of this state is shown in FIG.

  Thereafter, a processing opening 33 (here, a groove) is formed in the vicinity of the through hole 31 at a depth that penetrates the lowermost dummy film 35 in a portion where the dummy film 35 of the stacked structure remains, The dummy film 35 sandwiched between the interlayer insulating films 16 is removed through the opening 33. Etching with a chemical solution is used to remove the dummy film 35. For the arrangement of the through holes 31 and the openings 33, for example, an arrangement layout similar to that shown in FIG. 9 can be used. As a result, the dummy material 36 is exposed on the outer peripheral side wall of the through hole 31. FIG. 18 shows a structural cross-sectional view after the etching. FIG. 18 is a cross-sectional view in the A-A ′ direction of FIG. 9.

  Thereafter, the precursor material 19 of the intermediate electrode and the bidirectional rectifying film 14 are sequentially deposited in the region where the dummy film 35 has been removed through the opening 33. The film thickness of the precursor material 19 is preferably about 10 nm, and the film thickness of the bidirectional rectifying film 14 is preferably about 1 to 5 nm. Thereafter, the first electrode material 15 is further deposited, and the region where the dummy film 35 is removed is embedded with the first electrode material 15. FIG. 19A shows a structural cross-sectional view in this state. As the precursor material 19, polycrystalline silicon or a metal oxide such as nickel, cobalt, copper, ruthenium or the like is used. These metal oxides are characterized by being easily reduced to metals in a reducing atmosphere. For polycrystalline silicon, the electrode portion can be easily formed by silicidation.

  Thereafter, the first electrode material 15 deposited on the side wall of the opening 33 is removed until the bidirectional rectifying film 14 is exposed on the side wall surface of the opening 33. Furthermore, it is preferable to remove the bidirectional rectifying film 14 and the precursor film 19 deposited on the side wall of the opening 33 until the interlayer insulating film 16 is exposed on the side wall surface of the opening 33. However, if the bidirectional rectifying film 14 and the precursor material 19 are insulating materials, it is not always necessary to remove them. After removing at least the first electrode material 15 on the side wall of the opening 33, the opening 33 is filled with an insulating film. Further, the dummy material 36 filling the through hole 31 is removed, and the precursor material 19 is exposed on the side wall surface of the through hole. A structural sectional view of this state is shown in FIG.

  Thereafter, the precursor material 19 exposed on the side wall of the through hole 31 is changed to the intermediate electrode 13. A sectional view of the structure in this state is shown in FIG.

  If the precursor material 19 is polycrystalline silicon, silicide can be formed in a self-aligned manner similar to the exposed surface using a known silicidation process. As the silicide material, a material having good compatibility with the Si process such as nickel silicide and cobalt silicide and having a large work function is preferable because the switching operation of the variable resistance element can be stably performed. On the other hand, when a metal oxide film is used as the precursor material 19, the exposed surface is reduced by heat treatment in a hydrogen atmosphere and changed to a metal electrode, or oxygen in the metal oxide is not necessarily a metal. Defects can be increased to make it conductive and used as an electrode. Note that nickel, cobalt, and copper oxides can be reduced with hydrogen at about 400 ° C. This process is performed until an intermediate electrode having a depth of about 10 nm from the exposed surface of the precursor material 19 is formed.

  Thereafter, the variable resistor material 12 is deposited so as to cover the side wall surface of the through hole 31. A structural cross-sectional view in this state is shown in FIG.

  Thereafter, the variable resistor material 12 remaining at the bottom of the through hole 31 is removed by, for example, RIE (reactive ion etching), and the drain region 24 of the selection transistor 21 is exposed at the bottom of the through hole 31. Is filled with the second electrode material 11 to form a columnar second electrode. Thereafter, the second electrode material deposited on the upper surface is removed until the interlayer insulating film 16 is exposed. Thereby, a three-dimensional memory cell array is manufactured.

  Thereafter, the peripheral circuit of the three-dimensional memory cell array is formed to manufacture the device 4 of the present invention shown in FIG. It is preferable to perform a separate forming step after the manufacture of the device 4 of the present invention.

  In the manufacturing method of the device 4 of the present invention described above, the intermediate electrode 13 separated in the third direction in a self-aligning manner can be formed through the opening 33 instead of forming the recess in the through hole 31 by etching. it can.

  As described above, according to the devices 1 to 4 of the present invention and the manufacturing method thereof, it is possible to three-dimensionally integrate memory cells having a simple structure in which a bidirectional rectifying element and a variable resistance element are integrated. The manufacturing cost of the apparatus can be greatly reduced. In the present invention, since the bidirectional rectifying element is connected to the intermediate electrode 13 formed separately in the third direction, it has a stable and uniform bidirectional rectifying characteristic. As a result, a nonvolatile semiconductor memory device that has a large capacity, is inexpensive, and has high reliability can be realized.

<Another embodiment>
Another embodiment will be described below.

  <1> In the devices 1 to 3 of the present invention shown in the first to fourth embodiments, the bidirectional rectifying film 14 in the annular memory cell 13 formed by connecting the bidirectional rectifying element and the variable resistance element in series. Is on the outer peripheral side of the variable resistor material 12, one end on the outer peripheral side of the bidirectional rectifying element is connected to the plate electrode (first electrode) 15, and one end on the inner peripheral side of the variable resistive element is the columnar electrode (second electrode). The electrode is connected to the electrode 11, but this may be reversed. That is, the bidirectional rectifying film 14 is disposed on the inner peripheral side of the variable resistor, one end on the inner peripheral side of the bidirectional rectifying element is connected to the columnar electrode (second electrode) 11, and one end of the variable resistive element is a flat plate. It is good also as a structure connected with the electrode (1st electrode) 15. FIG. In that case, in the first to fourth embodiments, the variable resistor (variable resistor material) 12 is the bidirectional rectifying film 14, and the bidirectional rectifying film 14 is the variable resistor (variable resistor material) 12. The present invention may be applied with different readings. The materials of the plate electrode (first electrode) 15 and the columnar electrode (second electrode) 11 can also be appropriately changed according to this.

<2> In the above embodiment, the vertical transistor is disposed under the through hole, and the columnar electrode (second electrode) 11 is configured to be connected to the drain of the vertical transistor. It is not limited, and it may be connected to the drain region of a conventional MOS transistor.
<3> In the first and second embodiments, after the intermediate electrode 13 is separately formed in the recess of the through hole 31 (FIGS. 4B and 7B), the bidirectional rectifying film 14 remaining at the bottom The variable resistor material 12 is deposited after removing (FIGS. 5 and 8), but the bidirectional rectifying film 14 is deposited after the variable resistor material 12 is deposited in FIG. 5 or FIG. In addition to removing the variable resistor material 12 remaining at the bottom of the through hole 31, the bidirectional rectifying film 14 also remaining at the bottom may be removed.

  <4> In the second to fourth embodiments, when the dummy film 32 (34, 35) is removed by forming the processing opening 33, the layout shown in FIG. An extending groove is formed to remove the dummy film. As a result, the first electrode 15 is separated and formed in the Y direction and is formed in a linear shape extending in the X direction. However, the present invention is not limited to the configuration shown in the above layout. For example, as shown in the layout of FIG. 22, a hole can be formed as the opening 33 for processing.

  In this case, the dummy film can be removed by adjusting the etching time so that the dummy film 32 (34, 35) is etched to the distance R from the end of the hole 33 for processing. As a result, the first electrode 15 can two-dimensionally connect the memory cells in the X direction and the Y direction, and the manufactured nonvolatile semiconductor memory device is the same as the inventive device 1 of the first embodiment. It becomes composition.

  Alternatively, in FIG. 9, instead of forming a groove extending in the X direction as the opening 33, a groove extending in the Y direction can be formed as the opening 33.

  <5> In the first to fourth embodiments, the numerical values such as the film thickness of each material film and the dimension of the opening shown in the description of the manufacturing process are merely examples, and are limited to the values exemplified in the embodiment. It is not a thing.

  INDUSTRIAL APPLICABILITY The present invention is applicable to a semiconductor memory device, and in particular, to a nonvolatile semiconductor memory device including a variable resistance element in which a resistance state transitions due to voltage application and information is held by the resistance state after the transition. Is possible.

1-4: Nonvolatile semiconductor memory device according to one embodiment of the present invention (device of the present invention)
11, 41a, 41b: Columnar electrode (second electrode)
11a: Peripheral electrode 11b: Internal electrode 12, 42: Variable resistor material (variable resistor)
13, 43: Intermediate electrode (third electrode)
14: Bidirectional rectifying film 15, 45: Flat plate electrode (first electrode)
16, 46: Interlayer insulating film 17, 47: Memory cell 18: Two-dimensional memory cell array 19: Precursor of intermediate electrode 20: Semiconductor substrate 21: Select transistor 22: Gate electrode 23: Source region 24: Drain region 25: Channel region 31: Through-hole 32, 34-36: Dummy film (dummy material)
33: Openings for processing 37a to 37d: Contact plugs 38a to 38d: Wiring layer 48: Filament

Claims (13)

A plurality of two-terminal memory cells each including a nonvolatile variable resistance element whose resistance characteristics are changed by application of a voltage in a first direction, a second direction, and a third direction orthogonal to each other, in a three-dimensional matrix shape A non-volatile semiconductor memory device having a three-dimensional memory cell array arranged in
The three-dimensional memory cell array
A first electrode extending in at least one of the first direction and the second direction, wherein the first electrode is laminated in the third direction by two or more layers through an interlayer insulating film;
A plurality of through holes penetrating in the third direction through the stacked two or more first electrodes and the interlayer insulating film therebetween, the through holes being two-dimensional in the first direction and the second direction; Arranged
A plurality of second electrodes configured by columnar conductors extending in the third direction and filling the through holes without contacting the first electrodes;
The memory cell is
An annular third electrode;
An annular variable resistor in contact with either the inner peripheral side surface or the outer peripheral side surface of the third electrode;
An annular insulating film that contacts either the inner peripheral side surface or the outer peripheral side surface of the third electrode;
The first electrode is electrically connected to an outer peripheral side surface of the variable resistor and the annular insulating film that is not in contact with the third electrode,
The second electrode is electrically connected to the inner peripheral side of the variable resistor and the annular insulating film that is not in contact with the third electrode, thereby forming an annular memory cell. Being
The third electrode is separately formed in the third direction between the memory cells connected to the same second electrode ;
The nonvolatile semiconductor memory device , wherein the variable resistor is electrically separated in the third direction between the memory cells connected to the same second electrode . The first electrode is electrically connected to an outer peripheral side surface of the annular insulating film;
The nonvolatile semiconductor memory device according to claim 1, wherein the second electrode is electrically connected to an inner peripheral side surface of the variable resistor. The variable resistor, the third electrode, and one electrode connected to the variable resistor among the first electrode and the second electrode constitutes the variable resistor element,
The annular insulating film, the third electrode, and the other electrode connected to the annular insulating film among the first electrode and the second electrode constitute a two-terminal bidirectional rectifier. The nonvolatile semiconductor memory device according to claim 1 or 2. Select transistors are arranged in a plurality of two-dimensional matrices in the first direction and the second direction, respectively, adjacent to the arrangement direction of the three-dimensional memory cells in the third direction,
Wherein the second electrode, the non-volatile semiconductor memory device according to any one of claim 1 to 3, wherein the connecting one of the input and output terminal pair of said selection transistor in its top or bottom surface . The variable resistor is a transition metal oxide or aluminum oxide, or, non-volatile semiconductor memory device according to any one of claims 1-4, characterized in that it is composed of an oxynitride of a transition metal . A method of manufacturing a nonvolatile semiconductor memory device,
In the nonvolatile semiconductor memory device, a two-terminal type memory cell having a nonvolatile variable resistance element whose resistance characteristics are changed by application of voltage includes a first direction, a second direction, and a third direction orthogonal to each other. Each having a plurality of three-dimensional memory cell arrays arranged in a three-dimensional matrix,
The three-dimensional memory cell array
A first electrode extending in at least one of the first direction and the second direction, wherein the first electrode is laminated in the third direction by two or more layers through an interlayer insulating film;
A plurality of through holes penetrating in the third direction through the stacked two or more first electrodes and the interlayer insulating film therebetween, the through holes being two-dimensional in the first direction and the second direction; Arranged
A plurality of second electrodes configured by columnar conductors extending in the third direction and filling the through holes without contacting the first electrodes;
The memory cell is
An annular third electrode;
An annular variable resistor in contact with either the inner peripheral side surface or the outer peripheral side surface of the third electrode;
An annular insulating film that contacts either the inner peripheral side surface or the outer peripheral side surface of the third electrode;
The first electrode is electrically connected to an outer peripheral side surface of the variable resistor and the annular insulating film that is not in contact with the third electrode,
The second electrode is electrically connected to the inner peripheral side of the variable resistor and the annular insulating film that is not in contact with the third electrode, thereby forming an annular memory cell. Being
The third electrode is separately formed in the third direction between the memory cells connected to the same second electrode;
Said method comprises
A step of alternately depositing a first electrode material and an interlayer insulating film on a substrate to form a laminated structure of the first electrode material and the interlayer insulating film;
Forming a plurality of through holes penetrating the laminated structure in the laminated structure so as to be two-dimensionally arranged in a first direction and a second direction parallel to the substrate surface and orthogonal to each other;
Etching and removing the first electrode material exposed on the side wall of the through hole by a predetermined thickness, and forming a recess on the side wall of the through hole;
Depositing an insulating film material to be a nonlinear tunnel film and a third electrode material so as to cover the side wall surface including the concave portion of the through hole, respectively;
Removing the third electrode material formed on the side wall surface excluding the concave portion of the through hole, and leaving the third electrode material in the concave portion of the through hole;
Depositing a variable resistor material so as to cover a side wall surface of the through hole;
Filling the through hole with a second electrode material. A method for manufacturing a nonvolatile semiconductor memory device, comprising: A method of manufacturing a nonvolatile semiconductor memory device,
In the nonvolatile semiconductor memory device, a two-terminal type memory cell having a nonvolatile variable resistance element whose resistance characteristics are changed by application of voltage includes a first direction, a second direction, and a third direction orthogonal to each other. Each having a plurality of three-dimensional memory cell arrays arranged in a three-dimensional matrix,
The three-dimensional memory cell array
A first electrode extending in at least one of the first direction and the second direction, wherein the first electrode is laminated in the third direction by two or more layers through an interlayer insulating film;
A plurality of through holes penetrating in the third direction through the stacked two or more first electrodes and the interlayer insulating film therebetween, the through holes being two-dimensional in the first direction and the second direction; Arranged
A plurality of second electrodes configured by columnar conductors extending in the third direction and filling the through holes without contacting the first electrodes;
The memory cell is
An annular third electrode;
An annular variable resistor in contact with either the inner peripheral side surface or the outer peripheral side surface of the third electrode;
An annular insulating film that contacts either the inner peripheral side surface or the outer peripheral side surface of the third electrode;
The first electrode is electrically connected to an outer peripheral side surface of the variable resistor and the annular insulating film that is not in contact with the third electrode,
The second electrode is electrically connected to the inner peripheral side of the variable resistor and the annular insulating film that is not in contact with the third electrode, thereby forming an annular memory cell. Being
The third electrode is separately formed in the third direction between the memory cells connected to the same second electrode;
Said method comprises
A step of alternately depositing dummy films and interlayer insulating films on the substrate to form a laminated structure of the dummy films and the interlayer insulating films;
Forming a plurality of through holes penetrating the laminated structure in the laminated structure so as to be two-dimensionally arranged in a first direction and a second direction parallel to the substrate surface and orthogonal to each other;
Etching the dummy film exposed on the side wall of the through hole by a predetermined thickness and forming a recess on the side wall of the through hole;
A step of sequentially depositing an insulating film material and a third electrode material to be a nonlinear tunnel film so as to cover a side wall surface including the concave portion of the through hole;
Removing the third electrode material formed on the side wall surface excluding the concave portion of the through hole, and leaving the third electrode material in the concave portion of the through hole;
Depositing a variable resistor material so as to cover a side wall surface of the through hole;
Filling the through hole with a second electrode material;
Forming an opening for processing adjacent to the through hole in a portion where the dummy film of the stacked structure remains;
Removing the dummy film sandwiched between the interlayer insulating films through the opening;
Depositing and embedding a first electrode material in the region where the dummy film has been removed;
Filling the opening with an insulating film after removing the first electrode material deposited on the side wall of the opening until the interlayer insulating film is exposed on the side wall surface of the opening. A method for manufacturing a nonvolatile semiconductor memory device. A method of manufacturing a nonvolatile semiconductor memory device,
In the nonvolatile semiconductor memory device, a two-terminal type memory cell having a nonvolatile variable resistance element whose resistance characteristics are changed by application of voltage includes a first direction, a second direction, and a third direction orthogonal to each other. Each having a plurality of three-dimensional memory cell arrays arranged in a three-dimensional matrix,
The three-dimensional memory cell array
A first electrode extending in at least one of the first direction and the second direction, wherein the first electrode is laminated in the third direction by two or more layers through an interlayer insulating film;
A plurality of through holes penetrating in the third direction through the stacked two or more first electrodes and the interlayer insulating film therebetween, the through holes being two-dimensional in the first direction and the second direction; Arranged
A plurality of second electrodes configured by columnar conductors extending in the third direction and filling the through holes without contacting the first electrodes;
The memory cell is
An annular third electrode;
An annular variable resistor in contact with either the inner peripheral side surface or the outer peripheral side surface of the third electrode;
An annular insulating film that contacts either the inner peripheral side surface or the outer peripheral side surface of the third electrode;
The first electrode is electrically connected to an outer peripheral side surface of the variable resistor and the annular insulating film that is not in contact with the third electrode,
The second electrode is electrically connected to the inner peripheral side of the variable resistor and the annular insulating film that is not in contact with the third electrode, thereby forming an annular memory cell. Being
The third electrode is separately formed in the third direction between the memory cells connected to the same second electrode;
Said method comprises
A step of alternately depositing dummy films and interlayer insulating films on the substrate to form a laminated structure of the dummy films and the interlayer insulating films;
Forming a plurality of through holes penetrating the laminated structure in the laminated structure so as to be two-dimensionally arranged in a first direction and a second direction parallel to the substrate surface and orthogonal to each other;
Etching the dummy film exposed on the side wall of the through hole by a predetermined thickness and forming a recess on the side wall of the through hole;
Depositing a third electrode material so as to cover a side wall surface including the concave portion of the through hole;
Removing the third electrode material formed on the side wall surface excluding the concave portion of the through hole, and leaving the third electrode material in the concave portion of the through hole;
Depositing a variable resistor material so as to cover a side wall surface of the through hole;
Filling the through hole with a second electrode material;
Forming an opening for processing adjacent to the through hole in a portion where the dummy film of the stacked structure remains;
Removing the dummy film sandwiched between the interlayer insulating films through the opening;
Depositing an insulating film material to be a nonlinear tunnel film and a first electrode material in order in the region from which the dummy film has been removed, and filling the region from which the dummy film has been removed with the first electrode material;
Filling the opening with an insulating film after removing the first electrode material deposited on the side wall of the opening until the insulating film material is exposed on the side wall surface of the opening. A method for manufacturing a nonvolatile semiconductor memory device. A method of manufacturing a nonvolatile semiconductor memory device,
In the nonvolatile semiconductor memory device, a two-terminal type memory cell having a nonvolatile variable resistance element whose resistance characteristics are changed by application of voltage includes a first direction, a second direction, and a third direction orthogonal to each other. Each having a plurality of three-dimensional memory cell arrays arranged in a three-dimensional matrix,
The three-dimensional memory cell array
A first electrode extending in at least one of the first direction and the second direction, wherein the first electrode is laminated in the third direction by two or more layers through an interlayer insulating film;
A plurality of through holes penetrating in the third direction through the stacked two or more first electrodes and the interlayer insulating film therebetween, the through holes being two-dimensional in the first direction and the second direction; Arranged
A plurality of second electrodes configured by columnar conductors extending in the third direction and filling the through holes without contacting the first electrodes;
The memory cell is
An annular third electrode;
An annular variable resistor in contact with either the inner peripheral side surface or the outer peripheral side surface of the third electrode;
An annular insulating film that contacts either the inner peripheral side surface or the outer peripheral side surface of the third electrode;
The first electrode is electrically connected to an outer peripheral side surface of the variable resistor and the annular insulating film that is not in contact with the third electrode,
The second electrode is electrically connected to the inner peripheral side of the variable resistor and the annular insulating film that is not in contact with the third electrode, thereby forming an annular memory cell. Being
The third electrode is separately formed in the third direction between the memory cells connected to the same second electrode;
Said method comprises
A step of alternately depositing a first dummy film and an interlayer insulating film on a substrate to form a laminated structure of the first dummy film and the interlayer insulating film;
Forming a plurality of through holes penetrating the laminated structure in the laminated structure so as to be two-dimensionally arranged in a first direction and a second direction parallel to the substrate surface and orthogonal to each other;
Filling the through hole with a second dummy film;
Forming an opening for processing in the vicinity of the through hole in a portion where the first dummy film of the stacked structure remains;
Removing the first dummy film sandwiched between the interlayer insulating films through the opening until the second dummy film is exposed;
In the region from which the first dummy film has been removed, a precursor material that is a precursor of a third electrode material, an insulating film material that becomes a nonlinear tunnel film, and a first electrode material are sequentially deposited, and the first dummy film Filling the region from which the first electrode material is removed with the first electrode material;
Filling the opening with an insulating film after removing the first electrode material deposited on the side wall of the opening until the insulating film material is exposed on the side wall surface of the opening; and
Removing the second dummy film filling the through hole;
Changing a part of the precursor material exposed on the side wall of the through hole to the third electrode material;
Depositing a variable resistor material so as to cover a side wall surface of the through hole;
Filling the through hole with a second electrode material. A method for manufacturing a nonvolatile semiconductor memory device, comprising: The precursor material is polycrystalline silicon;
The nonvolatile process according to claim 9 , wherein the step of changing a part of the precursor material to the third electrode material is a step of siliciding the polycrystalline silicon exposed on a sidewall of the through hole. For manufacturing a conductive semiconductor memory device. The precursor material is a metal oxide film of an oxidizable metal;
The step of changing a part of the precursor material to the third electrode material changes the metal oxide film exposed on the side wall of the through hole to the metal to be oxidized by reduction treatment, or is a conductive material having many oxygen vacancies. The method of manufacturing a nonvolatile semiconductor memory device according to claim 9 , wherein the method is a step of changing to a conductive film. Forming a selection transistor in a matrix on the substrate;
Said step of forming a through hole, the non-volatile semiconductor memory device according to any one of claims 7 to 11, which is a step of the source or drain region to form the through-holes exposing the selection transistor on the bottom surface Manufacturing method. A forming step of applying a voltage between the first electrode material formed between the interlayer insulating films and the second electrode material formed in the through hole;
In the forming step, the resistance state of the portion of the variable resistor material that contacts the third electrode material is reduced, and the resistance state is changed from an initial high resistance state to a variable resistance state that changes due to voltage application, The portion of the variable resistor material that has changed to the variable resistance state functions as a variable resistor, and the portion of the variable resistor material that contacts the interlayer insulating film remains in the initial high resistance state. method of manufacturing a nonvolatile semiconductor memory device according to any one of claims 7 to 12, variable resistor, characterized in that it is electrically separated form the third direction.