CN107358254A - Processor for image recognition - Google Patents
Processor for image recognition Download PDFInfo
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- CN107358254A CN107358254A CN201710460366.0A CN201710460366A CN107358254A CN 107358254 A CN107358254 A CN 107358254A CN 201710460366 A CN201710460366 A CN 201710460366A CN 107358254 A CN107358254 A CN 107358254A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention proposes a kind of processor for image recognition, and it is a kind of containing three-dimensional storage（3D‑M）The distributed mode processor of array.The processor contains multiple storage processing units, and each unit contains a mode processing circuit and an at least 3D M arrays.The 3D M arrays are stacked on above mode processing circuit, and storage image model library etc..Mode processing circuit carries out pattern-recognition according to the iconic model storehouse to the user image data of input.
Description
Technical field
The present invention relates to integrated circuit fields, more precisely, being related to the processor for image recognition.
Background technology
Pattern match and pattern-recognition refer in target pattern（The pattern being retrieved, target pattern）Middle lookup and inspection
Rope pattern（For the pattern of retrieval, search pattern）Identical or close pattern.Wherein, pattern match requirement is found
Identical pattern, pattern-recognition, which requires nothing more than, finds close pattern.Except special instruction, this specification does not differentiate between pattern match
And pattern-recognition, and it is referred to as the various operations carried out to pattern with mode treatment.
Mode treatment（Including pattern match and pattern-recognition）It is widely used.Conventional mode treatment includes character string
Match somebody with somebody, code matches, speech recognition and image recognition etc..String matching is widely used in big data analysis（As finance data analysis,
Electric quotient data analysis, bioinformatics）Deng field：From big data（It is mostly at present text database, contains target string）In
Searching character string is searched, and carries out statistical analysis.Code matches are widely used in anti-Malware（Anti-malware, such as network
Safety, computer antivirus）Deng field：Virus identifications are searched from network packet（virus signature）Or check network
Whether packet meets the network standard（network rules）, so as to determine whether network packet is safe.Speech recognition will be logical
Cross speech transducer and collect or be stored in voice signal in audio file storehouse and acoustic model repository and language model storehouse
Match somebody with somebody.Image recognition will be collected or stored to the picture signal in image file storehouse and iconic model storehouse by imaging sensor
Matching.
With the arrival in big data epoch, traditional pattern base（Including search modes storehouse and target pattern storehouse）Turn into big
Type database（TB levels are to PB levels, or even EB levels）：Search modes storehouse（Including all patterns for being used to retrieve）Data volume
It is very big, and target pattern storehouse（Including all patterns being retrieved, usually customer data base）Data volume it is then more huge.Mesh
The von Neumann frameworks that preceding computer uses can not meet requirement of the big data epoch to mode treatment.In von
In Neumann frameworks, the processor for tupe and the memory for memory module are separation：Memory（As firmly
Disk, CD, tape etc.）Memory module data are used only as, and any mode treatment can not be carried out to it；All mode treatments are all
By external processor（Such as CPU, GPU）To complete.It is well known that bandwidth is limited between the processor and memory of separation, just
All data are read in slave pattern storehouse just to take long enough, and Treatment Analysis still more is carried out to them.Therefore, to large-scale pattern
The mode treatment in storehouse needs to expend for a long time.
One typical case of mode treatment is image recognition.A kind of means of image recognition are according to iconic model storehouse pair
User images carry out pattern-recognition.Wherein, the substantial amounts of iconic model of iconic model library storage.In identification, schema processor will
User image data and the iconic model in iconic model storehouse one by one compared with, find immediate iconic model.Because tradition is schemed
As processor（Such as CPU, GPU）Number of cores is limited, the pattern-recognition depth of parallelism is relatively low, and iconic model library storage is in external memory（Such as
Hard disk）In, that image processor obtains iconic model is time-consuming longer, therefore traditional images processor efficiency when handling image recognition is low
Under.
The content of the invention
The main object of the present invention is to improve the efficiency of image recognition.
It is a further object of the present invention to provide a kind of processor that can efficiently carry out image recognition.
In order to realize these and other purpose, the present invention proposes a kind of processor for image recognition, and it is a kind of
Stored containing three-dimensional（Three-dimensional memory, referred to as 3D-M）The distributed mode processor of array：At this
Managing device can not only memory module data, moreover it is possible to implements mode treatment to it.One schema processor chip contains at multiple storages
Unit is managed, each unit contains a mode processing circuit and an at least one storage at least pattern（Including target pattern and retrieval
Pattern）3D-M arrays.The Vertical collection of 3D-M arrays and mode processing circuit brings many advantages：Because 3D-M arrays do not account for
Substrate Area, it can be integrated on mode processing circuit, and this can increase memory capacity, reduce chip area.Importantly,
It can realize that a big bandwidth is electrically connected because 3D-M arrays and mode processing circuit are in same chip and apart from close, between them
Connect.By using extensive parallel computing（It is single that each distributed mode processor chips can contain up to ten thousand storage processing
Member）, distributed mode processor large-scale pattern base can be realized quick mode handle.
Correspondingly, the present invention proposes a kind of processor (200) for image recognition, it is characterised in that contains：One transmission
The input bus (110) of an at least user image data；Semi-conductive substrate (0) and multiple storage processing unit (100aa-
100mn), the multiple storage processing unit couples with the input bus (110), and each storage processing unit (100ij) is contained
At least one three-dimensional storage (3D-M) array (170) and a mode processing circuit (180), wherein：3D-M arrays (170) heap
It is stacked in above the substrate (0), the 3D-M arrays (170) storage at least iconic model；The mode processing circuit (180) is located at
In the substrate (0), the mode processing circuit (180) carries out pattern-recognition according to the iconic model to the user image data；Institute
State 3D-M arrays (170) and the mode processing circuit (180) and pass through multiple contact access opening (1av, 3av) couplings.
Brief description of the drawings
Fig. 1 is a kind of circuit block diagram of distributed mode processor.
Fig. 2A-Fig. 2 C are the circuit block diagrams of three kinds of storage processing units；
Fig. 3 A are a kind of three-dimensional writable memories（Three-dimensional writable memory, referred to as 3D-W）And
The sectional view of storage processing unit based on 3D-W；Fig. 3 B are that a kind of three-dimensional print records reservoir（three-dimensional
Printed memory, referred to as 3D-P）And the sectional view of the storage processing unit based on 3D-P.
Fig. 4 is a kind of perspective view of storage processing unit.
Fig. 5 A- Fig. 5 C are the substrate circuitry layouts of three kinds of storage processing units.
It is noted that these accompanying drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and be convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, the letter suffix behind numeral represents same class
The different instances of structure；Identical number prefix represents same or similar structure.In this manual, "/" represent " and/
Or ".
Embodiment
Fig. 1 represents a kind of processor 200 for image recognition, and it is a kind of distributed mode processor chips.At this
Reason device 200 contains m x n storage processing units 100aa-100mn.These storage processing units 100aa-100mn is both formed in
On substrate 0.Input bus 110 couples with each storage processing unit, and output bus 120 couples with each storage processing unit.
It is noted that distributed mode processor chips 200 can contain individual storage processing unit 100aa-100mn up to ten thousand.Such quantity
Numerous storage processing unit 100aa-100mn can ensure extensive parallel computing, to realize that fast mode is handled.
Each storage processing unit 100ij stores an at least pattern containing a mode processing circuit 170 and at least one
3D-M arrays 180.Fig. 2A-Fig. 2 C are three kinds of storage processing unit 100ij circuit block diagrams.In these embodiments, a mould
Formula process circuit 180 services for the 3D-M arrays 170 of varying number.Mode processing circuit 180 in Fig. 2A is a 3D-M battle array
Row 170 service：The mode data being stored in 3D-M arrays 170 electrically connects 160 by big bandwidth（Referring to Fig. 3 A- Fig. 4）It is sent into
Mode processing circuit 180, pattern match or pattern-recognition are carried out with input pattern data 110, and produce output mode data
120.Mode processing circuit 180 in Fig. 2 B services for four storage array 170A-170D：It is stored in 3D-M arrays 170A-
Mode data in 170D electrically connects 160A-160D by big bandwidth（Referring to Fig. 3 A- Fig. 4）Mode processing circuit 180 is sent into, and
Pattern match or pattern-recognition are carried out with input pattern data 110.Mode processing circuit 180 in Fig. 2 C is eight storage arrays
170A-170D and 170W-170Z services：The mode data being stored in 3D-M arrays 170A-170D and 170W-170Z passes through big
Bandwidth electrically connects 160A-160D and 160W-160Z（Referring to Fig. 3 A- Fig. 4）It is sent into mode processing circuit 180, and and input pattern
Data 110 carry out pattern match or pattern-recognition.It is can be seen that from later Fig. 5 A- Fig. 5 C as more 3D-M arrays services
Mode processing circuit 180 has bigger area and stronger function.
Fig. 3 A- Fig. 3 B represent two kinds of typical 3D-M.Fig. 3 A are a kind of sections of the storage processing unit 100ij based on 3D-W
Figure.The information of 3D-W storages uses electrical programming typing.Common 3D-W has 3D-XPoint.Other 3D-W include memristor,
Resistance-variable storing device（RRAM）, phase transition storage（PCM）、programmable metallization cell（PMC）、
conductive bridging random-access memory （CBRAM）Deng.According to its programmable number, 3D-W is again
It is divided into three-dimensional one-time programming memory（Three-dimensional one-time-programmable memory, referred to as
3D-OTP）With three-dimensional multiple programmable memory（three-dimensional multiple-time-programmable
Memory, referred to as 3D-MTP）.As its name suggests, 3D-OTP can be programmed once, and 3D-MTP can be programmed repeatedly（Including repeating to compile
Journey）.3D-OTP technical maturities, it can memory scan pattern base（Such as virus identifications storehouse, network standard storehouse, acoustic model repository, language
Model library etc.）, the mode data in these pattern bases, which only increases, not to be changed.3D-MTP is a kind of general-purpose storage, and it can be used to
Objective model storage storehouse, such as user data（Including personal code work）Deng.
Storage processing unit 100ij based on 3D-W contains substrate circuitry layer 0K of the formation on substrate 0.Accumulation layer
16A is stacked on substrate circuitry 0K, and accumulation layer 16B is stacked on accumulation layer 16A.Substrate circuitry layer 0K contains accumulation layer
16A, 16B peripheral circuit, it includes transistor 0t and interconnection line 0M.Each accumulation layer（Such as 16A）Contain a plurality of first address
Line（Such as 2a, in the y-direction）, a plurality of second address wire（Such as 1a, in the x-direction）Member is stored with multiple 3D-W（Such as 1aa）.Accumulation layer
16A, 16B are coupled by contacting access opening 1av, 3av with substrate 0 respectively.
3D-W stores first 5aa and contains one layer of programming layer diode film 14 of film 12 and one.It can be antifuse film to program film 12
（For 3D-OTP）Or other repeatedly programming films（For 3D-MTP）.Diode film 14 has following generalized character：
Under read voltage, its resistance is smaller；When applied voltage be less than read voltage or it is in opposite direction with read voltage when, its resistance is larger.
Diode film can be P-i-N diode or metal oxide（Such as TiO2）Diode etc..
Fig. 3 B are a kind of sectional views of the storage processing unit 100ij based on 3D-P.The information of 3D-P storages is in factory
Using mode of printing typing in production process（Print record method）.These information are permanently fixed, and can not be changed after dispatching from the factory.Print record
Method can be photoetching（photo-lithography）, nano-imprint method（nano-imprint）, electron beam scanning exposure（e-
beam lithography）, DUV scan exposures, laser scanning exposure (laser programming) etc..Common 3D-P has
Three-dimensional masking film program read-only memory（3D-MPROM）, it passes through masking film program logging data by photoetching process.3D-P reading speed
Degree is faster than 3D-W, and it is adapted to the fixed pattern base of storage（Such as acoustic model repository and language model storehouse）, and realize high-performance mould
Formula processing（Such as realize natural language processing and real-time language translation）.
3D-P contains at least two storage member 5aa, 6aa.It is a kind of low-resistance storage member to store first 6aa, and storing first 5aa is
A kind of high resistant storage member.Low-resistance stores first 6aa and contains a layer diode film 14, and it is more first 6aa than low-resistance storage more that high resistant stores first 5aa
Containing one layer of high resistance film 12.As a simply example, high resistance film 12 can be layer of silicon dioxide film.The high resistance film 12 is in work
It is physically removed in skill flow at first 6aa storing using printing record method.
In Fig. 3 A- Fig. 3 B 3D-M（Including 3D-W and 3D-P）In, each accumulation layer contains multiple 3D-M arrays.3D-M battle arrays
Row are the set of all storage members that have shared at least one address wire in an accumulation layer.In a 3D-M array, institute
It is continuous to have address wire, does not share any address wire from different 3D-M arrays.On the other hand, a 3D-M chip contains more
Individual 3D-M modules.Each 3D-M modules contain all accumulation layers in 3D-M, and it pushes up accumulation layer and only contains a 3D-M array, and
Projection of the 3D-M arrays on substrate determines the border of the 3D-M modules.
Fig. 4 discloses storage processing unit 100ij structure from another angle.The heap of 3D-M arrays 170 of memory module
The top of substrate 0 is stacked in, the mode processing circuit 180 of tupe is located in substrate 0, and by 3D-M arrays 170 at least partly
Covering.Big bandwidth between 3D-M arrays 170 and mode processing circuit 180 by being formed by largely contacting access opening 1av, 3av
Communication is realized in electrical connection 160.Because contact access opening 1av, 3av are large number of（Can be with up to ten thousand）And length is very short（Micron
Level）, the bandwidth of electrical connection 160 is far above the communication bandwidth of chip chamber in chip.
The Vertical collection of 3D-M arrays 170 and mode processing circuit 180 brings many advantages：Due to 3D-M arrays 170 not
Substrate Area 0 is accounted for, it can be integrated on mode processing circuit 180, and this can increase memory capacity, reduce chip area.It is heavier
Want, because 3D-M arrays 170 and mode processing circuit 180 are in same chip 200 and apart from close, energy between them
Realize large bandwidth.By using extensive parallel computing, distributed mode processor 200 can be realized quick to large-scale pattern base
Mode treatment.
Fig. 5 A- Fig. 5 C disclose the specific implementation of three kinds of storage processing units.Fig. 5 A embodiment corresponds to Fig. 2A
Middle storage processing unit 100ij.Mode processing circuit 180 is that a 3D-M array 170 services, and it is complete by 3D-M arrays 170
Covering.In this embodiment, 3D-M arrays 170 contain four peripheral circuits, including X-decoder 15,15` and Y-decoder（Including
Reading circuit）17th, 17`, mode processing circuit 180 are located between this four peripheral circuits.In fig. 5, due to 3D-M arrays
170 above substrate circuitry 0K, not in substrate circuitry 0K, are represented by dashed line its projection on substrate 0 herein.
In the present embodiment, mode processing circuit 180 is limited between four peripheral circuits, and its area is no more than
The area of 3D-M arrays 170, therefore its area is smaller, function is limited.The embodiment is well suited to realize better simply mode treatment（Such as
String matching and code matches）.It is obvious that more complicated mode treatment（Such as speech recognition, image recognition）Need bigger
Circuit, this needs vacates bigger Substrate Area under 3D-M arrays 170, so as to the layout of mode processing circuit 180.Fig. 5 B-
Fig. 5 C, which disclose two kinds, has more large area and more powerful mode processing circuit 180.
Fig. 5 B embodiment corresponds to storage processing unit 100ij in Fig. 2 B.In this embodiment, a mode treatment electricity
Road 180 is that four 3D-M arrays 170A-170D are serviced.Each 3D-M arrays（Such as 170A）Only two peripheral circuits（As X is decoded
Device 15A and Y-decoder 17A）.Below this four 3D-M arrays 170A-170D, substrate circuitry 0K can be formed with free surface jet
One mode processing circuit 180.It is obvious that the mode processing circuit 180 in Fig. 5 B can be four times of Fig. 5 A big, it can realize compared with
Complicated mode treatment function.
Fig. 5 C embodiment corresponds to storage processing unit 100ij in Fig. 2 C.In this embodiment, a mode treatment electricity
Road 180 is that eight 3D-M arrays 170A-170D and 170W-170Z are serviced.This eight 3D-M arrays are divided into two groups of 150A, 150B.
Every group（Such as 150A）Including four 3D-M arrays（Such as 170A-170D）.In first group of 150A four 3D-M arrays 170A-170D
Lower section, substrate circuitry can form first mode process circuit component A 180A with free surface jet.Similarly, in second group of 150B
Four 3D-M arrays 170W-170Z below, substrate circuitry can also free surface jet, form second mode process circuit component B
180B.First mode process circuit component 180A and second mode process circuit component 180B forms mode processing circuit 180.
In the present embodiment, between adjacent peripheral circuit（Between such as adjacent X-decoder 15A, 15C；In adjacent Y-decoder 17A,
Between 17B；Between adjacent Y-decoder 17C, 17D）Leave gap（Such as G）, to form wiring channel 190Xa, 190Ya,
190Yb, communicated for realizing between different mode process circuit component 150A, 150B or between different mode process circuit.Very
Substantially, the mode processing circuit 180 in Fig. 5 C can be the octuple big of Fig. 5 A, and it can realize more complicated mode treatment function.
In some embodiments of the invention, mode processing circuit 180 only needs to complete partial mode processing function.Such as
Say, mode processing circuit 180 only needs to complete simple mode processing（Such as the extraction and processing of simple feature）.By the simple mode
Pattern after processing screening will further be sent to more powerful external processor by output bus 120（Such as CPU, GPU）In it is complete
Into final mode treatment.Because most of pattern in pattern base can be screened out by simple mode processing, the pattern of output only accounts for
The fraction of pattern base, this can reduce the bandwidth pressure of output bus 120.
In distributed mode processor 200, storage processing unit 100ij can use both of which processing mode ---
Class processor mode and class memory mode.For class processor mode, storage processing unit 100ij is for the external world just as one
It is individual can with the search modes storehouse that it is carried, the processor of mode treatment is carried out to external user data.Particularly, storage is handled
The unit 100ij memory scan database of 3D-M arrays 170；Storage processing unit 100ij input data 110 is user data
（Including personal code work）, these user data are generally caused in real time, such as network packet；Storage processing unit
User data 110 and search modes storehouse are carried out pattern match or pattern-recognition by 100ij.At 3D-M arrays 170 and pattern
There is big bandwidth connection 160, this mode treatment mode is stored in separation and deposited than traditional, search modes stock between reason device 180
The mode treatment mode efficiency high of reservoir.
For class memory mode, storage processing unit 100ij is for the external world as one is mainly used in storing number of users
According to and can utilize carry mode processing circuit carry out mode treatment memory.Particularly, user data is stored in for a long time
In the 3D-M arrays 170 for storing up processing unit 100ij；Storage processing unit 100ij input data 110 is search modes data；
Search modes data 110 and its user data are carried out pattern match or pattern-recognition by storage processing unit 100ij.It is noted that
Multiple distributed mode processor chips 200 using class memory mode can be packaged into storage card as flash chip
（Such as SD card, TF card）And solid state hard disc, for storing the user data of magnanimity（Such as user data archives）.Due to each distribution
Each storage processing unit 100ij in schema processor chip 200 carries a mode processing circuit 180, this pattern
Process circuit 180 only needs to handle the data that 3D-M arrays 170 store in storage processing unit 100ij.Therefore, no matter storage card
Have with the capacity of solid state hard disc much, time of its mode treatment all handles coupled close to single-mode process circuit 180
3D-M arrays 170 in time of data for storing.This big advantage is unimaginable for conventional processors.
In class memory mode, storage processing unit 100ij is the final memory device of user data.This and tradition
, processor containing in-line memory it is different：In-line memory only interim storage user data in conventional processors,
The final memory device or external memory of user data（Such as hard disk, CD, tape）.If user data stores for a long time
In conventional processors, then the conventional processors are only capable of as these data, services, and can not be other data, services.Namely
Say, a large number of users data need to use many processors.Because conventional processors are very expensive, this processing mode cost is excessively
It is high.Compare therewith, in storage processing unit 100ij proposed by the present invention, mode processing circuit 180 is integrated in 3D-M arrays
170 lower sections, the peripheral circuit with 3D-M arrays（Such as decoder）Formed simultaneously.Because 3D-M will natively form peripheral circuit,
And peripheral circuit only accounts for very little area on substrate 0（Referring to Fig. 5 A- Fig. 5 C）, most of Substrate Area can be used for rock mechanism
Process circuit 180, mode processing circuit 180 are free for 3D-M.Therefore, in distributed mode processor chips
A large amount of approximate free mode processing circuits 180 can be formed on 200, each mode processing circuit 180 is specific data（Deposit
Storage is in 3D-M arrays 170 coupled thereto）Service.
A simple introduction is done in the application with regard to distributed mode processor below.As an example, distributed mode processing
Device 200 is an anti-Malware（anti-malware）Processor, it is mainly used in network security and computer antivirus.Network is pacified
Class processor mode can be used entirely：The input data 110 of distributed mode processor 200 is network packet, 3D-M arrays 170
Network standard storehouse and virus identifications storehouse are stored, mode processing circuit 180 carries out pattern match to them.Computer antivirus can use
Class processor mode and class memory mode：For class processor mode, the user data stored in computer is as input number
Transmitted according to 110 to distributed mode processor 200,3D-M arrays 170 and store virus identifications storehouse, mode processing circuit 180 is to it
Carry out pattern match；For class memory mode, virus identifications are sent to distributed mode processor as input data 110
200, user data is stored in 3D-M arrays 170, and mode processing circuit 180 carries out pattern match to them.In class processor
In mode, 3D-M can be 3D-OTP or 3D-MTP, and it is used to store network standard storehouse and virus identifications storehouse.In class memory side
In formula, 3D-M is preferably 3D-MTP, and it stores customer data base.
As another example, distributed mode processor 200 is analyzed available for big data（Such as finance data analysis, electricity
Quotient data analysis, bioinformatics）.Big data analysis is related to unstructured data or semi-structured data.It is traditional, using pass
It is type database（relational database）Analysis method it is helpless to this.Distributed mode processor 200 can carry
Tall and big data analysis capabilities.In order to improve efficiency, preferably with class memory mode：Big data is as archives storage in 3D-M battle arrays
In row 170, the keyword for data analysis delivers to distributed mode processor 200 as input pattern data 110, at pattern
Manage circuit 180 and pattern match is carried out to them.In big data analysis, 3D-M is preferably 3D-MTP, and it is used to store number of users
According to.
Distributed mode processor 200 can be also used for speech recognition and/or image recognition., can be with identification process
Using class processor mode and class memory mode.For class processor mode, voice/view data is as defeated caused by user
Enter data 110 and deliver to distributed mode processor 200,3D-M arrays 170 store various identification model storehouses（As acoustic model repository,
Language model storehouse, iconic model storehouse etc.）, afterwards schema processor 180 be identified.To class memory mode, caused by user
Voice/view data is as archives storage, it is necessary to which the speech signal or picture signal searched are as input in 3D-M arrays 170
Data 110 deliver to distributed mode processor 200, and mode processing circuit 180 is identified and searched afterwards.In class processor side
In formula, 3D-M can be 3D-P, 3D-OTP or 3D-MTP, and it stores acoustic model repository, language model storehouse, iconic model storehouse etc..
In class memory mode, 3D-M is preferably 3D-MTP, its storaged voice/image file storehouse.
It should be appreciated that on the premise of not away from the spirit and scope of the present invention, can be to the form and details of the present invention
It is modified, this simultaneously applies the spirit of the present invention without prejudice to them.Therefore, except the spirit according to appended claims,
The present invention should not be restricted by any restrictions.
Claims (10)
1. a kind of processor (200) for image recognition, it is characterised in that contain：
The input bus (110) of an one transmission at least user image data；
Semi-conductive substrate (0) and multiple storage processing units (100aa-100mn), the multiple storage processing unit are defeated with this
Enter bus (110) coupling, each storage processing unit (100ij) contains at least one three-dimensional storage (3D-M) array (170) and one
Mode processing circuit (180), wherein：
The 3D-M arrays (170) are stacked on above the substrate (0), the 3D-M arrays (170) storage at least iconic model；
The mode processing circuit (180) is located in the substrate (0), and the mode processing circuit (180) is according to the iconic model pair
The user image data carries out pattern-recognition；
The 3D-M arrays (170) and the mode processing circuit (180) are coupled by multiple contact access openings (1av, 3av).
2. processor (200) according to claim 1, is further characterized in that：The 3D-M is three-dimensional writeable storage member
（3D-W）.
3. processor (200) according to claim 1, is further characterized in that：The 3D-M arrays are that a three-dimensional is once compiled
Journey memory（3D-OTP）Array.
4. processor (200) according to claim 1, is further characterized in that：The 3D-M arrays are a three-dimensional repeatedly volumes
Journey memory（3D-MTP）Array.
5. processor (200) according to claim 1, is further characterized in that：The 3D-M arrays be 3D-XPoint,
Memristor, resistance-variable storing device（RRAM）, phase transition storage（PCM）、programmable metallization cell
（PMC）Or conductive bridging random-access memory（CBRAM）.
6. processor (200) according to claim 1, is further characterized in that：The 3D-M arrays (170) covering is at least partly
The mode processing circuit (180).
7. processor (200) according to claim 1, is further characterized in that：The mode processing circuit (180) is by least
Two 3D-M arrays (170A, 170B) coverings.
8. processor (200) according to claim 1, is further characterized in that：The mode processing circuit (180) is by least
Four 3D-M arrays (170A-170D) coverings.
9. processor (200) according to claim 1, is further characterized in that：The mode processing circuit (180) is by least
Eight 3D-M arrays (170A-170D, 170W-170Z) coverings.
10. processor (200) according to claim 1, is further characterized in that：It is the multiple contact access opening (1av,
3av) form a big bandwidth electrical connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/984,358 US20180268235A1 (en) | 2016-03-07 | 2018-05-20 | Image-Recognition Processor |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2016101279815 | 2016-03-07 | ||
| CN201610127981 | 2016-03-07 | ||
| CN201710130887.XA CN107169404B (en) | 2016-03-07 | 2017-03-07 | Distributed mode processor with three-dimensional memory array |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN108172255A (en) * | 2018-01-15 | 2018-06-15 | 上海新储集成电路有限公司 | A kind of data-storage system |
| CN109146763A (en) * | 2017-06-19 | 2019-01-04 | 成都海存艾匹科技有限公司 | Processor for image recognition |
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| CN109145596A (en) * | 2017-06-19 | 2019-01-04 | 成都海存艾匹科技有限公司 | Enhance the processor of computer security |
| CN109148471A (en) * | 2017-06-19 | 2019-01-04 | 成都海存艾匹科技有限公司 | Have both the memory of speech identifying function |
| CN109147836A (en) * | 2017-06-19 | 2019-01-04 | 成都海存艾匹科技有限公司 | Have both the big data memory of data analysis function |
| CN109147794A (en) * | 2017-06-19 | 2019-01-04 | 成都海存艾匹科技有限公司 | Processor for speech recognition |
| CN109145683A (en) * | 2017-06-19 | 2019-01-04 | 成都海存艾匹科技有限公司 | Have both the memory of image identification function |
| CN109144401A (en) * | 2017-06-19 | 2019-01-04 | 成都海存艾匹科技有限公司 | Have both the memory of virus investigation function |
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| CN109545783A (en) * | 2017-09-22 | 2019-03-29 | 成都海存艾匹科技有限公司 | Three-dimensional computations chip containing three-dimensional memory array |
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| CN111446247A (en) | 2020-07-24 |
| CN111384052B (en) | 2022-09-27 |
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| CN111384051B (en) | 2022-09-27 |
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| CN107301222A (en) | 2017-10-27 |
| CN107301222B (en) | 2020-11-10 |
| CN111463203A (en) | 2020-07-28 |
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