CN117912505A - Memory chip, memory device and electronic device - Google Patents
Memory chip, memory device and electronic device Download PDFInfo
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- CN117912505A CN117912505A CN202211239471.9A CN202211239471A CN117912505A CN 117912505 A CN117912505 A CN 117912505A CN 202211239471 A CN202211239471 A CN 202211239471A CN 117912505 A CN117912505 A CN 117912505A
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- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
The application relates to a memory chip, a memory device and an electronic device. The memory chip comprises a plurality of memory cells, each memory cell comprises a substrate and a plurality of memory sub-cells, the memory sub-cells are arranged on the substrate in a stacked mode, each memory sub-cell comprises memory layers and insulating layers which are alternately arranged in a stacked mode, and a first electrode penetrating through the memory layers and the insulating layers, each memory layer comprises a memory part for storing data and a second electrode, the first electrode is electrically connected with the memory parts of all the memory layers of the memory sub-cells, and the first electrode and the second electrode are used for being connected with a peripheral circuit so as to control access of the data in the memory part through the peripheral circuit. The plurality of storage subunits can be of independent structures which can be manufactured independently, and the manufacturing difficulty of the storage chip is reduced.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a memory chip, a memory device, and an electronic device.
Background
With the rapid development of data storage technology, the requirements of users on the cost performance of storage are also higher and higher. The memory chip is a main medium for data storage in a computer, and the memory capacity is one of key indexes of the performance of the memory chip.
Capacity boosting of memory chips is typically achieved by optimizing the manner of operation or optimizing the memory array architecture. The number of stacked layers in the conventional memory chip is increased, so that the manufacturing difficulty is increased, the mass production is difficult, and when the negative benefit caused by the increase of the number of stacked layers is greater than the positive benefit caused by the increase of the storage density, the cost performance of the memory chip is not high.
Therefore, it is necessary to provide a novel memory chip which can meet the requirements of large memory capacity, low manufacturing difficulty and easy mass production.
Disclosure of Invention
The embodiment of the application provides a memory chip, a memory device and an electronic device. The plurality of storage subunits of the embodiment of the application are of a storage structure which can be manufactured independently, so that the manufacturing difficulty of the storage chip is reduced, and the mass production is easy.
In a first aspect, an embodiment of the present application provides a memory chip. The memory chip comprises a plurality of memory cells, each memory cell in the plurality of memory cells comprises a substrate and a plurality of memory sub-cells, the plurality of memory sub-cells are stacked on the substrate, each memory sub-cell comprises a memory layer and an insulating layer which are alternately stacked, and a first electrode penetrating through the memory layer and the insulating layer, the memory layer comprises a memory part for storing data and a second electrode, the first electrode is electrically connected with the memory parts of all the memory layers of the memory sub-cells, and the first electrode and the second electrode are used for being connected with a peripheral circuit so as to control the access of the data in the memory part through the peripheral circuit. It will be appreciated that the number of storage subunits of the present application is at least two.
In the embodiment of the application, the number of the storage layers of each storage subunit can be one, two or three, and when the number of the storage layers is at least two, the at least two storage layers are spaced and laminated on the substrate, an insulating layer is arranged between the storage layers and the substrate, and an insulating layer is arranged between two adjacent storage layers.
In order to increase the storage capacity of the memory chip, the number of layers of the memory chip is generally increased, and as the number of layers of the memory chip increases, the manufacturing process difficulty of the memory chip is increased, especially for the electrode which needs to penetrate through a plurality of memory layers, the manufacturing difficulty is greater. In the embodiment of the application, the multi-layer memory unit is divided into a plurality of memory subunits, and each memory subunit is a memory structure which is manufactured independently, so that the manufacturing process difficulty is reduced, and the mass production is easy. The multi-layer structure of the memory chip is decomposed into a plurality of memory subunits which can be manufactured independently, and the number of the layer structures of each memory subunit is smaller than the total number of the layer structures of the memory chip, so that the difficult process degree of etching the memory layer and the insulating layer is effectively reduced, and the process difficulty of depositing the electrode is reduced.
In a possible implementation manner, the first electrodes of the plurality of memory sub-units of each memory unit are not conducted with each other, and the peripheral circuit controls access of data in the plurality of memory sub-units respectively. In the embodiment of the application, the plurality of storage subunits can be independently controlled and independently access data.
In a possible implementation manner, the insulating layer exists between two adjacent storage subunits in the plurality of storage subunits. The insulating layer isolates the first electrodes of the two adjacent storage subunits, so that the first electrodes of the two adjacent storage subunits are not communicated with each other, the two adjacent storage subunits are two independent storage structures which can be manufactured independently, and the manufacturing process difficulty of the storage chip is reduced.
In a possible implementation, the first electrodes of the plurality of memory sub-units of each memory unit are conducted with each other, and the peripheral circuit controls access of the plurality of memory sub-units as a whole to data therein. In the embodiment of the application, a plurality of storage subunits can be uniformly controlled to access data.
In one possible embodiment, a buffer layer is present between the first electrode and the storage portion. The material of the buffer layer may be carbon, and the embodiment of the application does not limit the material of the buffer layer. The buffer layer can prevent the material of the first electrode and the material of the storage part from diffusing, and can increase interface contact, and the buffer layer is favorable for improving the storage performance of the storage chip.
In a possible embodiment, a gate layer is present between the first electrode and the memory portion. The gate layer may be located outside the first electrode. The gating layer plays a role of a switch and reads and writes the needed information according to the user demand.
In one possible embodiment, the storage portion is a self-venting material. The memory part can adopt a memory chip which is composed of self-gating materials and integrates gating characteristics and memory characteristics, so that a gating layer is not required to be arranged independently, and the manufacturing process is simplified.
In a possible embodiment, each memory subunit includes a hole penetrating the memory layer and the insulating layer, and the first electrode is formed in the hole. In an embodiment of the present application, after one memory subunit is fabricated, another memory subunit is fabricated on the fabricated memory subunit. Each memory subunit includes an aperture for depositing a first electrode.
In a possible implementation manner, the number of layers of the storage layer of each storage subunit is less than or equal to 32. When the number of layers of the memory layer is greater than 32, the number of layers of the memory layer is excessive, and the size of each memory subunit is thicker, which is not beneficial to the deposition of the memory part and the first electrode in terms of technology. According to the embodiment of the application, the memory chip is divided into a plurality of independent memory subunits, so that the manufacturing process difficulty of the memory chip is reduced, each memory subunit can be independently manufactured, the number of layers is small, and the manufacturing process difficulty is reduced. Multiple memory subunits may be stacked to increase the memory capacity of the memory chip.
In one possible implementation manner, the material of the storage part is one of a phase change material, an oxide, a resistive material, a ferroelectric material and a magnetic storage material. Illustratively, the phase change material may be a chalcogenide compound, and the phase change material may also be an elemental Sb (antimony), a Ge-Te (germanium-tellurium) binary compound, a Ge-Sb (germanium-antimony) binary compound, a Sb-Te (antimony-tellurium) binary compound, a Bi-Te (bismuth-tellurium) binary compound, an In-Se (indium-selenium) binary compound, a Ge-Sb-Te (germanium-antimony-tellurium) ternary compound, a Ge-Bi-Te (germanium-bismuth-tellurium) ternary compound, a Ge-Sb-Bi-Te (germanium-antimony-bismuth-tellurium) quaternary compound, or any one or more of compounds having different chemical formulas formed by doping elements. The oxide may be silicon oxide, etc., the resistive material may be binary metal oxide, bismuth telluride, hfO2 (hafnium dioxide), siO2 (silicon dioxide), etc., the ferroelectric material may be lead zirconium titanium, aluminum oxide, hfZrO (hafnium zirconium oxide), etc., and the magnetic memory material may be hexagonal ferrite, ferric fluoride, feO (iron oxide), coO (cobalt oxide), etc. The phase-change memory chip is obtained by adopting a phase-change material, the three-dimensional flash memory chip is obtained by adopting an oxide, the resistance-change memory chip is obtained by adopting a resistance-change material, the ferroelectric memory chip is obtained by adopting a ferroelectric material, the magnetic resistance memory chip is obtained by adopting a magnetic memory material, and the like. The materials of the storage parts of the different storage subunits may be the same or different.
In one possible embodiment, the storage portions of the plurality of storage subunits are different in material. Each storage subunit in the embodiment of the application is an independent storage structure, can be independently manufactured, and is convenient for depositing storage parts with different materials, so that a plurality of storage subunits are storage structures with different access mechanisms. Multiple memory subunits are stacked together to form a memory chip having multiple memory advantages. For example, the memory part of one memory subunit may use a phase change material to obtain a memory subunit with phase change memory advantage, and the memory part of the other memory subunit may use a resistance change material to obtain a memory subunit with resistance change memory advantage, which is favorable for obtaining a memory chip with good comprehensive performance, and the memory material may be flexibly configured according to requirements.
In a second aspect, the present application provides a memory device, including a peripheral circuit and a memory chip according to any one of the embodiments of the first aspect, where the peripheral circuit is configured to control access of data in the memory chip.
In a third aspect, the present application provides an electronic device, including a processor and a storage device according to any one of the embodiments of the second aspect, where the processor is configured to read data from the storage device or write data to the storage chip of the storage device.
Drawings
In order to more clearly describe the embodiments of the present invention or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present invention or the background art.
Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
FIG. 2 is a simplified schematic diagram of a memory chip according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an internal structure of a memory chip according to an embodiment of the present application;
FIG. 4 is a schematic diagram showing an internal structure of another memory chip according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a structure of a substrate and a memory subunit according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a memory subunit according to an embodiment of the present application from another perspective;
FIG. 7 is a flowchart of a memory chip fabrication according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a structure for depositing an insulating layer and a second electrode on a substrate according to an embodiment of the present application;
FIG. 9 is a schematic view of a structure for forming holes according to an embodiment of the present application;
FIG. 10 is a schematic view of a structure for forming a recess according to an embodiment of the present application;
FIG. 11 is a schematic diagram of a deposition storage portion and a first electrode according to an embodiment of the present application;
Fig. 12 is a schematic structural view of a connection portion according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
As shown in fig. 1, fig. 1 is a schematic structural diagram of an electronic device 100. The electronic device 100 may be a notebook computer, a tablet computer, a mobile phone, a wearable device, a server, a computer, or the like. In the embodiment of the present application, description is made taking an example in which the electronic apparatus 100 is a mobile phone. The electronic device 100 may comprise a processor 10 and a storage device 11, the processor 10 being arranged to read data from the storage device 11 or to write data to the storage device 11. The memory device 11 may include a peripheral circuit 12 and a memory chip 20. The peripheral circuit 12 is used to control access of data in the memory chip 20.
Fig. 1 is merely a schematic representation of the location and structure of processor 10, peripheral circuit 12, and memory chip 20, and processor 10, peripheral circuit 12, and memory chip 20 may be located in other locations of electronic device 100, as the application is not limited in this regard.
The electronic device 100 further includes one or more of a housing 101, a display screen 102, a front camera 103, and a battery 104. The display screen 102 is fixed to the housing 101, and the display screen 102 is used for displaying images, satisfying the use requirements of users. The display screen 102 may include a display layer and a touch layer covering the display layer, where the touch layer may be used for a user to perform a touch operation, and the touch layer may be a transparent glass cover plate, plastic or other material with good light transmittance. The display layer may be a liquid crystal display, or an organic light emitting diode display, or the like. The display layer may include a display region and a non-display region, the non-display region being located on one side of the display region or surrounding the periphery of the display region, wherein in some electronic devices, the non-display region may not be provided. The front camera 103 is used for taking pictures or videos, and meets the shooting requirement of the electronic device 100. A battery 104 is located inside the electronic device 100 for powering the electronic device 100. The processor 10 and the battery 104 are both located on the side of the display screen 102 where the non-display surface is located.
In some implementations, the electronic device 100 includes a rear camera (not shown in fig. 1) for taking pictures or videos. A headphone jack or the like may be provided on the housing 101 of the electronic device 100.
It should be noted that fig. 1 is a schematic diagram schematically illustrating a structure of an electronic device 100, and the structure of the electronic device 100 is not limited by the present application.
As shown in fig. 1,2 and 3, fig. 2 is a simplified schematic structure of the memory chip 20, and fig. 3 is a schematic internal structure of the memory chip 20. The memory chip 20 may include a plurality of memory cells 210, and the plurality of memory cells 210 may be understood as at least two memory cells 210, and the plurality of memory cells 210 may be arranged in an array to form the memory chip 20. Each memory cell 210 includes a substrate 21 and a plurality of memory sub-cells 22, three memory sub-cells 22 being illustrated in fig. 2 and 3. The plurality of storage subunits 22 may be understood as at least two storage subunits 22. The plurality of memory subcells 22 are sequentially stacked on the same side of the substrate 21.
Referring to fig. 3, each memory sub-unit 22 includes a memory layer 220 and an insulating layer 224 alternately stacked, and a first electrode 221 penetrating the memory layer 220 and the insulating layer 224. The memory layer 220 includes a second electrode 222 and a memory portion 223 for storing data, the first electrode 221 is electrically connected to the memory portion 223 of all the memory layers 220 of the memory subunit 22, and the first electrode 221 and the second electrode 222 are used for connecting the peripheral circuit 12 to control access of the data in the memory portion 223 through the peripheral circuit 12.
As will be appreciated, the first electrode 221 is disposed to intersect the second electrode 222, and the storage portion 223 is located at the intersection between the first electrode 221 and the second electrode 222. The crossing arrangement of the first electrode 221 and the second electrode 222 may be understood as that the first electrode 221 and the second electrode 222 are not parallel, and the first electrode 221 may be perpendicular to the second electrode 222, for example, the storage portion 223 may be located at a perpendicular crossing between the first electrode 221 and the second electrode 222. In other embodiments, the first electrode 221 and the second electrode 222 may not be perpendicular.
In the embodiment of the present application, at least one memory layer 220 and at least two insulating layers 224 are alternately stacked on the substrate 21. When the memory layer 220 is one layer, the memory layer 220 is located between two insulating layers 224. When the memory layer 220 has at least two layers, one insulating layer 224 is located between the memory layer 220 and the substrate 21, and the other insulating layers 224 are located between two adjacent memory layers 220 to insulate between the two adjacent memory layers 220. The number of the storage layers 220 may be one, two, three, four, five, etc., and the number of the layers of the storage layers 220 is not limited in the embodiment of the present application.
In order to increase the memory capacity of the memory chip 20, the number of layers of the memory chip 20 (i.e., the number of stacked memory layers 220 and the number of insulating layers 224) is generally increased, and as the number of layers of the memory chip 20 increases, the difficulty of the process for manufacturing the memory chip 20 increases. The plurality of memory subunits 22 in the embodiment of the application are a plurality of independent memory subunits which can be manufactured independently, so that the manufacturing process difficulty of the multi-layer memory chip is reduced, the deposition difficulty of the memory portion 223 is reduced, the deposition difficulty of the first electrode 221 is reduced, and the mass production is easy.
Illustratively, the memory chip 20 is exemplified by 128 layers, i.e., the memory chip 20 includes 128 memory layers 220 stacked with the substrate 21. In the prior art, it is necessary to etch a continuous hole (which is used for depositing the first electrode) capable of penetrating 128 layers by etching or the like, and also etch a recess capable of depositing the memory portion on the second electrode of each of 128 layers through the continuous hole. The continuous hole is usually a narrow and long hole, the more the number of layers the continuous hole passes through, the longer the hole size is, so that the recess capable of depositing the storage part is etched in the narrow and long hole, the first electrode is deposited in the hole, the process difficulty is increased when the storage part is deposited in the recess through the hole, and the manufacturing yield is low. The embodiment of the present application may divide the 128-layer memory chip 20 into a plurality of memory sub-units, for example, four memory sub-units, each memory sub-unit 22 may include 32 layers, the number of layers of each memory sub-unit 22 is less than the total number of layers of the memory chip 20, the length of the hole for depositing the first electrode of each memory sub-unit 22 is reduced, so that the first electrode is deposited, and the memory portion 223 is deposited in the recess. Different memory subunits 22 are manufactured independently, one memory subunit 22 is manufactured and stacked, deposited and manufactured, and the other memory subunit 22 is manufactured, so that the manufacturing difficulty of the memory chip 20 is reduced. And because of simple manufacturing process, a plurality of storage subunits 22 can be overlapped according to the requirement, so that the storage capacity of the storage chip 20 is effectively increased.
The memory chip 20 in the embodiment of the present application is divided into a plurality of memory sub-units 22, and the number of layers of each memory sub-unit 22 is smaller, so that the deposition memory portion 223 and the deposition first electrode 221 can be deposited by using existing mature technologies, without developing a new deposition process. Further, since the memory chip 20 is divided into the plurality of memory subunits 22, the number of the memory layers 220 within each memory subunit 22 is reduced, so that the path of signal transmission is short and the signal transmission speed is substantially uniform.
In some embodiments, referring to FIG. 3, the first electrodes 221 of the plurality of memory sub-cells 22 of each memory cell 210 are non-conductive to each other, and the peripheral circuit 12 controls access to data in the plurality of memory sub-cells 22, respectively. I.e. the first electrodes 221 of the plurality of memory sub-cells 22 of each memory cell 210 are electrically non-conductive and are two independent electrodes. The plurality of storage subunits 22 are a plurality of independently controllable storage structures. In the embodiment of the present application, the first electrodes 221 of the plurality of memory sub-units 22 of each memory unit 210 are not communicated with each other, so that the large-size electrodes are divided into a plurality of independent electrodes (i.e., a plurality of first electrodes 221), so that the plurality of memory sub-units 22 are a plurality of independent memory sub-units which can be independently manufactured, which is beneficial to reducing the manufacturing difficulty of the memory chip 20.
Illustratively, an insulating layer 224 is disposed between two adjacent memory subunits 22 of the plurality of memory subunits 22. So that the first electrodes 221 of the plurality of memory sub-units 22 of each memory unit 210 are insulated, i.e. not communicated with each other, the plurality of memory sub-units 22 are separated into a plurality of independent memory structures which can be manufactured independently, and the manufacturing process difficulty of the memory chip 20 is reduced.
In some embodiments, memory sub-unit 22 includes a bit line 229, bit line 229 being located on a side of first electrode 221 facing away from substrate 21 and electrically connected to first electrode 221, bit line 229 being for electrically connecting peripheral circuit 12. Illustratively, the bit line 229 and the first electrode 221 may be electrically connected through a connection portion 2290. The second electrode 222 may be a word line. The bit line 229, the connection portion 2290, and the first electrode 221 are all made of conductive material, and may be regarded as a whole, and are electrically conductive to each other.
Referring to fig. 3, in some embodiments, a distance L1 between the bit line 229 of one memory sub-cell 22 and the first electrode 221 of an adjacent memory sub-cell 22 is greater than or equal to 50nm. Illustratively, the spacing L1 between the bit line 229 of one memory sub-cell 22 and the first electrode 221 of an adjacent memory sub-cell 22 may be 60nm, 70nm, 80nm, 100nm, or the like. In the embodiment of the application, the distance between the bit line 229 of one memory sub-unit 22 and the first electrode 221 of the adjacent memory sub-unit 22 is set by limiting the distance between the bit line 229 of one memory sub-unit 22 and the first electrode 221 of the adjacent memory sub-unit 22, so that the insulation layer between the bit line 229 of one memory sub-unit 22 and the first electrode 221 of the adjacent memory sub-unit 22 is broken down and conducted after voltages are applied to the bit line 229 and the first electrode 221 of the adjacent two memory sub-units 22, and information access of the memory sub-unit 22 is affected, thereby causing information access confusion. When the pitch between the bit line 229 of one memory sub-cell 22 and the first electrode 221 of the adjacent memory sub-cell 22 is less than 50nm, the pitch between the bit line 229 of one memory sub-cell 22 and the first electrode 221 of the adjacent memory sub-cell 22 is too small, which easily results in breakdown of the structure between the bit line 229 of one memory sub-cell 22 and the first electrode 221 of the adjacent memory sub-cell 22 after voltage application. In other embodiments, the spacing between the bit line 229 of one memory sub-cell 22 and the first electrode 221 of an adjacent memory sub-cell 22 may be less than 50nm, as long as the bit line 229 of one memory sub-cell 22 and the first electrode 221 of an adjacent memory sub-cell 22 are not broken down.
In some embodiments, referring to fig. 4, fig. 4 is a schematic diagram of another memory chip 20. The first electrodes 221 of the plurality of memory sub-units 22 of each memory cell 210 are turned on to each other, and the peripheral circuit 12 controls access of the plurality of memory sub-units 22 as a whole to data therein. The plurality of storage subunits 22 are under unified control.
In some embodiments, the number of layers of storage layers 220 of storage subunits 22 remote from substrate 21 may be less than the number of layers of storage layers 220 of storage subunits 22 proximate to substrate 21. In the process of manufacturing the memory sub-units 22, there is a problem that the surface of each memory sub-unit 22 away from the substrate 21 is uneven, and a plurality of memory sub-units 22 are stacked such that the structure of the memory sub-unit 22 further away from the substrate 21 is uneven, and even if the degree of unevenness is reduced by a mechanical planarization process in the process of manufacturing, the unevenness cannot be completely eliminated. According to the embodiment of the application, the number of layers of the storage layer 220 of the storage subunit 22 far from the substrate 21 is smaller than that of the storage layer 220 of the storage subunit 22 close to the substrate 21, so that the number of layers of the storage subunit far from the substrate 21 is reduced, and the storage layer of the storage chip 20 is prevented from being mainly concentrated on the uneven storage subunit far from the substrate 21, and the performance and the structural stability of the storage chip 20 are influenced.
In some embodiments, the number of storage layers 220 of the plurality of storage subunits 22 may be sequentially reduced, or the number of layers of some storage subunits 22 may be the same, and the number of layers of some storage subunits 22 may be reduced, which may be specifically adjusted according to the requirements and performances, which is not limited in the present application.
Each memory subcell 22 includes a hole 225, the hole 225 penetrating the memory layer 220 and the insulating layer 224, and a first electrode 221 formed in the hole 225. The hole 225 may be obtained by etching on the memory layer 220 and the insulating layer 224. When the number of the memory layers 220 is plural and the number of the insulating layers 224 is plural, the holes 225 may pass through the plurality of the memory layers 220 and the plurality of the insulating layers 224.
The more layers each memory subunit 22 is, the greater the difficulty of fabrication. Illustratively, the greater the number of memory layers 220 per memory subunit 22, the greater the difficulty in etching the plurality of memory layers 220 and the plurality of insulating layers 224 to form the aperture 225 accommodating the first electrode 221, and the greater the difficulty in etching the recess 226 accommodating the memory portion 223, and the greater the difficulty in depositing the memory portion 223, the first electrode 221. In some embodiments, the number of layers of the memory layer 220 of each memory subunit 22 is less than or equal to 32, which is advantageous in avoiding an excessive number of layers of the memory layer 220 of each memory subunit 22, resulting in a thicker size of each memory subunit 22, which is technically disadvantageous in depositing the memory portion 223 and the first electrode 221.
According to the embodiment of the application, the memory chip 20 is divided into the independent plurality of memory subunits 22, so that the manufacturing process difficulty of the memory chip 20 is reduced, each memory subunit 22 can be independently manufactured, the number of layers is small, and the manufacturing process difficulty is reduced. Multiple memory subunits 22 may be stacked to increase the memory capacity of the memory chip 20. In other embodiments, the number of storage layers 220 may be greater than 32, and the number of storage layers 220 may be 64, for example.
The material of the storage portion 223 may be one of a phase change material, an oxide, a resistive material, a ferroelectric material, and a magnetic storage material. Illustratively, the phase change material may be a chalcogenide compound, and the phase change material may also be an elemental Sb (antimony), a Ge-Te (germanium-tellurium) binary compound, a Ge-Sb (germanium-antimony) binary compound, a Sb-Te (antimony-tellurium) binary compound, a Bi-Te (bismuth-tellurium) binary compound, an In-Se (indium-selenium) binary compound, a Ge-Sb-Te (germanium-antimony-tellurium) ternary compound, a Ge-Bi-Te (germanium-bismuth-tellurium) ternary compound, a Ge-Sb-Bi-Te (germanium-antimony-bismuth-tellurium) quaternary compound, or any one or more of compounds having different chemical formulas formed by doping elements. The oxide may be silicon oxide, etc., the resistive material may be binary metal oxide, bismuth telluride, hfO2 (hafnium dioxide) or SiO2 (silicon dioxide), etc., the ferroelectric material may be lead zirconium titanium, aluminum oxide, hfZrO (hafnium zirconium oxide), etc., and the magnetic memory material may be hexagonal ferrite, ferric fluoride, feO (ferric oxide) or CoO (cobalt oxide), etc., and the specific materials used in the phase change material, oxide, resistive material, ferroelectric material, magnetic memory material are not limited in the present application.
The material of the storage sections 223 of the plurality of storage subunits 22 may be the same or different. For example, a phase-change memory chip can be obtained by adopting a phase-change material, and has the advantages of non-volatility, high reading and writing speed, long service life, stable memory, low power consumption and the like; the three-dimensional flash memory chip can be obtained by adopting the oxide, and has the advantages of non-volatility, high reading and writing speed, capability of processing larger workload more quickly, small volume, durability and the like; a resistance change material resistance change memory chip can be adopted, and the resistance change memory chip has the advantages of non-volatility, low operation voltage, low power consumption, scratch resistance, and the like; the ferroelectric memory chip can be obtained by adopting a ferroelectric material, has the advantages of non-volatility, high durability, high-speed reading and writing and the like, or the magnetic memory chip can be obtained by adopting a magnetic memory material, and has the advantages of non-volatility, high capacity density and service life.
The storage portions 223 of the plurality of storage sub-units 22 may employ different storage materials to obtain the memory chip 20. The plurality of memory subunits 22 in the embodiment of the application are a plurality of independent memory structures, can be manufactured independently, and are convenient for depositing the memory parts 223 with different materials, so that the plurality of memory subunits 22 are memory structures with different access mechanisms, and the plurality of memory subunits 22 are stacked together to form the memory chip 20 with various memory advantages. Illustratively, the memory portion 223 of one memory subunit 22 may use a phase-change material to obtain a memory subunit 22 with a phase-change memory advantage, and the memory portion 223 of another memory subunit 22 may use a resistance-change material to obtain a memory subunit 22 with a resistance-change memory advantage, which is beneficial to obtaining a memory chip 20 with good comprehensive performance, and the memory material may be flexibly configured according to needs. In the embodiment of the present application, the storage sections 223 of at least two storage subunits 22 may be provided with different materials.
In some embodiments, referring to fig. 3 and 4, the memory sub-unit 22 includes a buffer layer 227, the buffer layer 227 is located at the periphery of the first electrode 221, and the buffer layer 227 is located between the first electrode 221 and the memory portion 223. The material of the buffer layer 227 may be carbon, and the buffer layer 227 may prevent diffusion of the material of the first electrode 221 and the material of the storage portion 223, and may increase interface contact, so that the provision of the buffer layer 227 is beneficial to improving storage performance.
As shown in fig. 5, fig. 5 is a schematic structural view of a substrate 21 and a memory subunit 22. Fig. 5 schematically illustrates only one storage subunit 22, and it is understood that the number of storage subunits 22 in the embodiment of the present application is at least two. The memory sub-unit 22 further includes a gate layer 228, the gate layer 228 being located between the first electrode 221 and the memory portion 223, and the gate layer 228 also being located between the buffer layer 227 and the first electrode 221. The gating layer 228 functions as a switch to read and write information according to user's needs.
In some embodiments, the memory portion 223 may employ a memory chip formed of a self-gating memory material that integrates the gating characteristics with the memory characteristics, so that a separate gating layer is not required.
As shown in fig. 6, fig. 6 is a schematic diagram of a memory sub-unit 22 from another perspective. The bit line 229 is provided with a first contact hole 2291, and the first contact hole 2291 is used for electrically connecting peripheral circuits. The first contact hole 2291 may be located at an edge of the bit line 229 to facilitate wiring to electrically connect peripheral circuits to the bit line 229. The second electrode 222 includes a second contact hole 2221, and the second contact hole 2221 may be located at an edge of the second electrode 222, the second contact hole 2221 being used to connect peripheral circuits.
The application provides a method for manufacturing a memory chip 20, as shown in fig. 7, fig. 7 is a flowchart of manufacturing the memory chip 20, and the method for manufacturing the memory chip 20 in one embodiment specifically includes the following steps:
S10, providing a substrate 21.
Referring to fig. 3, the substrate 21 may be a substrate made of polysilicon, monocrystalline silicon, sapphire, aluminum nitride or glass, the substrate 21 may be a rigid substrate or a flexible substrate, and the material of the substrate 21 is not limited and may be selected according to requirements.
S20, manufacturing a storage subunit 22 on the substrate 21.
Referring to fig. 3, the memory sub-unit 22 includes a memory layer 220 and an insulating layer 224 alternately stacked, and a first electrode 221 penetrating the memory layer 220 and the insulating layer 224, the memory layer 220 includes a memory portion 223 storing data and a second electrode 222, the first electrode 221 is electrically connected to the memory portion 223 of all the memory layers 220 of the memory sub-unit 22, and the first electrode 221 and the second electrode 222 are used for connecting to the peripheral circuit 12 to control access of data in the memory portion 223 through the peripheral circuit 12.
S30, manufacturing another storage subunit 22 on the manufactured storage subunit 22.
Referring to fig. 3, each memory sub-unit 22 includes a memory layer 220 and an insulating layer 224 which are alternately stacked, and a first electrode 221 penetrating the memory layer 220 and the insulating layer 224, the memory layer 220 includes a memory portion 223 for storing data and a second electrode 222, the first electrode 221 is electrically connected to the memory portion 223 of all the memory layers 220 of the memory sub-units 22, and the first electrode 221 and the second electrode 222 are used for connecting to the peripheral circuit 12 to control access of data in the memory portion 223 through the peripheral circuit 12.
The first electrodes 221 of the plurality of memory sub-units 22 of each memory cell 210 may be non-conductive to each other or may be non-conductive to each other, and in the embodiment of the present application, the first electrodes 221 of the plurality of memory sub-units 22 of each memory cell 210 may be non-conductive to each other.
In the embodiment of the application, one storage subunit 22 can be firstly deposited and manufactured on the substrate 21, then the other storage subunit 22 is manufactured on the manufactured one storage subunit 22, the manufacturing of the two storage subunits 22 is not affected, and the two storage subunits 22 are independently manufactured, so that the increase of the difficulty of the deposition process along with the increase of the layer number can be avoided.
A method for fabricating a storage sub-unit 22 in one embodiment specifically includes the steps of:
As shown in fig. 8, fig. 8 is a schematic structural view of depositing an insulating layer 224 and a second electrode 222 on a substrate 21. In the embodiment of the present application, the number of the second electrodes 222 is four. Insulating layers 224 and second electrodes 222 are alternately laminated on the substrate 21. The insulating layer 224 and the second electrode 222 may be deposited by chemical vapor deposition, or may be deposited by other deposition methods, which is not limited in the present application. The insulating layer 224 may be silicon dioxide, and the second electrode 222 may be tungsten or tin, however, the material of the insulating layer 224 and the second electrode 222 is not limited in the present application. An insulating layer 224 is disposed between the second electrode 222 and the substrate 21, and an insulating layer 224 is disposed between adjacent second electrodes 222.
As shown in fig. 9, fig. 9 is a schematic view of a structure in which the hole 225 is formed. In the embodiment of the present application, the insulating layer 224 and the layer structure formed by the second electrode 222 may be etched to form the hole 225. The number of holes 225 may be plural, and one of the holes 225 is exemplified in the present application. The holes 225 penetrate the multi-layered insulating layer 224 and the multi-layered second electrode 222, and a space may be provided between the holes 225 and the substrate 21, that is, the holes 225 do not penetrate the insulating layer 224 in direct contact with the substrate 21.
As shown in fig. 10, fig. 10 is a schematic view of a structure in which the concave portion 226 is formed. In an embodiment of the present application, the recess 226 may be formed by removing a portion of the second electrode 222 through an etching back process. Illustratively, a recess 226 is formed at an end of the second electrode 222 facing the aperture 225.
As shown in fig. 11, fig. 11 is a schematic structural view of the deposition storage portion 223 and the first electrode 221. The storage portion 223 is deposited in the recess 226, and the buffer layer 227, the gate layer 228, and the first electrode 221 are sequentially deposited in the hole 225, the buffer layer 227 being located outside the gate layer 228. In some embodiments, the storage portion 223 may be a self-gating storage material integrating gating characteristics and storage characteristics, or the gating layer 228 may not be provided. An insulating material is redeposited on the insulating layer 224 furthest from the substrate 21, increasing the thickness of the insulating layer 224 such that the surface of the insulating layer 224 furthest from the substrate 21 facing away from the substrate covers the first electrode 221.
As shown in fig. 12 and 5, fig. 12 is a schematic structural view of the connection portion 2290. A connection portion 2290 is formed by depositing an electrode material such as tungsten in the first via hole 31 while passing through the first via hole 31 on the uppermost insulating layer 224, and a second via hole 32 is formed while depositing an electrode material such as tungsten in the second via hole 32, thereby forming a bit line 229.
Referring to fig. 3, 5 and 8-12, the steps of fabricating one memory subunit 22 on another memory subunit 22 include: an insulating layer 224 is deposited over one completed memory subunit 22, a second electrode 222 over the insulating layer 224, multiple layers of insulating layers 224 and multiple layers of second electrodes 222 may be alternately stacked and deposited over the completed memory subunit 22. The insulating layer 224 and the second electrode 222 are subjected to etching treatment to form a hole 225 and a recess 226. The storage portion 223 is deposited in the recess 226 and the first electrode 221 is deposited in the hole 225.
The other specific steps for fabricating the memory sub-unit 22 are described with reference to fig. 3, 5 and 8-12, and are not repeated here. The plurality of memory sub-units are stacked in the above-described fabrication steps to form a multi-layered, large-memory-capacity memory chip 20.
The present application deposits the storage portion 223 in the recess 226, deposits the first electrode 221 in the hole 225, and if the number of layers of the memory layer 220 is large, the depth of the hole 225 is large, the difficulty of depositing the storage portion 223 in the recess 226 of the multi-layered memory layer 220 is increased, and the difficulty of depositing the first electrode 221 in the hole 225 having a large depth is also increased, as is the case in the entire memory chip 20, and if the memory chip 20 is not divided into a plurality of independent memory sub-units by the present application, the manufacturing difficulty is increased when a multi-layered structure is employed in order to increase the memory capacity of the memory chip 20. The multiple memory subunits in the embodiment of the application can be independently manufactured, so that the manufacturing process difficulty of the memory chip 20 is reduced and the mass production is easy on the basis of ensuring the large memory capacity.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (12)
1. The memory chip comprises a plurality of memory cells, and is characterized in that each memory cell in the plurality of memory cells comprises a substrate and a plurality of memory sub-cells, the plurality of memory sub-cells are stacked on the substrate, each memory sub-cell in the plurality of memory sub-cells comprises memory layers and insulating layers which are alternately stacked, and a first electrode penetrating through the memory layers and the insulating layers, the memory layers comprise memory parts for storing data and second electrodes, the first electrode is electrically connected with the memory parts of all the memory layers of the memory sub-cells, and the first electrode and the second electrode are used for being connected with a peripheral circuit so as to control the access of the data in the memory parts through the peripheral circuit.
2. The memory chip of claim 1, wherein the first electrodes of the plurality of memory subcells of each memory cell are non-conductive to each other, and wherein the peripheral circuitry controls access to data in the plurality of memory subcells, respectively.
3. The memory chip of claim 2, wherein the insulating layer is present between two adjacent memory sub-units of the plurality of memory sub-units.
4. The memory chip of claim 1, wherein the first electrodes of the plurality of memory sub-units of each memory cell are conductive to each other, and the peripheral circuit controls access of the plurality of memory sub-units as a whole to data therein.
5. The memory chip of any one of claims 1 to 4, wherein a buffer layer is present between the first electrode and the memory portion.
6. The memory chip of any one of claims 1 to 5, wherein a gating layer is present between the first electrode and the memory portion.
7. The memory chip of any one of claims 1 to 5, wherein the memory portion is a self-gating material.
8. The memory chip of any one of claims 1 to 5, wherein each memory subunit includes a hole through the memory layer and insulating layer, the first electrode being formed in the hole.
9. The memory chip of any one of claims 1 to 8, wherein the number of layers of the memory layer of each memory subunit is equal to or less than 32.
10. The memory chip of any one of claims 1 to 9, wherein the memory portions of the plurality of memory sub-units are of different materials.
11. A memory device comprising peripheral circuitry and the memory chip of any one of claims 1 to 10, the peripheral circuitry being for controlling access to data in the memory chip.
12. An electronic device comprising a processor and the memory device of claim 11, the processor configured to read data from the memory device or write data to the memory device memory chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211239471.9A CN117912505A (en) | 2022-10-11 | 2022-10-11 | Memory chip, memory device and electronic device |
| PCT/CN2023/110919 WO2024078102A1 (en) | 2022-10-11 | 2023-08-03 | Memory chip, memory device and electronic device |
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| CN202211239471.9A CN117912505A (en) | 2022-10-11 | 2022-10-11 | Memory chip, memory device and electronic device |
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| KR20130046700A (en) * | 2011-10-28 | 2013-05-08 | 삼성전자주식회사 | Semiconductor memory device including three-dimensionally arranged memory elements |
| JP5996324B2 (en) * | 2012-08-07 | 2016-09-21 | シャープ株式会社 | Nonvolatile semiconductor memory device and manufacturing method thereof |
| US8946023B2 (en) * | 2013-03-12 | 2015-02-03 | Sandisk Technologies Inc. | Method of making a vertical NAND device using sequential etching of multilayer stacks |
| KR20150067811A (en) * | 2013-12-09 | 2015-06-19 | 에스케이하이닉스 주식회사 | Semiconductor device and method of manufacturing the same |
| US9159426B1 (en) * | 2014-05-07 | 2015-10-13 | Sandisk Technologies Inc. | Three dimensional memory device having stacked conductive channels |
| KR102693517B1 (en) * | 2016-05-27 | 2024-08-08 | 삼성전자주식회사 | Vertical memory devices |
| WO2019237248A1 (en) * | 2018-06-12 | 2019-12-19 | Yangtze Memory Technologies Co., Ltd. | Memory device and forming method thereof |
| CN111969106A (en) * | 2020-08-17 | 2020-11-20 | 长江存储科技有限责任公司 | Phase change memory device and method of manufacturing the same |
| CN112271254B (en) * | 2020-10-27 | 2021-12-28 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
| CN113345489B (en) * | 2021-06-28 | 2023-08-08 | 长江存储科技有限责任公司 | Memory and operation method thereof |
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