CN107134464A - A kind of array base palte, its driving method and display device - Google Patents
A kind of array base palte, its driving method and display device Download PDFInfo
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- CN107134464A CN107134464A CN201710534850.3A CN201710534850A CN107134464A CN 107134464 A CN107134464 A CN 107134464A CN 201710534850 A CN201710534850 A CN 201710534850A CN 107134464 A CN107134464 A CN 107134464A
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- 239000010409 thin film Substances 0.000 description 6
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Abstract
The invention discloses a kind of array base palte, its driving method and display device, due to same one-row pixels unit one the first grid line of correspondence and second grid line and a grid line cabling, and the first switch unit connected one to one by setting with each first grid line and the second switch unit connected one to one with each second grid line, corresponding first grid line of same row pixel cell and the corresponding connection with a grid line cabling of the second grid line can be made, the first grid line and the corresponding scanning signal of the second grid line input connected by same grid line to one-row pixels unit, so as on the basis of double grid line designs are realized, reduce the quantity of original grid line cabling, improve the line width of grid line cabling, and then signal transmission delay phenomenon and reduction area occupied can drop.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte, its driving method and display device.
Background technology
At present, array base palte is frequently with double grid linear structure, to reduce the quantity of data wire.The array of double grid linear structure
Substrate, as shown in figure 1, including：Multiple pixel PX, a plurality of first grid line Gate1_m (m=1,2,3,4) and the second grid line
Gate2_m, and with the first grid line Gate1_m and the second grid line Gate2_m data wire Data_n arranged in a crossed manner (n=1,2),
Wherein, two grid lines are connected to one-row pixels, for example, in the first row pixel, odd column pixel is connected to the first grid line
Gate1_1, even column pixels are connected to the second grid line Gate2_1, and raster data model IC (Integrated Circuit, collection
Into circuit) the 100 grid line Gate1_m of grid line cabling 200 and first and the second grid line Gate1_m mono- by being arranged at frame
One correspondence connection；Two adjacent row pixels are connected to same data line Data_n, for example, first row pixel and secondary series pixel
Data wire Data_1 is connected to, the 3rd row pixel is connected to data wire Data_2 with the 4th row pixel, so as to reduce array
The quantity of data wire in substrate, and then the source drive IC in the source driving chip that is connected with data wire can be made
The quantity of (Integrated Circuit, integrated circuit) halves.
However, because the quantity of grid line cabling adds one times, therefore the more areas of grid line cabling needs carry out typesetting,
The frame area for causing grid line cabling to take is excessive so that frame becomes causes typesetting rate low greatly.And because frame area is certain,
After grid line cabling increase the line width of every grid line cabling is narrowed, so that signal transmission delay phenomenon can be brought, and then caused
The problem of pixel undercharge.
The content of the invention
The embodiment of the present invention provides a kind of array base palte, its driving method and display device, to reduce grid line cabling
Quantity, reduces the area of grid line cabling and improves line width, and then reduces signal transmission delay phenomenon and reduction area occupied.
Therefore, the invention provides a kind of array base palte, including：Multiple pixel cells, intersection and insulation that array is set
The grid line and data wire of setting；The grid line include it is a plurality of be arranged in parallel and the first grid line corresponding with every one-row pixels unit and
Second grid line, for same one-row pixels unit, odd column pixel unit connects the first grid line, even column pixels unit connection second
Grid line；Adjacent two row pixel cells connect same data line, and the data wire be arranged at odd column pixel unit and
Between even column pixels unit；The array base palte also includes：The grid line cabling set is corresponded with every row pixel cell, with
And the correspondence first switch unit and second that often row pixel cell is arranged between first grid line and second grid line is opened
Close unit；Each grid line cabling by first switch unit and the second switch unit respectively with first grid line and institute
State the connection of the second grid line.
Preferably, in above-mentioned array base palte provided in an embodiment of the present invention, the array base palte also includes：First control
Signal wire and the second control signal wire；
Each first switch unit includes：First switch transistor, wherein, the control pole of the first switch transistor
It is connected with first control signal wire, the first pole is connected with corresponding grid line cabling, the second pole and corresponding first grid line phase
Even；
Each second switch unit includes：Second switch transistor, wherein, the control pole of the second switch transistor
Be connected with second control signal wire, the first of the first pole and corresponding first switch transistor is extremely connected, the second pole with it is right
The second grid line answered is connected.
Preferably, in above-mentioned array base palte provided in an embodiment of the present invention, first control signal wire and described
Two control signal wires be arranged in parallel with the data wire respectively, and positioned at the non-display area of the array base palte.
Preferably, in above-mentioned array base palte provided in an embodiment of the present invention, each grid line cabling and each described first
Switch element and each second switch unit are respectively positioned on the non-display area of the array base palte.
Preferably, in above-mentioned array base palte provided in an embodiment of the present invention, per corresponding first grid line of one-row pixels and
Second grid line is relatively arranged on correspondence row pixel cell both sides.
Preferably, in above-mentioned array base palte provided in an embodiment of the present invention, each grid line cabling and the first grid
Line and second grid line are set with layer.
Correspondingly, the embodiment of the present invention additionally provides a kind of display device, including：Above-mentioned provided in an embodiment of the present invention
A kind of array base palte.
Preferably, in above-mentioned display device provided in an embodiment of the present invention, in addition to：It is connected with each grid line cabling
Grid drive chip and the source driving chip that is connected with the data wire.
Preferably, in above-mentioned display device provided in an embodiment of the present invention, the first control is also included in the array base palte
When signal wire and the second control signal wire processed, the source driving chip also with first control signal wire and described second
Control signal wire is connected.
Correspondingly, the embodiment of the present invention additionally provides a kind of any of the above-described kind of array base palte provided in an embodiment of the present invention
Driving method, including：
In a vertical interval, corresponding scanning signal is inputted to each grid line cabling successively；Wherein, for one
Grid line cabling, when the grid line cabling inputs corresponding scanning signal, controls the first switch being connected with the grid line cabling
Unit and second switch sequence of unit are opened, and the grid line cabling timesharing is connected with first grid line and second grid line
Connect.
The present invention has the beneficial effect that：
Array base palte provided in an embodiment of the present invention, its driving method and display device, due to same one-row pixels unit pair
First grid line and second grid line and a grid line cabling are answered, and is connected by setting to correspond with each first grid line
The first switch unit connect and the second switch unit connected one to one with each second grid line, can make same row pixel list
Corresponding first grid line of member with the second grid line is corresponding with a grid line cabling connects, i.e., by same grid line to one-row pixels list
The first grid line and the corresponding scanning signal of the second grid line input of member connection, so as to realize the basis of double grid line designs
On, reduce the quantity of original grid line cabling, improve the line width of grid line cabling, and then can drop signal transmission delay phenomenon and
Reduce area occupied.
Brief description of the drawings
Fig. 1 is the structural representation of array base palte in the prior art；
Fig. 2 is the structural representation of array base palte provided in an embodiment of the present invention；
Fig. 3 is the concrete structure schematic diagram of array base palte provided in an embodiment of the present invention；
Fig. 4 is the driver' s timing figure of the array base palte shown in Fig. 3；
Fig. 5 is the schematic diagram of the scanning signal inputted into each grid line；
Fig. 6 is the flow chart of driving method provided in an embodiment of the present invention；
Fig. 7 is the structural representation of display device provided in an embodiment of the present invention.
Embodiment
In order that the purpose of the present invention, technical scheme and advantage are clearer, below in conjunction with the accompanying drawings, to the embodiment of the present invention
The embodiment of the array base palte of offer, its driving method and display device is described in detail.It should be appreciated that following
Described preferred embodiment is merely to illustrate and explain the present invention, and is not intended to limit the present invention.And in the feelings not conflicted
Under condition, the feature in embodiment and embodiment in the application can be mutually combined.
Each shapes and sizes do not reflect the actual proportions of array base palte in accompanying drawing, and purpose is in the schematically illustrate present invention
Hold.
The embodiments of the invention provide a kind of array base palte, as shown in Fig. 2 including：Multiple pixel cells that array is set
PX, the grid line of intersection and insulation set and data wire Data_k (k be positive integer, Fig. 2 in illustrated by taking k=2 as an example)；Grid line
It is be arranged in parallel and first grid line Gate1_p corresponding with every one-row pixels unit and the second grid line Gate2_p (p=including a plurality of
1st, 2,3 ... P, P are total line number of pixel in array base palte, are illustrated by taking P=4 as an example in Fig. 2), for same one-row pixels list
Member, odd column pixel unit connects the first grid line Gate1_p, and even column pixels unit connects the second grid line Gate2_p；Adjacent
Two row pixel cells connect same data line Data_k, and data wire Data_k is arranged at odd column pixel unit and even number
Between row pixel cell；Array base palte also includes：The a plurality of grid line cabling G_p set is corresponded with every row pixel cell, with
And often row pixel cell is arranged on the first switch unit 10_ between the first grid line Gate1_p and the second grid line Gate2_p to correspondence
P and second switch unit 20_p；Each grid line cabling G_p by first switch unit 10_p and second switch unit 20_p respectively with
First grid line Gate1_p and the second grid line Gate2_p connections.
It is understood that the pixel cell in the embodiment of the present invention includes thin film transistor (TFT) and pixel electrode, wherein, often
The grid of thin film transistor (TFT) in individual pixel cell is connected with corresponding first grid line or the second grid line, the source electrode of thin film transistor (TFT)
It is connected with corresponding data wire, the drain electrode of thin film transistor (TFT) is connected with the pixel electrode in current pixel unit.
Above-mentioned array base palte provided in an embodiment of the present invention, due to same one-row pixels unit correspondence one the first grid line and one
The grid line of bar second and a grid line cabling, and by set the first switch unit connected one to one with each first grid line with
And the second switch unit connected one to one with each second grid line, can make corresponding first grid line of same row pixel cell with
The connection corresponding with a grid line cabling of second grid line, i.e., the first grid line connected by same grid line to one-row pixels unit with
Second grid line inputs corresponding scanning signal, so as on the basis of double grid line designs are realized, reduce original grid line and walk
The quantity of line, improves the line width of grid line cabling, and then can drop signal transmission delay phenomenon and reduction area occupied.Specific
During implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in Fig. 2 one-row pixels unit correspondence one first
An a grid line Gate1_p and second grid line Gate2_p and grid line cabling G_p, these grid line cablings G_p are additionally operable to connection
Grid drive chip (i.e. Gate IC), accordingly it is also possible to the quantity of Gate IC cascade circuits is reduced half, so as to
Reduce Gate IC area occupied.Also, in actual applications, grid line cabling is usually non-display area first with array base palte
Connection terminal electrical connection in domain, then connection terminal is electrically connected with Gate IC again, to realize grid line cabling and Gate IC electricity
Connection.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in Fig. 2 per one-row pixels
Corresponding first grid line Gate1_p and the second grid line Gate2_p are relatively arranged on correspondence row pixel cell both sides.Certainly, it is each
Corresponding first grid line of row pixel and the second grid line can also be arranged on the upside or downside of correspondence row pixel cell simultaneously, herein
It is not construed as limiting.
, in the specific implementation, can be with above-mentioned array base palte provided in an embodiment of the present invention in order to simplify preparation technology
Make each grid line cabling with layer same material.The figure of each grid line cabling can be so formed by a patterning processes, simplifies and prepares
Technique, saves production cost.
Further, in the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, each grid line can be made
Cabling is set with each first grid line and each second grid line with layer.And it is further possible to make each grid line cabling and each the
One grid line and each second grid line same material.The extra technique for making grid line cabling can be so increased without, it is only necessary in system
Change original composition figure when forming the first grid line and the second grid line when making array base palte, you can pass through a patterning processes
The figure of grid line cabling and the first grid line and the second grid line is formed, preparation technology can be simplified, production cost is saved.Certainly,
Each grid line cabling can also be set with other film layers with layer, be not limited thereto.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, each first switch unit and each the
Two switch elements can be located at viewing area, or can also be located at non-display area, be not limited thereto.
In order to improve the area of viewing area, in the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention
In, each grid line cabling is respectively positioned on the non-display area of array base palte with each first switch unit and each second switch unit.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in figure 3, array base palte is also
It can include：First control signal wire 30 and the second control signal wire 40；
Each first switch unit 10_p can specifically include：First switch transistor M1, wherein, first switch transistor M1
Control pole be connected with the first control signal wire 30, the first pole and corresponding grid line cabling G_p are connected, the second pole and corresponding the
One grid line Gate1_p is connected；
Each second switch unit 20_p can specifically include：Second switch transistor M2, wherein, second switch transistor M2
Control pole be connected with the second control signal wire 40, the first of the first pole and corresponding first switch transistor M1 is extremely connected, the
Two poles are connected with corresponding second grid line Gate2_p.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in figure 3, first switch is brilliant
Body pipe M1 can be N-type transistor.Certainly, first switch transistor can also be P-type transistor, be not limited thereto.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in figure 3, second switch is brilliant
Body pipe M2 can be N-type transistor.Certainly, second switch transistor can also be P-type transistor, be not limited thereto.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, the conducting of N-type transistor high level,
Low level is ended；P-type transistor high level ends, low level conducting.
It should be noted that the switching transistor mentioned in the above embodiment of the present invention can be thin film transistor (TFT) (TFT,
Thin Film Transistor) or metal oxide semiconductor field effect tube (MOS, Metal Oxide
Scmiconductor), it is not limited thereto.In specific implementation, control extremely its grid of these transistors, according to crystal
The difference of the type of pipe and the signal of input, using the first pole as its source electrode or drain electrode, regard the second pole as its drain electrode or source
Pole.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in figure 3, the first control letter
Number line 30 can be arranged in parallel with data wire Data_k, and positioned at the non-display area of array base palte.Certainly, the first control signal
Line can not also be arranged in parallel with data wire Data_k, be not limited thereto.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in figure 3, the second control letter
Number line 40 can be arranged in parallel with data wire Data_k, and positioned at the non-display area of array base palte.Certainly, the second control signal
Line can not also be arranged in parallel with data wire Data_k, be not limited thereto.
It is preferred that in order to unify technique, in the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention,
As shown in figure 3, the first control signal wire 30 and the second control signal wire 40 be arranged in parallel with data wire Data_k, and positioned at battle array
The non-display area of row substrate.
Below by taking the structure of the array base palte shown in Fig. 3 as an example, the driver' s timing figure with reference to shown in Fig. 4 is implemented to the present invention
The driving process for the above-mentioned array base palte that example is provided is described.In Fig. 4, to input scanning signal g_1 to grid line cabling G_1
Exemplified by, scanning signal g_1 includes high level stage T0.Wherein, g_1 represents Gate IC input grid line cablings G_1 scanning letter
Number, gate1_1 represents the signal of the first grid line Gate1_1 receptions, and gate2_1 represents the signal of the second grid line Gate2_1 receptions,
CS1 represents the control signal on the first control signal wire 30, and CS2 represents the control signal on the second control signal wire 40.Control
Signal CS1 and control signal CS2 can be cycle phase with, opposite in phase and dutycycle be 50% clock signal.Due to control
Signal CS1 processed and control signal CS2 effect make the scanning signal g_1 high level stage T0 T01 that to be divided into the cycle equal
With two stages of T02.
In the T1 stages, because the control signal CS1 on the first control signal wire 30 is high level, the second control signal wire 40
On control signal CS2 be low level, therefore first switch unit 10_1 in first switch transistor M1 conducting, second switch
Second switch transistor M2 cut-offs in unit 20_1.Because the first switch transistor M1 in first switch unit 10_1 is led
It is logical, and scanning signal g_1 high level signal is supplied to the first grid line Gate1_1, therefore the first grid line Gate1_1 receives high
The signal of level.Therefore, each pixel cell of the first grid line Gate1_1 connections is opened to be charged, and the second grid line
Each pixel cell of Gate2_1 connections, which is closed, stops charging.
In the T2 stages, because the control signal CS1 on the first control signal wire 30 is low level, the second control signal wire 40
On control signal CS2 be high level, therefore first switch unit 10_1 in first switch transistor M1 cut-off, second switch
Second switch transistor M2 conductings in unit 20_1.Because the second switch transistor M2 in second switch unit 20_1 is led
It is logical, and scanning signal g_1 high level signal is supplied to the second grid line Gate2_1, therefore the second grid line Gate2_1 receives high
The signal of level.Therefore, each pixel cell of the second grid line Gate2_1 connections is opened to be charged, and the first grid line
Each pixel cell of Gate1_1 connections, which is closed, stops charging.
In other stages in addition to T1 and T2, for every one-row pixels unit, although first switch transistor M1 and
Timesharing is turned on two switching transistor M2 under control signal CS1 and control signal CS2 control respectively, but only can be respectively to first
Grid line Gate1_1 and the second grid line Gate2_1 output low level signals.
Also, as shown in figure 5, to correspondence the first row pixel cell grid line cabling G_1 input scanning signal g_1 when,
The signal that first grid line Gate1_1 of correspondence the first row pixel cell is received is gate1_1, and the second grid line Gate2_1 is received
The signal arrived is gate2_1.Similarly, when the grid line cabling G_2 to the second row pixel cell of correspondence inputs scanning signal g_2,
The signal that first grid line Gate1_2 of the second row pixel cell of correspondence is received is gate1_2, and the second grid line Gate2_2 is received
The signal arrived is gate2_2.When the grid line cabling G_3 to correspondence the third line pixel cell inputs scanning signal g_3, correspondence the
The signal that first grid line Gate1_3 of three row pixel cells is received is gate1_3, the letter that the second grid line Gate2_3 is received
Number be gate2_3.
In addition, corresponding to correspondence fourth line pixel cell, the corresponding grid line cabling input of fifth line pixel cell ...
During scanning signal, it drives process and the above-mentioned course of work essentially identical, is not described in detail here.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of above-mentioned provided in an embodiment of the present invention of driving
A kind of driving method of array base palte, as shown in fig. 6, this method can specifically include：
S601, in a vertical interval, successively to each grid line cabling input scanning signal；Wherein, for a grid line
Cabling, when grid line cabling inputs corresponding scanning signal, controls the first switch unit and second being connected with grid line cabling to open
Close sequence of unit to open, the timesharing of grid line cabling is connected with the first grid line and the second grid line.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, including the embodiment of the present invention is carried
Any of the above-described kind of array base palte supplied.The principle that the display device solves problem is similar to aforementioned array substrate, therefore the display
The implementation of device may refer to the implementation of aforementioned array substrate, repeats part and will not be repeated here.
In the specific implementation, in above-mentioned display device provided in an embodiment of the present invention, as shown in fig. 7, can also include：
The source driving chip 60 being connected with each grid line cabling G_p grid drive chips 50 being connected and with data wire Data_k.Should
Grid drive chip 50 is used to sequentially input corresponding scanning signal to each grid line cabling G_p of connection.The source driving chip
60 are used to input corresponding data-signal to the data wire Data_k of connection.The work of grid drive chip and source driving chip
Process and the course of work of the prior art are essentially identical, it will be apparent to an ordinarily skilled person in the art that having, herein
Do not repeat, also should not be taken as limiting the invention.
In the specific implementation, in above-mentioned display device provided in an embodiment of the present invention, as shown in fig. 7, in array base palte
Also include the first control signal wire 30 and the second control signal wire 40 when, source driving chip 60 also with the first control signal wire 30
And second control signal wire 40 connect.So can be using source driving chip 60 come to the first control signal wire 30 and second
Control signal wire 40 inputs corresponding control signal, simplifies preparation technology.
In the specific implementation, above-mentioned display device provided in an embodiment of the present invention can be：Mobile phone, tablet personal computer, TV
Any product or part for receiving display function such as machine, display, notebook computer, DPF, navigator.For the display
Other essential parts of device are it will be apparent to an ordinarily skilled person in the art that have, not do superfluous herein
State, also should not be taken as limiting the invention.
Array base palte provided in an embodiment of the present invention, its driving method and display device, due to same one-row pixels unit pair
First grid line and second grid line and a grid line cabling are answered, and is connected by setting to correspond with each first grid line
The first switch unit connect and the second switch unit connected one to one with each second grid line, can make same row pixel list
Corresponding first grid line of member with the second grid line is corresponding with a grid line cabling connects, i.e., by same grid line to one-row pixels list
The first grid line and the corresponding scanning signal of the second grid line input of member connection, so as to realize the basis of double grid line designs
On, reduce the quantity of original grid line cabling, improve the line width of grid line cabling, and then can drop signal transmission delay phenomenon and
Reduce area occupied.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (10)
1. a kind of array base palte, including：The grid line and data wire of multiple pixel cells, intersection and insulation set that array is set；
The grid line be arranged in parallel and the first grid line corresponding with every one-row pixels unit and the second grid line including a plurality of, for same a line
Pixel cell, odd column pixel unit connects the first grid line, and even column pixels unit connects the second grid line；Two adjacent row pixels
Unit connects same data line, and the data wire is arranged between odd column pixel unit and even column pixels unit；
Characterized in that, the array base palte also includes：The grid line cabling set is corresponded with every row pixel cell, and it is correspondingly every
Row pixel cell is arranged on first switch unit and second switch unit between first grid line and second grid line；Respectively
The grid line cabling by first switch unit and the second switch unit respectively with first grid line and the second gate
Line is connected.
2. array base palte as claimed in claim 1, it is characterised in that the array base palte also includes：First control signal wire
With the second control signal wire；
Each first switch unit includes：First switch transistor, wherein, the control pole of the first switch transistor and institute
State the first control signal wire to be connected, the first pole is connected with corresponding grid line cabling, the second pole is connected with corresponding first grid line；
Each second switch unit includes：Second switch transistor, wherein, the control pole of the second switch transistor and institute
State the second control signal wire to be connected, the first of the first pole and corresponding first switch transistor is extremely connected, the second pole with it is corresponding
Second grid line is connected.
3. array base palte as claimed in claim 2, it is characterised in that first control signal wire and the second control letter
Number line be arranged in parallel with the data wire respectively, and positioned at the non-display area of the array base palte.
4. the array base palte as described in claim any one of 1-3, it is characterised in that each grid line cabling and each described first
Switch element and each second switch unit are respectively positioned on the non-display area of the array base palte.
5. the array base palte as described in claim any one of 1-3, it is characterised in that per corresponding first grid line of one-row pixels and
Second grid line is relatively arranged on correspondence row pixel cell both sides.
6. the array base palte as described in claim any one of 1-3, it is characterised in that each grid line cabling and the first grid
Line and second grid line are set with layer.
7. a kind of display device, it is characterised in that including：Array base palte as described in claim any one of 1-6.
8. display device as claimed in claim 7, it is characterised in that also include：The grid being connected with each grid line cabling
Driving chip and the source driving chip being connected with the data wire.
9. display device as claimed in claim 8, it is characterised in that also include the first control signal wire in the array base palte
During with the second control signal wire, the source driving chip also with first control signal wire and second control signal
Line is connected.
10. a kind of driving method of array base palte as described in claim any one of 1-6, it is characterised in that including：
In a vertical interval, scanning signal is inputted to each grid line cabling successively；Wherein, for a grid line cabling,
When the grid line cabling inputs corresponding scanning signal, the first switch unit and second being connected with the grid line cabling is controlled
Switch element order is opened, and the grid line cabling timesharing is connected with first grid line and second grid line.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710534850.3A CN107134464A (en) | 2017-07-03 | 2017-07-03 | A kind of array base palte, its driving method and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710534850.3A CN107134464A (en) | 2017-07-03 | 2017-07-03 | A kind of array base palte, its driving method and display device |
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Application publication date: 20170905 |