CN104252079A - Array substrate, driving method thereof, display panel and display device - Google Patents
Array substrate, driving method thereof, display panel and display device Download PDFInfo
- Publication number
- CN104252079A CN104252079A CN201410510675.0A CN201410510675A CN104252079A CN 104252079 A CN104252079 A CN 104252079A CN 201410510675 A CN201410510675 A CN 201410510675A CN 104252079 A CN104252079 A CN 104252079A
- Authority
- CN
- China
- Prior art keywords
- driving circuit
- grid driving
- drive signal
- gate line
- array base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses an array substrate, a driving method thereof, a display panel and a display device. By the array substrate, power consumption on a source driving integrated circuit is reduced when point overturning is realized. All gate driving sub-circuits which are connected with odd-numbered rows of gate lines in the array substrate are connected to one another in a cascading manner to form a first gate driving circuit; all gate driving sub-circuits connected with even-numbered rows of gate lines are connected to one another in a cascading manner to form a second gate driving circuit; in a half displaying period displayed by a frame of an image, the odd-numbered rows of gate lines receive gate driving signals outputted by the first gate driving circuit, and the data lines receive first source driving signals outputted by the source driving integrated circuit; in the other half displaying period displayed by the frame of the image, the even-numbered rows of gate lines receive gate driving signals outputted by the second gate driving circuit, and the data lines receive second source driving signals outputted by the source driving integrated circuit; and the polarity of the first source driving signals is opposite to that of the second source driving signals.
Description
Technical field
The present invention relates to display technology field, particularly relate to a kind of array base palte and driving method, display panel, display device.
Background technology
Prior art LCDs (Liquid Crystal Display, LCD) comprise one and be dispersed with multiple thin film transistor (TFT) (Thin Film Transistor, TFT) array base palte, on array base palte, the drain electrode correspondence of a TFT connects pixel (pixel) electrode, the source electrode correspondence of TFT connects data (Data) line, and the grid correspondence of TFT connects grid (Gate) line.Array base palte row cutting (Gate Driver On Array, GOA) technology is integrated on array base palte by the thin film transistor (TFT) as gate switch circuit, thus save grid-driving integrated circuit part.In array base palte, every a line Gate line is all corresponding connects a GOA circuit, under the control of time schedule controller, the unlatching of the grid of the TFT that GOA control circui is connected with Gate line or closedown, when the grid of TFT is opened, source electrode drive circuit (Source Driver IC) drives Data line to export corresponding drive singal.
The structural representation of prior art array base palte as shown in Figure 1, every a line Gate line is all corresponding connects a GOA circuit, by triggering the switch controlling every one-row pixels between each GOA circuit successively, the input end of the GOA circuit GOA2 that the output terminal of the GOA circuit GOA1 connected as: the first row Gate line is connected with the second row Gate line connects, the input end of the GOA circuit GOA3 that the output terminal of GOA circuit GOA2 that the second row Gate line connects is connected with the third line Gate line connects, the input end of the GOA circuit GOA4 that the output terminal of GOA circuit GOA3 that the third line Gate line connects is connected with fourth line Gate line connects, namely the Gate line in GOA circuit array substrate drives line by line.When upset (dot inversion) will be realized, the signal of Data line input constantly will carry out the conversion of positive-negative polarity, namely under same image often after a Gate line sweep time, the polarity of the drive singal that every bar Data line is contained will overturn once, such as in order to realize a upset, suppose that the polarity of the data-signal in the pixel of the first row first row is just, the polarity of the data-signal that the pixel of the second row first row is corresponding will be negative, therefore when GOA circuit is from when driving the Gate line of the first row to transfer the Gate line of driving second row to, polarity on first Data line will be negative from just becoming.The conversion that the signal that this Data line inputs constantly carries out positive-negative polarity can consume a large amount of energy, and easily makes the temperature of source electrode driven integrated circuit on display panels raise.
In order to solve the problem, prior art adopts a kind of new array base-plate structure, as shown in Figure 2, G1, G2, G3 and G4 represents Article 1 Gate line respectively, Article 2 Gate line, the drive singal of Article 3 Gate line and the input of Article 4 Gate line, under this configuration, the signal of Data line input does not need the conversion carrying out positive-negative polarity, namely in the process of a two field picture display, the polarity of the signal of Data line input is changeless, polarity as the signal of Data1 input is just, the polarity of the signal of Data2 input is negative, the polarity of the signal of Data3 input is just, the polarity of the signal of Data4 input is negative.Because this structure needs both sides TFT being produced in a row pixel electrode, the cost of manufacture therefore in actual fabrication process is comparatively large, and technique is more complicated.
For double-gate structure, in order to reduce the power consumption of source electrode driven integrated circuit, namely the positive-negative polarity of the signal of Data line input does not change, adopt the dot structure shown in Fig. 3, when Gate line adopts the progressive scan mode described in Fig. 1 and Fig. 2, polarity with adjacent two pixel cells of a line is identical, and the pixel namely in the some upset that realizes of this situation overturns with two adjacent pixels, can not realize putting upset as in Figure 1 and Figure 2.
In sum, prior art constantly carries out the conversion realization point upset of positive-negative polarity during by the signal that Data line inputs, the power consumption of source electrode driven integrated circuit can be caused excessive, cause the temperature of integrated circuit in it to raise; When realizing some upset by the structure of new array base palte, production cost is higher, and technique is more complicated.
Summary of the invention
Embodiments providing a kind of array base palte and driving method, display panel, display device, in order to when realizing some upset, reducing the power consumption of source electrode driven integrated circuit.
A kind of array base palte that the embodiment of the present invention provides, comprises the pixel cell of some arrayed, wherein,
Each odd-numbered line gate line is all corresponding connects a raster data model electronic circuit, and all raster data model electronic circuit cascades be connected with odd-numbered line gate line connect to form first grid driving circuit;
Each even number line gate line is all corresponding connects a raster data model electronic circuit, and all raster data model electronic circuit cascades be connected with even number line gate line connect to form second grid driving circuit;
Within half display cycle of a two field picture display, odd-numbered line gate line receives the gate drive signal that described first grid driving circuit exports, each data line receives the first source drive signal that source electrode driven integrated circuit exports, and the polarity of the described first source drive signal that adjacent two data lines receive is contrary;
Within another half display cycle of a two field picture display, even number line gate line receives the gate drive signal that described second grid driving circuit exports, each data line receives the second source drive signal that source electrode driven integrated circuit exports, and the polarity of the described second source drive signal that adjacent two data lines receive is contrary;
Wherein, described first source drive signal is contrary with the polarity of described second source drive signal.
The array base palte provided by the embodiment of the present invention, due within half display cycle of a two field picture display, odd-numbered line gate line receives the gate drive signal that described first grid driving circuit exports, each data line receives the first source drive signal that source electrode driven integrated circuit exports, within another half display cycle of a two field picture display, even number line gate line receives the gate drive signal that described second grid driving circuit exports, each data line receives the second source drive signal that source electrode driven integrated circuit exports, and the first source drive signal is contrary with the polarity of the second source drive signal, therefore, the point upset of pixel can be realized when this two field picture shows, the polarity of the source drive signal of source electrode driven integrated circuit output simultaneously does not need constantly to change, only need change once within half display cycle, can while the upset of realization point, reduce the power consumption of source electrode driven integrated circuit, do not need to increase production cost simultaneously yet.
Preferably, described first grid driving circuit and described second grid driving circuit are positioned at the same side of array base palte; Or
Described first grid driving circuit and described second grid driving circuit lay respectively at the heteropleural of array base palte.
Like this, convenient in actual fabrication process, simple by such design.
Preferably, when the scanning trigger pip for triggering described first grid driving circuit or second grid driving circuit output gate drive signal is one,
Described first grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, described second grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, or, described first grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, described second grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, be connected with the first order raster data model electronic circuit of described first grid driving circuit for triggering the described first grid driving circuit output scanning trigger pip of gate drive signal, the afterbody raster data model electronic circuit of described first grid driving circuit is connected with the first order raster data model electronic circuit of described second grid driving circuit, or,
Described second grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, described first grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, or, described second grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, described first grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, be connected with the first order raster data model electronic circuit of described second grid driving circuit for triggering the described second grid driving circuit output scanning trigger pip of gate drive signal, the afterbody raster data model electronic circuit of described second grid driving circuit is connected with the first order raster data model electronic circuit of described first grid driving circuit,
When the scanning trigger pip for triggering described first grid driving circuit or second grid driving circuit output gate drive signal is two,
Described first grid driving circuit, according to gate line concatenated in order from top to bottom or from top to bottom corresponding to array base palte, exports the scanning trigger pip of gate drive signal be connected with the first order raster data model electronic circuit of described first grid driving circuit for triggering described first grid driving circuit;
Described second grid driving circuit, according to gate line concatenated in order from top to bottom or from top to bottom corresponding to array base palte, exports the scanning trigger pip of gate drive signal be connected with the first order raster data model electronic circuit of described second grid driving circuit for triggering described second grid driving circuit.
Like this, first grid driving circuit and second grid driving circuit are by annexation above, convenient in real work, simple.
The embodiment of the present invention additionally provides a kind of display panel, and this display panel comprises above-mentioned array base palte.
The display panel provided due to the embodiment of the present invention comprises above-mentioned array base palte, and therefore the power consumption of this display panel can reduce equally.
The embodiment of the present invention additionally provides a kind of display device, and this device comprises above-mentioned display panel.
The display device provided due to the embodiment of the present invention comprises above-mentioned display panel, and therefore the power consumption of this display device can reduce equally.
The embodiment of the present invention additionally provides a kind of driving method of above-mentioned array base palte, and described method comprises:
Within half display cycle of a two field picture display, first grid driving circuit exports gate drive signal to odd-numbered line gate line, source electrode driven integrated circuit exports the first source drive signal to each data line, and the polarity exporting to the described first source drive signal of adjacent two data lines is contrary;
Within another half display cycle of a two field picture display, second grid driving circuit exports gate drive signal to even number line gate line, source electrode driven integrated circuit exports the second source drive signal to each data line, and the polarity exporting to the described second source drive signal of adjacent two data lines is contrary;
Wherein, described first source drive signal is contrary with the polarity of described second source drive signal.
By the driving method of above-mentioned array base palte provided by the invention, because in the method, the polarity of the source drive signal of source electrode driven integrated circuit output does not need constantly to change, only need change once within half display cycle, while the upset of realization point, the power consumption of source electrode driven integrated circuit can be reduced.
Preferably, described first grid driving circuit gives corresponding gate line according to the Sequential output gate drive signal from top to bottom of gate line in array base palte, or, give corresponding gate line according to the Sequential output gate drive signal from top to bottom of gate line in array base palte;
Described second grid driving circuit gives corresponding gate line according to the Sequential output gate drive signal from top to bottom of gate line in array base palte, or, give corresponding gate line according to the Sequential output gate drive signal from top to bottom of gate line in array base palte.
Like this, by this scan method, convenient in actual scanning process, simple.
Preferably, the polarity of described first source drive signal is just, the polarity of described second source drive signal is negative; Or the polarity of described first source drive signal is negative, the polarity of described second source drive signal is just.
Like this, as long as the polarity of the first source drive signal is contrary with the polarity of the second source drive signal, a upset can be realized easily.
Accompanying drawing explanation
Fig. 1 is the structural representation of prior art array base palte;
Fig. 2 is the schematic diagram of the another kind of array base palte of prior art;
Fig. 3 is the schematic diagram of the array base palte of prior art double-gate structure;
The structural representation of a kind of array base palte that Fig. 4 provides for the embodiment of the present invention;
The structural representation of the another kind of array base palte that Fig. 5 provides for the embodiment of the present invention;
The annexation schematic diagram of the gate driver circuit in a kind of array base palte that Fig. 6 (a) and Fig. 6 (b) provide for the embodiment of the present invention;
The annexation schematic diagram of the another kind of gate driver circuit in a kind of array base palte that Fig. 7 provides for the embodiment of the present invention;
The schematic diagram of the array base palte of the double-gate structure that Fig. 8 provides for the embodiment of the present invention;
The driving method process flow diagram of a kind of array base palte that Fig. 9 provides for the embodiment of the present invention.
Embodiment
Embodiments providing a kind of array base palte and driving method, display panel, display device, in order to when realizing some upset, reducing the power consumption of source electrode driven integrated circuit.
The array base palte and driving method thereof that the specific embodiment of the invention provides is introduced in detail below in conjunction with accompanying drawing.
As shown in Figure 4, the specific embodiment of the invention provides a kind of array base palte, the pixel cell 40 comprising some arrayed, a plurality of data lines be connected with source electrode driven integrated circuit, as Data1, Data2, Data3, Data n and many gate lines being connected with gate driver circuit, as Gate1, Gate2, Gate3 and Gate4
Each odd-numbered line gate line is all corresponding connects a raster data model electronic circuit, as the first row gate lines G ate1 correspondence connects raster data model electronic circuit 410, the third line gate lines G ate3 correspondence connects raster data model electronic circuit 411, and all raster data model electronic circuit cascades be connected with odd-numbered line gate line connect to form first grid driving circuit 41;
Each even number line gate line is all corresponding connects a raster data model electronic circuit, as the second row gate lines G ate2 correspondence connects raster data model electronic circuit 420, fourth line gate lines G ate4 correspondence connects raster data model electronic circuit 421, and all raster data model electronic circuit cascades be connected with even number line gate line connect to form second grid driving circuit 42;
Within half display cycle of a two field picture display, odd-numbered line gate line receives the gate drive signal that first grid driving circuit 41 exports, and each data line receives the first source drive signal that source electrode driven integrated circuit exports; Within another half display cycle of a two field picture display, even number line gate line receives the gate drive signal that second grid driving circuit 42 exports, each data line receives the second source drive signal that source electrode driven integrated circuit exports, wherein, the first source drive signal is contrary with the polarity of the second source drive signal.
When same two field picture display, the polarity of the source drive signal that the source electrode driven integrated circuit that each data line receives exports within half display cycle is contrary, and the polarity of the source drive signal that the source electrode driven integrated circuit that adjacent two data lines receive exports is contrary.Particularly, if within half display cycle of a two field picture display, the polarity of the source drive signal that the source electrode driven integrated circuit that Data1 receives exports just is, then, within another half display cycle, the polarity of the source drive signal that the source electrode driven integrated circuit that Data1 receives exports is negative; If within half display cycle of a two field picture display, the polarity of the source drive signal that the source electrode driven integrated circuit that Data1 receives exports is negative, then within another half display cycle, the polarity of the source drive signal that the source electrode driven integrated circuit that Data1 receives exports just is.For adjacent two data lines, as Data1 and Data2, within the whole cycle of a two field picture display, the polarity of the source drive signal of the source electrode driven integrated circuit output of reception is contrary.
Particularly, for the array base palte of gate driver circuit single side scan, first grid driving circuit 41 and second grid driving circuit 42 are positioned at the same side of array base palte, certainly, first grid driving circuit 41 and second grid driving circuit 42 can also be arranged at respectively the heteropleural of array base palte in actual applications, as shown in Figure 5, the specific embodiment of the invention does not limit the particular location that first grid driving circuit 41 and second grid driving circuit 42 are arranged.
Introduce the waterfall sequence of each raster data model electronic circuit in first grid driving circuit and second grid driving circuit below in detail.
When the scanning trigger pip exporting gate drive signal for triggering first grid driving circuit or second grid driving circuit is one, in first grid driving circuit and second grid driving circuit, the waterfall sequence of each raster data model electronic circuit is as shown in Fig. 6 (a) He 6 (b).
Particularly, as shown in Fig. 6 (a), the specific embodiment of the invention is when image shows, first grid driving circuit 41 is according to gate line concatenated in order from top to bottom corresponding to array base palte, that is: the output terminal of the first order raster data model electronic circuit 610 of first grid driving circuit 41 is connected with the input end of the second level raster data model electronic circuit 611 of first grid driving circuit 41, second grid driving circuit 42 is according to gate line concatenated in order from top to bottom corresponding to array base palte, that is: the raster data model electronic circuit be connected with gate lines G ate n+1 is first order raster data model electronic circuit 620, export the scanning trigger pip 61 of gate drive signal be connected with the input end of the first order raster data model electronic circuit 610 of first grid driving circuit 41 for triggering first grid driving circuit 41, the afterbody raster data model electronic circuit 612 of first grid driving circuit 41 is connected with the first order raster data model electronic circuit 620 of second grid driving circuit 42.Under this annexation, first grid driving circuit 41 gives corresponding gate line according to the Sequential output gate drive signal from top to bottom of gate line in array base palte, i.e. first grid driving circuit 41 forward scan, as shown in arrow downward in figure, second grid driving circuit 42 gives corresponding gate line according to the Sequential output gate drive signal from top to bottom of gate line in array base palte, i.e. second grid driving circuit 42 reverse scan, as shown in arrow upwards in figure.
Certainly, can also be first grid driving circuit 41 in the specific embodiment of the invention according to gate line concatenated in order from top to bottom corresponding to array base palte, second grid driving circuit 42 is according to gate line concatenated in order from top to bottom corresponding to array base palte, first order raster data model electronic circuit for triggering scanning trigger pip and first grid driving circuit 41 that first grid driving circuit 41 exports gate drive signal is connected, the afterbody raster data model electronic circuit of first grid driving circuit 41 is connected with the first order raster data model electronic circuit of second grid driving circuit 42, concrete annexation and Fig. 6 (a) similar, under this annexation, first grid driving circuit 41 reverse scan, second grid driving circuit 42 forward scan.
As shown in Fig. 6 (b), the specific embodiment of the invention is when image shows, second grid driving circuit 42 is according to gate line concatenated in order from top to bottom corresponding to array base palte, that is: the output terminal of the first order raster data model electronic circuit 620 of second grid driving circuit 42 is connected with the input end of the second level raster data model electronic circuit 621 of second grid driving circuit 42, first grid driving circuit 41 is according to gate line concatenated in order from top to bottom corresponding to array base palte, that is: the raster data model electronic circuit be connected with gate lines G ate n is first order raster data model electronic circuit 610, first order raster data model electronic circuit 620 for triggering scanning trigger pip 62 and second grid driving circuit 42 that second grid driving circuit 42 exports gate drive signal is connected, the afterbody raster data model electronic circuit 622 of second grid driving circuit 42 is connected with the first order raster data model electronic circuit 610 of first grid driving circuit 41.Under this annexation, second grid driving circuit 42 gives corresponding gate line according to the Sequential output gate drive signal from top to bottom of gate line in array base palte, i.e. second grid driving circuit 42 forward scan, as shown in arrow downward in figure, first grid driving circuit 41 gives corresponding gate line according to the Sequential output gate drive signal from top to bottom of gate line in array base palte, i.e. first grid driving circuit 41 reverse scan, as shown in arrow upwards in figure.
Certainly, can also be second grid driving circuit 42 in the specific embodiment of the invention according to gate line concatenated in order from top to bottom corresponding to array base palte, first grid driving circuit 41 is according to gate line concatenated in order from top to bottom corresponding to array base palte, first order raster data model electronic circuit for triggering scanning trigger pip and second grid driving circuit 42 that second grid driving circuit 42 exports gate drive signal is connected, the afterbody raster data model electronic circuit of second grid driving circuit 42 is connected with the first order raster data model electronic circuit of first grid driving circuit 41, concrete annexation and Fig. 6 (b) similar, under this annexation, first grid driving circuit 41 forward scan, second grid driving circuit 42 reverse scan.
When the scanning trigger pip exporting gate drive signal for triggering first grid driving circuit or second grid driving circuit is two, in first grid driving circuit and second grid driving circuit, the waterfall sequence of each raster data model electronic circuit as shown in Figure 7.
First grid driving circuit 41, according to gate line concatenated in order from top to bottom corresponding to array base palte, is connected for the first order raster data model electronic circuit 610 triggering scanning trigger pip 61 and first grid driving circuit 41 that first grid driving circuit 41 exports gate drive signal.Second grid driving circuit 42, according to gate line concatenated in order from top to bottom corresponding to array base palte, is connected for the first order raster data model electronic circuit 620 triggering scanning trigger pip 62 and second grid driving circuit 42 that second grid driving circuit 42 exports gate drive signal.Under this annexation, first grid driving circuit 41 forward scan, second grid driving circuit 42 forward scan.
Certainly, the specific embodiment of the invention can also be first grid driving circuit 41 according to gate line concatenated in order from top to bottom corresponding to array base palte, second grid driving circuit 42 is according to gate line concatenated in order from top to bottom corresponding to array base palte, concrete annexation and Fig. 7 similar, under this annexation, first grid driving circuit 41 reverse scan, second grid driving circuit 42 forward scan.
The specific embodiment of the invention can also be first grid driving circuit 41 according to gate line concatenated in order from top to bottom corresponding to array base palte, second grid driving circuit 42 is according to gate line concatenated in order from top to bottom corresponding to array base palte, concrete annexation and Fig. 7 similar, under this annexation, first grid driving circuit 41 reverse scan, second grid driving circuit 42 reverse scan.
The specific embodiment of the invention can also be first grid driving circuit 41 according to gate line concatenated in order from top to bottom corresponding to array base palte, second grid driving circuit 42 is according to gate line concatenated in order from top to bottom corresponding to array base palte, concrete annexation and Fig. 7 similar, under this annexation, first grid driving circuit 41 forward scan, second grid driving circuit 42 reverse scan.
For double-gate structure, the first grid driving circuit 41 adopting the specific embodiment of the invention to provide and the type of drive of second grid driving circuit 42 scan, as shown in Figure 8, be the situation of carrying out overturning with two adjacent pixels relative to the pixel of prior art when some upset, the specific embodiment of the invention can realize the upset of single pixel.
As shown in Figure 9, the specific embodiment of the invention additionally provides a kind of driving method of array base palte, and the method comprises:
S901, one two field picture display half display cycle in, first grid driving circuit exports gate drive signal to odd-numbered line gate line, source electrode driven integrated circuit exports the first source drive signal to each data line, and the polarity exporting to the described first source drive signal of adjacent two data lines is contrary;
S902, one two field picture display another half display cycle in, second grid driving circuit exports gate drive signal to even number line gate line, source electrode driven integrated circuit exports the second source drive signal to each data line, and the polarity exporting to the described second source drive signal of adjacent two data lines is contrary;
Wherein, described first source drive signal is contrary with the polarity of described second source drive signal.
In sum, when the present invention is embodied in a two field picture display, triggered successively by the raster data model electronic circuit of odd-numbered line, the raster data model electronic circuit of even number line triggers successively.Like this, within half display cycle of a two field picture display, the pixel of odd-numbered line is opened and charges, and certainly, also can be that the pixel of even number line is opened and charges, at this moment same data line can input the signal of same polarity; Within another half display cycle of a two field picture display, the pixel of even number line is opened and charges, certainly, also can be that the pixel of odd-numbered line is opened and charges, at this moment same data line can input the signal of same polarity, namely in the whole display cycle of a two field picture display, the polarity of the signal of same data line input only needs conversion once, then can realize a picture display effect for upset, can reduce the power consumption of source electrode driven integrated circuit like this.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (8)
1. an array base palte, comprises the pixel cell of some arrayed, it is characterized in that,
Each odd-numbered line gate line is all corresponding connects a raster data model electronic circuit, and all raster data model electronic circuit cascades be connected with odd-numbered line gate line connect to form first grid driving circuit;
Each even number line gate line is all corresponding connects a raster data model electronic circuit, and all raster data model electronic circuit cascades be connected with even number line gate line connect to form second grid driving circuit;
Within half display cycle of a two field picture display, odd-numbered line gate line receives the gate drive signal that described first grid driving circuit exports, each data line receives the first source drive signal that source electrode driven integrated circuit exports, and the polarity of the described first source drive signal that adjacent two data lines receive is contrary;
Within another half display cycle of a two field picture display, even number line gate line receives the gate drive signal that described second grid driving circuit exports, each data line receives the second source drive signal that source electrode driven integrated circuit exports, and the polarity of the described second source drive signal that adjacent two data lines receive is contrary;
Wherein, described first source drive signal is contrary with the polarity of described second source drive signal.
2. array base palte according to claim 1, is characterized in that, described first grid driving circuit and described second grid driving circuit are positioned at the same side of array base palte; Or
Described first grid driving circuit and described second grid driving circuit lay respectively at the heteropleural of array base palte.
3. array base palte according to claim 2, is characterized in that,
When the scanning trigger pip for triggering described first grid driving circuit or second grid driving circuit output gate drive signal is one,
Described first grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, described second grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, or, described first grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, described second grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, be connected with the first order raster data model electronic circuit of described first grid driving circuit for triggering the described first grid driving circuit output scanning trigger pip of gate drive signal, the afterbody raster data model electronic circuit of described first grid driving circuit is connected with the first order raster data model electronic circuit of described second grid driving circuit, or,
Described second grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, described first grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, or, described second grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, described first grid driving circuit is according to gate line concatenated in order from top to bottom corresponding to array base palte, be connected with the first order raster data model electronic circuit of described second grid driving circuit for triggering the described second grid driving circuit output scanning trigger pip of gate drive signal, the afterbody raster data model electronic circuit of described second grid driving circuit is connected with the first order raster data model electronic circuit of described first grid driving circuit,
When the scanning trigger pip for triggering described first grid driving circuit or second grid driving circuit output gate drive signal is two,
Described first grid driving circuit, according to gate line concatenated in order from top to bottom or from top to bottom corresponding to array base palte, exports the scanning trigger pip of gate drive signal be connected with the first order raster data model electronic circuit of described first grid driving circuit for triggering described first grid driving circuit;
Described second grid driving circuit, according to gate line concatenated in order from top to bottom or from top to bottom corresponding to array base palte, exports the scanning trigger pip of gate drive signal be connected with the first order raster data model electronic circuit of described second grid driving circuit for triggering described second grid driving circuit.
4. a display panel, is characterized in that, described display panel comprises the array base palte described in the arbitrary claim of claim 1-3.
5. a display device, is characterized in that, described device comprises display panel according to claim 4.
6. a driving method for the array base palte described in the arbitrary claim of claim 1-3, is characterized in that, described method comprises:
Within half display cycle of a two field picture display, first grid driving circuit exports gate drive signal to odd-numbered line gate line, source electrode driven integrated circuit exports the first source drive signal to each data line, and the polarity exporting to the described first source drive signal of adjacent two data lines is contrary;
Within another half display cycle of a two field picture display, second grid driving circuit exports gate drive signal to even number line gate line, source electrode driven integrated circuit exports the second source drive signal to each data line, and the polarity exporting to the described second source drive signal of adjacent two data lines is contrary;
Wherein, described first source drive signal is contrary with the polarity of described second source drive signal.
7. driving method according to claim 6, is characterized in that,
Described first grid driving circuit gives corresponding gate line according to the Sequential output gate drive signal from top to bottom of gate line in array base palte, or, give corresponding gate line according to the Sequential output gate drive signal from top to bottom of gate line in array base palte;
Described second grid driving circuit gives corresponding gate line according to the Sequential output gate drive signal from top to bottom of gate line in array base palte, or, give corresponding gate line according to the Sequential output gate drive signal from top to bottom of gate line in array base palte.
8. method according to claim 6, is characterized in that, the polarity of described first source drive signal is just, the polarity of described second source drive signal is negative; Or the polarity of described first source drive signal is negative, the polarity of described second source drive signal is just.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410510675.0A CN104252079B (en) | 2014-09-28 | 2014-09-28 | A kind of array base palte and its driving method, display panel, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410510675.0A CN104252079B (en) | 2014-09-28 | 2014-09-28 | A kind of array base palte and its driving method, display panel, display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104252079A true CN104252079A (en) | 2014-12-31 |
| CN104252079B CN104252079B (en) | 2017-12-26 |
Family
ID=52187119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410510675.0A Active CN104252079B (en) | 2014-09-28 | 2014-09-28 | A kind of array base palte and its driving method, display panel, display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104252079B (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047115A (en) * | 2015-08-10 | 2015-11-11 | 武汉华星光电技术有限公司 | Detection drive circuit, detection drive unit and detection method |
| CN105741803A (en) * | 2016-03-28 | 2016-07-06 | 深圳市新奕光电有限公司 | Liquid crystal display drive method and circuit |
| CN105788549A (en) * | 2016-04-22 | 2016-07-20 | 昆山龙腾光电有限公司 | Pixel driving structure, driving method and display device |
| CN106847216A (en) * | 2017-03-02 | 2017-06-13 | 昆山龙腾光电有限公司 | Display device and display drive method |
| CN106952607A (en) * | 2017-05-25 | 2017-07-14 | 京东方科技集团股份有限公司 | Display base plate, display panel and display device |
| WO2017181482A1 (en) * | 2016-04-18 | 2017-10-26 | 深圳市华星光电技术有限公司 | Liquid crystal display and drive method therefor |
| CN107505792A (en) * | 2017-09-26 | 2017-12-22 | 深圳市华星光电半导体显示技术有限公司 | Array base palte, display panel and display device |
| WO2018028017A1 (en) * | 2016-08-10 | 2018-02-15 | 武汉华星光电技术有限公司 | Liquid-crystal display panel and liquid-crystal display device |
| CN108428426A (en) * | 2017-02-13 | 2018-08-21 | 群创光电股份有限公司 | Display panel and display device |
| US10580509B2 (en) | 2017-09-26 | 2020-03-03 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd | Array substrate, display panel and display device |
| CN113741105A (en) * | 2020-05-29 | 2021-12-03 | 京东方科技集团股份有限公司 | Array substrate, driving method thereof and display device |
| CN114495800A (en) * | 2022-03-07 | 2022-05-13 | 北京京东方显示技术有限公司 | Display panel driving method and display device |
| CN115064135A (en) * | 2022-07-08 | 2022-09-16 | 京东方科技集团股份有限公司 | Driving circuit and driving method of display panel and display device |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010046002A1 (en) * | 2000-05-29 | 2001-11-29 | Ming-Tien Lin | Dot inversion mode active matrix liquid crystal display with pre-writing circuit |
| US20040090561A1 (en) * | 2002-11-11 | 2004-05-13 | Song Sang Moo | Liquid crystal display panel and method of making the same |
| CN1790473A (en) * | 2004-12-14 | 2006-06-21 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus |
| CN101154357A (en) * | 2006-09-28 | 2008-04-02 | 胜华科技股份有限公司 | Driving method for scanning line |
| CN101216649A (en) * | 2008-01-10 | 2008-07-09 | 京东方科技集团股份有限公司 | Crystal display device array substrate and driving method thereof |
| CN101261801A (en) * | 2007-03-09 | 2008-09-10 | 株式会社瑞萨科技 | Driving circuit for displaying |
| CN101546542A (en) * | 2008-03-24 | 2009-09-30 | 索尼株式会社 | Liquid crystal display device, liquid crystal display method, display control device, and display control method |
| CN102456334A (en) * | 2010-10-28 | 2012-05-16 | 三星移动显示器株式会社 | Active matrix liquid crystal display panel with coupling of gate lines and data lines to pixels which reduces crosstalk and power consumption, and method of driving the same |
| CN103529610A (en) * | 2012-07-05 | 2014-01-22 | 乐金显示有限公司 | Liquid crystal display device |
| CN103700358A (en) * | 2013-12-31 | 2014-04-02 | 合肥京东方光电科技有限公司 | GIP (Gate In Panel) type LCD (Liquid Crystal Display) device |
-
2014
- 2014-09-28 CN CN201410510675.0A patent/CN104252079B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010046002A1 (en) * | 2000-05-29 | 2001-11-29 | Ming-Tien Lin | Dot inversion mode active matrix liquid crystal display with pre-writing circuit |
| US20040090561A1 (en) * | 2002-11-11 | 2004-05-13 | Song Sang Moo | Liquid crystal display panel and method of making the same |
| CN1790473A (en) * | 2004-12-14 | 2006-06-21 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus |
| CN101154357A (en) * | 2006-09-28 | 2008-04-02 | 胜华科技股份有限公司 | Driving method for scanning line |
| CN101261801A (en) * | 2007-03-09 | 2008-09-10 | 株式会社瑞萨科技 | Driving circuit for displaying |
| CN101216649A (en) * | 2008-01-10 | 2008-07-09 | 京东方科技集团股份有限公司 | Crystal display device array substrate and driving method thereof |
| CN101546542A (en) * | 2008-03-24 | 2009-09-30 | 索尼株式会社 | Liquid crystal display device, liquid crystal display method, display control device, and display control method |
| CN102456334A (en) * | 2010-10-28 | 2012-05-16 | 三星移动显示器株式会社 | Active matrix liquid crystal display panel with coupling of gate lines and data lines to pixels which reduces crosstalk and power consumption, and method of driving the same |
| CN103529610A (en) * | 2012-07-05 | 2014-01-22 | 乐金显示有限公司 | Liquid crystal display device |
| CN103700358A (en) * | 2013-12-31 | 2014-04-02 | 合肥京东方光电科技有限公司 | GIP (Gate In Panel) type LCD (Liquid Crystal Display) device |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047115A (en) * | 2015-08-10 | 2015-11-11 | 武汉华星光电技术有限公司 | Detection drive circuit, detection drive unit and detection method |
| CN105741803A (en) * | 2016-03-28 | 2016-07-06 | 深圳市新奕光电有限公司 | Liquid crystal display drive method and circuit |
| WO2017181482A1 (en) * | 2016-04-18 | 2017-10-26 | 深圳市华星光电技术有限公司 | Liquid crystal display and drive method therefor |
| CN105788549A (en) * | 2016-04-22 | 2016-07-20 | 昆山龙腾光电有限公司 | Pixel driving structure, driving method and display device |
| US10317760B2 (en) | 2016-08-10 | 2019-06-11 | Wuhan China Star Optoelectronics Technology Co., Ltd | Liquid crystal panels and liquid crystal devices |
| WO2018028017A1 (en) * | 2016-08-10 | 2018-02-15 | 武汉华星光电技术有限公司 | Liquid-crystal display panel and liquid-crystal display device |
| US10114261B2 (en) | 2016-08-10 | 2018-10-30 | Wuhan China Star Optoelectronics Technology Co., Ltd | Liquid crystal panels and liquid crystal devices |
| CN108428426A (en) * | 2017-02-13 | 2018-08-21 | 群创光电股份有限公司 | Display panel and display device |
| CN106847216A (en) * | 2017-03-02 | 2017-06-13 | 昆山龙腾光电有限公司 | Display device and display drive method |
| CN106847216B (en) * | 2017-03-02 | 2020-01-07 | 昆山龙腾光电有限公司 | Display device and display driving method |
| CN106952607A (en) * | 2017-05-25 | 2017-07-14 | 京东方科技集团股份有限公司 | Display base plate, display panel and display device |
| CN107505792A (en) * | 2017-09-26 | 2017-12-22 | 深圳市华星光电半导体显示技术有限公司 | Array base palte, display panel and display device |
| US10580509B2 (en) | 2017-09-26 | 2020-03-03 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd | Array substrate, display panel and display device |
| CN113741105A (en) * | 2020-05-29 | 2021-12-03 | 京东方科技集团股份有限公司 | Array substrate, driving method thereof and display device |
| CN114495800A (en) * | 2022-03-07 | 2022-05-13 | 北京京东方显示技术有限公司 | Display panel driving method and display device |
| CN114495800B (en) * | 2022-03-07 | 2023-12-26 | 北京京东方显示技术有限公司 | Display panel driving method and display device |
| CN115064135A (en) * | 2022-07-08 | 2022-09-16 | 京东方科技集团股份有限公司 | Driving circuit and driving method of display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104252079B (en) | 2017-12-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104252079A (en) | Array substrate, driving method thereof, display panel and display device | |
| CN103208250B (en) | A kind of driving circuit, driving method and display device | |
| CN104200786A (en) | Array substrate, and drive method, display panel and display device thereof | |
| US20180053478A1 (en) | Liquid crystal display panel and driving method thereof | |
| CN1847963B (en) | Liquid crystal display device | |
| CN105225652B (en) | A kind of driving method of display device, device and display device | |
| CN104977763B (en) | A kind of driving circuit and its driving method, liquid crystal display | |
| CN103250202B (en) | Display device and method for powering same | |
| CN104795044B (en) | Drive device, driving method and display device | |
| CN100498921C (en) | Driving method | |
| CN103280201B (en) | Gate drive apparatus and display device | |
| CN103187038B (en) | A kind of double-gate liquid crystal display device and driving method thereof | |
| CN101221337A (en) | Array substrate of LCD device and its driving method | |
| CN105511184A (en) | Liquid crystal display panel and driving method thereof | |
| CN105182638A (en) | Array substrate, display device and drive method thereof | |
| EP1555648A3 (en) | Display device and projection type display apparatus | |
| CN101216649A (en) | Crystal display device array substrate and driving method thereof | |
| US20160253955A1 (en) | Driving method and driving circuit of display panel and display device | |
| CN102819157A (en) | Liquid crystal display panel and display device | |
| CN103985365A (en) | Polarity inversion drive method and device of liquid crystal display panel | |
| KR102091434B1 (en) | Display device | |
| KR102045787B1 (en) | Method of driving display panel and display apparatus for performing the same | |
| CN105116656A (en) | Pixel driving method, pixel driving device and display device | |
| CN105527737A (en) | Liquid crystal display panel and driving method thereof | |
| CN105225635A (en) | Array base palte horizontal drive circuit, shift register, array base palte and display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |