CN107102682A - The system and method for DDS outputs is controlled by customed Qsys peripheral hardwares - Google Patents
The system and method for DDS outputs is controlled by customed Qsys peripheral hardwares Download PDFInfo
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- CN107102682A CN107102682A CN201710193769.3A CN201710193769A CN107102682A CN 107102682 A CN107102682 A CN 107102682A CN 201710193769 A CN201710193769 A CN 201710193769A CN 107102682 A CN107102682 A CN 107102682A
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- dds
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- core processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/022—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
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Abstract
The present invention relates to the system and method that DDS outputs are controlled by customed Qsys peripheral hardwares.The system that DDS outputs are controlled by customed Qsys peripheral hardwares, including soft-core processor, Avalon buses, element interface conversion matching module, DDS output control modules and DDS signal generator modules.The method that DDS outputs are controlled by customed Qsys peripheral hardwares, comprises the following steps：(1) soft-core processor sends Wave data, (2) soft-core processor is to FREQUENCY CONTROL word register transmission frequency control word, and frequency control word is issued into DDS signal generator modules, (3) control command is sent to DDS signal generator modules by soft-core processor, (4) Wave data that DDS signal generator modules are read in Wave data register produces waveform signal, and waveform signal is deposited with waveform signal register, (5) soft-core processor reads the data in waveform signal register, obtains waveform signal.
Description
Technical field
The invention belongs to electronic applications, and in particular to the system and method for DDS outputs is controlled by customed Qsys peripheral hardwares.
Background technology
The principle of existing DDS output control systems is as follows：MCU is directly controlled by parallel input and output (PIO) pattern
DDS module.PIO patterns are a kind of to perform I/O port commands by CPU and carry out the data exchange mode of reading and writing data.It is this
Lowly, CPU occupation rates are also very high for mode data transmission speed, can be because of the excessive cpu resource of occupancy during a large amount of transmission data
Cause system-down, it is impossible to carry out other operations.
The content of the invention
Goal of the invention：The present invention has made improvements in view of the above-mentioned problems of the prior art, i.e. first mesh of the invention
Be disclose by customed Qsys peripheral hardwares control DDS output system, it passes through the creating new component function in Qsys
Conversion logic needed for customization in component sequential, bus is directly accessed to the system by described element interface by peripheral hardware
(Avalon buses), and write correlation software operate on it.Second object of the present invention is to disclose by certainly
The method for customizing the control DDS outputs of Qsys peripheral hardwares.
Technical scheme：The system that DDS outputs are controlled by customed Qsys peripheral hardwares, including：
Soft-core processor, frequency and waveform for configuring DDS；
Avalon buses, are connected with the soft-core processor, and data interaction is carried out for soft-core processor and peripheral hardware；
Element interface changes matching module, is connected with the Avalon buses, for the signal from Avalon buses
Enter row decoding；
DDS output control modules, are connected with element interface conversion matching module, the register for configuring DDS；
DDS signal generator modules, are connected with the DDS output control modules, for producing output signal.
Further, the DDS output control modules include：
Wave data register, the output end that its input changes matching module with element interface is connected, for storing ripple
Shape is in output amplitude not in the same time；
FREQUENCY CONTROL word register, the output end that its input changes matching module with element interface is connected, for storing
The frequency of current waveform to be output；
Control command register, the output end that its input and element interface change matching module is connected, for start with
Stop Waveform is exported；
Waveform signal register, the input that its output end changes matching module with element interface is connected, for depositing DDS
The waveform signal that signal generator module is produced.
The method that DDS outputs are controlled by customed Qsys peripheral hardwares, comprises the following steps：
(1) soft-core processor sends Wave data by Avalon buses, and the Wave data is stored in Wave data deposit
In device,
(2) soft-core processor sends the frequency produced needed for waveform by Avalon buses to FREQUENCY CONTROL word register again
Control word, and frequency control word is sent to DDS signal generator modules,
(3) soft-core processor sends control command to control command register, and control command is sent into the production of DDS signals
Raw module,
(4) DDS signal generator modules are read in Wave data register by the frequency control word and control command of acquisition
Wave data produce waveform signal, and the waveform signal is deposited with waveform signal register,
(5) soft-core processor sends reading order, you can read the data in waveform signal register, obtains DDS signals
The waveform signal that generation module is produced.
Beneficial effect：It is disclosed by the invention by customed Qsys peripheral hardwares control DDS output system and method have with
Lower beneficial effect：
1st, the various registers that soft-core processor can be in the immediate system as accessing common peripheral hardware；
2nd, with it, the task that waveform is produced can be offloaded into DDS output control modules so that soft-core processor
More affairs can be handled, system real-time response performance is improved.
Brief description of the drawings
Fig. 1 is the structural schematic block diagram disclosed by the invention by the customed Qsys peripheral hardwares control DDS systems exported；
Fig. 2 is the schematic flow sheet disclosed by the invention by the customed Qsys peripheral hardwares control DDS methods exported.
Embodiment：
The embodiment to the present invention is described in detail below.
As shown in figure 1, the system of DDS outputs is controlled by customed Qsys peripheral hardwares, including：
Soft-core processor, frequency and waveform for configuring DDS；
Avalon buses, are connected with soft-core processor, and data interaction is carried out for soft-core processor and peripheral hardware；
Element interface changes matching module, is connected with Avalon buses, for being carried out to the signal from Avalon buses
Decoding；
DDS output control modules, are connected with element interface conversion matching module, the register for configuring DDS；
DDS signal generator modules, are connected with DDS output control modules, for producing output signal.
Further, DDS output control modules include：
Wave data register, the output end that its input changes matching module with element interface is connected, for storing ripple
Shape is in output amplitude not in the same time；
FREQUENCY CONTROL word register, the output end that its input changes matching module with element interface is connected, for storing
The frequency of current waveform to be output；
Control command register, the output end that its input and element interface change matching module is connected, for start with
Stop Waveform is exported；
Waveform signal register, the input that its output end changes matching module with element interface is connected, for depositing DDS
The waveform signal that signal generator module is produced.
As shown in Fig. 2 controlling the method for DDS outputs by customed Qsys peripheral hardwares, comprise the following steps：
(1) soft-core processor sends Wave data by Avalon buses, and the Wave data is stored in Wave data deposit
In device,
(2) soft-core processor sends the frequency produced needed for waveform by Avalon buses to FREQUENCY CONTROL word register again
Control word, and frequency control word is sent to DDS signal generator modules,
(3) soft-core processor sends control command to control command register, and control command is sent into the production of DDS signals
Raw module,
(4) DDS signal generator modules are read in Wave data register by the frequency control word and control command of acquisition
Wave data produce waveform signal, and the waveform signal is deposited with waveform signal register,
(5) soft-core processor sends reading order, you can read the data in waveform signal register, obtains DDS signals
The waveform signal that generation module is produced.
Embodiments of the present invention are elaborated above.But the present invention is not limited to above-mentioned embodiment,
In the knowledge that art those of ordinary skill possesses, it can also be done on the premise of present inventive concept is not departed from
Go out various change.
Claims (3)
1. the system of DDS outputs is controlled by customed Qsys peripheral hardwares, it is characterised in that including：
Soft-core processor, frequency and waveform for configuring DDS；
Avalon buses, are connected with the soft-core processor, and data interaction is carried out for soft-core processor and peripheral hardware；
Element interface changes matching module, is connected with the Avalon buses, for being carried out to the signal from Avalon buses
Decoding；
DDS output control modules, are connected with element interface conversion matching module, the register for configuring DDS；
DDS signal generator modules, are connected with the DDS output control modules, for producing output signal.
2. the system according to claim 1 that DDS outputs are controlled by customed Qsys peripheral hardwares, it is characterised in that described
DDS output control modules include：
Wave data register, the output end that its input changes matching module with element interface is connected, and exists for stored waveform
Not output amplitude in the same time；
FREQUENCY CONTROL word register, the output end that its input changes matching module with element interface is connected, current for storing
The frequency of waveform to be output；
Control command register, the output end that its input changes matching module with element interface is connected, for starting and stopping
Waveform is exported；
Waveform signal register, the input that its output end changes matching module with element interface is connected, for depositing DDS signals
The waveform signal that generation module is produced.
3. the method for DDS outputs is controlled by customed Qsys peripheral hardwares, it is characterised in that comprise the following steps：
(1) soft-core processor sends Wave data by Avalon buses, and the Wave data is stored in Wave data register,
(2) soft-core processor sends the FREQUENCY CONTROL produced needed for waveform by Avalon buses to FREQUENCY CONTROL word register again
Word, and frequency control word is sent to DDS signal generator modules,
(3) soft-core processor sends control command to control command register, and control command is sent into DDS signals generation mould
Block,
(4) DDS signal generator modules read the ripple in Wave data register by the frequency control word and control command of acquisition
Graphic data produces waveform signal, and the waveform signal is deposited with waveform signal register,
(5) soft-core processor sends reading order, you can read the data in waveform signal register, obtains DDS signals and produces
The waveform signal that module is produced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710193769.3A CN107102682A (en) | 2017-03-28 | 2017-03-28 | The system and method for DDS outputs is controlled by customed Qsys peripheral hardwares |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710193769.3A CN107102682A (en) | 2017-03-28 | 2017-03-28 | The system and method for DDS outputs is controlled by customed Qsys peripheral hardwares |
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| Publication Number | Publication Date |
|---|---|
| CN107102682A true CN107102682A (en) | 2017-08-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710193769.3A Pending CN107102682A (en) | 2017-03-28 | 2017-03-28 | The system and method for DDS outputs is controlled by customed Qsys peripheral hardwares |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090121796A1 (en) * | 2007-11-08 | 2009-05-14 | Patterson Jeffery S | Polyphase numerically controlled oscillator |
| CN104809085A (en) * | 2015-04-20 | 2015-07-29 | 哈尔滨工业大学 | Controller for excitation output by waveform self-defining based on AVALON bus and control method thereof |
-
2017
- 2017-03-28 CN CN201710193769.3A patent/CN107102682A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090121796A1 (en) * | 2007-11-08 | 2009-05-14 | Patterson Jeffery S | Polyphase numerically controlled oscillator |
| CN104809085A (en) * | 2015-04-20 | 2015-07-29 | 哈尔滨工业大学 | Controller for excitation output by waveform self-defining based on AVALON bus and control method thereof |
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| PB01 | Publication | ||
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| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170829 |