CN104809085A - Controller for excitation output by waveform self-defining based on AVALON bus and control method thereof - Google Patents
Controller for excitation output by waveform self-defining based on AVALON bus and control method thereof Download PDFInfo
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Abstract
The invention relates to a controller for excitation output by waveform self-defining based on an AVALON bus and a control method thereof, and belongs to the field of excitation output control. The existing controller for controlling peripherals in FPGA (field programmable gate array) has the defects of troublesome control process, easy mistaking, difficult adjusting, poor flexibility and universality, and long design time. The method comprises the following steps of enabling a microprocessor to store the setting number of waveform generation channels, waveform data information and a series of waveform discrete point values into an RAM (random access memory); starting a DA (digital to analog) conversion controller, repeatedly reading the waveform data information in the RAM, and respectively writing into corresponding registers; configuring the waveform data information under the mutual action of time interval controllers; starting a DA chip to convert and generate an expected task waveform. The method has the characteristics that the method is applied into the system for providing the excitation output, and the DA conversion chip with an SPI (serial peripheral interface) and a PIO (parallel input and output) interface is controlled to generate the waveform excitation output meeting the expectation of a user; the actual application value is high, the flexibility and convenience in use are realized, the universality is strong, and the like.
Description
Technical field
The present invention relates to controller and the control method thereof of a kind of waveform customization based on AVALON bus excitation output.
Background technology
Under many circumstances, user needs hardware system can produce excitation output to meet some specific demand according to self-defined random waveform.This process comprises to read and store user-defined shape information data and produces consistent excitation export two parts with according to the shape information stored.Whole process relates to the control of the many peripherals around the DA chip with SPI interface and PIO interface, and many employing FPGA complete the control to peripheral hardware at present.Because whole control procedure complexity is loaded down with trivial details, the logic that classic method is write exist control procedure loaded down with trivial details, easily make mistakes, redjustment and modification difficulty, dirigibility and poor universality, the shortcomings such as whole design process length consuming time.For this reason, need to propose a kind of brand-new controller scheme, make the logic control function based on the AVALON bus resource of FPGA inside and the IP kernel of maturation with random waveform excitation output.
Summary of the invention
The object of the invention is to there is to solve the controller controlling peripheral hardware in existing FPGA the problem that control procedure is loaded down with trivial details, adjust the design process length consuming time of difficulty, poor universality and controller itself, and propose controller and the control method thereof of a kind of waveform customization based on AVALON bus excitation output.
Based on the controller that the waveform customization excitation of AVALON bus exports, described controller comprises:
For reading the DA switching controller of Wave data information in RAM; Wherein, described DA switching controller configures one for what Wave data information is write different register and only writes master port, to control peripherals; The read-only master port of shape information data is write for obtaining in RAM with one;
For storing the RAM of the Wave data information of user's setting; Wherein, described RAM adopts ready-made IP kernel, for shortening the design cycle; And described RAM arrange one read-only from port for what read by DA switching controller, and one is only write from port for what write the shape information recording program of microprocessor in RAM, causes conflict to avoid reading while write RAM;
For generation of the DA chip of waveform;
The time interval controls device of wave period is set for the time interval between control waveform cycle mid point and point;
The microprocessor of the Wave data information of user's setting is stored for control RAM;
For connecting PIO register and the SPI register of DA chip, import the medium of DA chip by the Wave data information in RAM; Wherein, SPI register is for transmitting the information of opening and producing undulating path number, and PIO register is used for the information of the discrete point value of transmitted waveform.
Based on the controller control method that the waveform customization excitation of AVALON bus exports, described controller control method is realized by following steps:
The unlatching that user sets by step one, microprocessor produces undulating path number, Wave data information: waveform each cycle is always counted, the multiplicity of wave period and wave period, and a series of discrete point value of waveform comprising waveform shape and waveforms amplitude to be stored on FPGA sheet in RAM successively;
And when the multiplicity of the wave period arranged is between 1-65534, waveform disappears after repeating predetermined number of times, when the multiplicity of the wave period arranged is 65535, waveform can repeat until arrange new waveform or manually stop always;
Step 2, the Wave data information that step one stored, as configuration parameter, then send configuration-direct, to start DA switching controller by microprocessor to DA switching controller;
The Wave data information of step 3, DA switching controller memory ram storage in read step one repeatedly, then writes in corresponding PIO register and SPI register respectively by Wave data information;
Step 4, under the acting in conjunction of time interval controls device, complete the configuration of Wave data information;
Step 5, startup DA chip are changed, and make the respective channel port generation data interaction of PIO register and SPI register and DA chip; So far, nuclear energy in IP is set in advance according to user and the Wave data information control DA chip that inputs, produce the task waveform of expection, the excitation being finally integrated into the driving force with setting exports.
Beneficial effect of the present invention is:
(1) the present invention fully utilizes resource on the waveform customization excitation o controller and the ripe AVALON Bus Wire that provides of altera corp write, with AVALON bus for interconnected bus, design 8 autonomous channel random waveform excitation o controllers of the DA chip with SPI interface and PIO interface.There is logical organization advantage clearly, compared with the existing controller design cycle, by Controller gain variations cycle time 80%.
(2) the present invention is finally generated the IP kernel meeting AVALON bus protocol specification by SOPC Builder, and user can increase and decrease IP kernel number according to number of active lanes, makes controller have adjustment easy, the feature of applying flexible and versatility.
(3) the present invention is to have 16 passage DA conversion chips of SPI interface and PIO interface, solves 8 tunnel random waveform information data write buffer memorys and generates two large problems with reading.In this design basis, user can set waveform shape, waveforms amplitude, wave period, the multiplicity of wave period and the information of unlatching generation undulating path number in advance, and then logic control DA chip produces corresponding waveform, be integrated into the excitation with certain driving force and export.For realizing the greatest versatility of logic, strengthen flexibility ratio, all logics are made into the kernel meeting specification, can be articulated in AVALON bus according to actual needs by user, solve the problem that 16 passages produce the logic control that random waveform excitation exports independently of one another, final logical design exists with the IP kernel form meeting ALTERA Corporation Instructions, have flexible and convenient to use, stable and reliable for performance, highly versatile, the advantage of applied range.
Accompanying drawing explanation
Fig. 1 is the entire block diagram of the controller that the excitation of the waveform customization based on AVALON bus that the present invention relates to exports;
Fig. 2 is the Wave data information that the DA switching controller that the present invention relates to reads RAM, and it is write respectively corresponding PIO register and the schematic flow sheet of SPI register;
Fig. 3 is the state transition diagram that the embodiment of the present invention 1 relates to;
Embodiment
Embodiment one:
The controller of the excitation of the waveform customization based on the AVALON bus output of present embodiment, as shown in Figure 1, described controller comprises:
For reading the DA switching controller of Wave data information in RAM; Wherein, described DA switching controller configures one for what Wave data information is write different register and only writes master port, to control peripherals; The read-only master port of shape information data is write for obtaining in RAM with one;
For storing the RAM of the Wave data information of user's setting; Wherein, described RAM adopts ready-made IP kernel, for shortening the design cycle; And described RAM arrange one read-only from port for what read by DA switching controller, and one is only write from port for what write the shape information recording program of microprocessor in RAM, causes conflict to avoid reading while write RAM;
For generation of the DA chip of waveform;
The time interval controls device of wave period is set for the time interval between control waveform cycle mid point and point;
The microprocessor of the Wave data information of user's setting is stored for control RAM;
For connecting PIO register and the SPI register of DA chip, import the medium of DA chip by the Wave data information in RAM; Wherein, SPI register is for transmitting the information of opening and producing undulating path number, and PIO register is used for the information of the discrete point value of transmitted waveform.
Embodiment two:
The controller control method exported unlike the excitation of the waveform customization based on AVALON bus of, present embodiment with embodiment one, the channel end of described DA chip also arranges the power amplifier chip of the driving force for strengthening DA chip.
Embodiment three:
The controller control method of the excitation of the waveform customization based on the AVALON bus output of present embodiment, described controller control method is realized by following steps:
The unlatching that user sets by step one, microprocessor produces undulating path number, Wave data information: waveform each cycle is always counted, the multiplicity of wave period and wave period, and a series of discrete point value of waveform comprising waveform shape and waveforms amplitude to be stored on FPGA sheet in RAM successively;
And when the multiplicity of the wave period arranged is between 1-65534, waveform disappears after repeating predetermined number of times, when the multiplicity of the wave period arranged is 65535, waveform can repeat until arrange new waveform or manually stop always;
Step 2, the Wave data information that step one stored, as configuration parameter, then send configuration-direct, to start DA switching controller by microprocessor to DA switching controller;
The Wave data information of step 3, DA switching controller memory ram storage in read step one repeatedly, then writes in corresponding PIO register and SPI register respectively by Wave data information;
Step 4, under the acting in conjunction of time interval controls device, complete the configuration of Wave data information;
Step 5, startup DA chip are changed, and make the respective channel port generation data interaction of PIO register and SPI register and DA chip; So far, nuclear energy in IP is set in advance according to user and the Wave data information control DA chip that inputs, produce the task waveform of expection, the excitation being finally integrated into the driving force with setting exports.
Embodiment four:
With embodiment three unlike, the controller control method of the excitation of the waveform customization based on the AVALON bus output of present embodiment, as shown in Figure 2, the unlatching that user sets by microprocessor described in step one produces undulating path number, Wave data information: waveform each cycle is always counted, the multiplicity of wave period and wave period, and the process that a series of discrete point value of waveform comprising waveform shape and waveforms amplitude is stored on FPGA sheet in RAM is successively:
Step one by one, initialization DA chip;
Step one two, the unlatching generation undulating path number set by DA switching controller reading user;
Step one three, to be read waveform each cycle by DA switching controller and always to count num, and judge whether the waveform each cycle num that always counts is zero; If so, then DA chip exports clearing; If not, then next step is carried out;
Step one four, the unlatching of step one two being read produce waveform each cycle that undulating path number and step one three read and always count in RAM that num is stored on FPGA sheet;
The step First Five-Year Plan, be stored in the RAM on FPGA sheet by the multiplicity of wave period described in DA switching controller read step one;
Step one six, be stored to time interval controls device by wave period described in DA switching controller read step one;
Step one seven, by two discrete point values of waveform described in DA switching controller read step one: waveform shape and waveforms amplitude are also stored in the RAM on FPGA sheet.
Embodiment five:
With embodiment three or four unlike, the controller control method of the excitation of the waveform customization based on the AVALON bus output of present embodiment, open the situation producing undulating path number described in step one two to comprise: open all passages and produce consistent waveform, or only open one of them passage and produce waveform.
Embodiment six:
With embodiment five unlike, the controller control method of the excitation of the waveform customization based on the AVALON bus output of present embodiment, the Wave data information of the memory ram storage in read step one repeatedly of DA switching controller described in step 3, then process Wave data information write respectively in corresponding PIO register and SPI register is
Step 3 one, the multiplicity of wave period according to step one user setting, DA switching controller reads the discrete point value of the waveform stored in RAM repeatedly: waveform shape and waveforms amplitude also send to PIO register;
The unlatching of user's setting that step 3 two, DA switching controller are stored in described in read step one in RAM repeatedly produces undulating path number, and sends to SPI register;
Step 3 three, DA switching controller are repeatedly stored in the wave period in RAM described in read step one and send to time interval controls device;
The Wave data information in RAM is stored in: waveform each cycle is always counted, the multiplicity of wave period described in step 3 four, FPGA program repeat read step one.
Embodiment seven:
With embodiment three, four or six unlike, the controller control method of the excitation of the waveform customization based on the AVALON bus output of present embodiment, DA switching controller described in step 3 one reads the discrete point value of the waveform stored in RAM repeatedly: waveform shape and waveforms amplitude also send to the process of PIO register to be, wave period is set by the time interval between time interval controls device control waveform cycle mid point and point, often arrive the end time of wave period setting, time interval controls device produces high level enable signal a: i_endatatoDA=1, now DA switching controller is enabled signal enabling, start next the group waveforms amplitude read in RAM,
And, DA conversion instruction is started: i_enautoDA=1 when microprocessor sends, and the multiplicity of wave period does not reach the multiplicity of specifying: during this two conditions of autoDA=1, DA switching controller repeatedly reads the waveforms amplitude that stores in RAM and sends to PIO register to start to produce waveform with control DA chip.
Embodiment 1:
Based on AVALON bus waveform customization excitation export controller control method, the state conversion process of the logic control of whole controller as shown in Figure 3,
Step one by one, initialization DA chip;
Step one two, the unlatching generation undulating path number set by DA switching controller reading user;
Step one three, to be read waveform each cycle by DA switching controller and always to count num, and judge whether the waveform each cycle num that always counts is zero; If so, then DA chip exports clearing; If not, then next step is carried out;
Step one four, the unlatching of step one two being read produce waveform each cycle that undulating path number and step one three read and always count in RAM that num is stored on FPGA sheet;
The step First Five-Year Plan, be stored in the RAM on FPGA sheet by the multiplicity of wave period described in DA switching controller read step one; And when the multiplicity of the wave period arranged is 65534, waveform disappears after repeating 65534 times;
Step one six, be stored to time interval controls device by wave period described in DA switching controller read step one;
Step one seven, by two discrete point values of waveform described in DA switching controller read step one: waveform shape and waveforms amplitude are also stored in the RAM on FPGA sheet;
So far, the unlatching that user sets by microprocessor produces undulating path number, Wave data information: waveform each cycle is always counted, the multiplicity of wave period and wave period, and two discrete point values of waveform: waveform shape and waveforms amplitude to be stored on FPGA sheet in RAM successively;
Step 2, the Wave data information that step one stored, as configuration parameter, then send configuration-direct, to start DA switching controller by microprocessor to DA switching controller;
Step 3, microprocessor have issued and start DA conversion instruction, when namely starting the enable signal i_enautoDA=1 of DA switching controller, control DA switching controller starts to read successively to open from RAM to produce undulating path number chan_samplenumber [15:0], Wave data information: waveform each cycle is always counted, the multiplicity periodstop of wave period and wave period, and two discrete point values of waveform: waveform shape and waveforms amplitude RAMdata.
Comprise the chan_samplenumber [15:11] opening generation undulating path information of number and can deliver to SPI register by DA switching controller;
Wherein, chan_samplenumber [15:11] comprises open channel information of number: when chan_samplenumber [15]=1, represent that all passages all can produce consistent waveform; When chan_samplenumber [15]=0, represented the passage of the generation waveform that is unlocked by chan_samplenumber [14:11].What chan_samplenumber [10:0] represented that each cycle occurs counts.Periodstop represents the multiplicity of wave period, and according to the multiplicity of wave period of user's setting,
According to the multiplicity of the wave period of step one user setting, wave period is set by the time interval between time interval controls device control waveform cycle mid point and point, often arrive the end time of wave period setting, time interval controls device produces high level enable signal a: i_endatatoDA=1, now DA switching controller is enabled signal enabling, starts next the group waveforms amplitude read in RAM;
And, DA conversion instruction is started: i_enautoDA=1 when microprocessor sends, and the multiplicity of wave period does not reach the multiplicity of specifying: during this two conditions of autoDA=1, DA switching controller repeatedly reads the waveforms amplitude that stores in RAM and sends to PIO register to start to produce waveform with control DA chip;
Step 4, under the acting in conjunction of time interval controls device, complete the configuration of Wave data information;
Step 5, startup DA chip are changed, and make the respective channel port generation data interaction of PIO register and SPI register and DA chip; So far, nuclear energy in IP is set in advance according to user and the Wave data information control DA chip that inputs, produce the task waveform of expection, the excitation being finally integrated into the driving force with setting exports.
The present invention, to have 16 passage DA conversion chips of SPI interface and PIO interface, solves 8 tunnel random waveform information data write buffer memorys and generates two large problems with reading.In this design basis, user can set waveform shape, waveforms amplitude, wave period, the multiplicity of wave period and the information of unlatching generation undulating path number in advance, and then logic control DA chip produces corresponding waveform, be integrated into the excitation with certain driving force and export.For realizing the greatest versatility of logic, strengthen flexibility ratio, all logics are made into the kernel meeting specification, can be articulated according to actual needs in AVALON bus by user.
Claims (7)
1., based on the controller that the waveform customization excitation of AVALON bus exports, it is characterized in that: described controller comprises:
For reading the DA switching controller of Wave data information in RAM; Wherein, described DA switching controller configures one for what Wave data information is write different register and only writes master port, to control peripherals; The read-only master port of shape information data is write for obtaining in RAM with one;
For storing the RAM of the Wave data information of user's setting; Wherein, described RAM adopts ready-made IP kernel, for shortening the design cycle; And described RAM arrange one read-only from port for what read by DA switching controller, and one is only write from port for what write the shape information recording program of microprocessor in RAM, causes conflict to avoid reading while write RAM;
For generation of the DA chip of waveform;
The time interval controls device of wave period is set for the time interval between control waveform cycle mid point and point;
The microprocessor of the Wave data information of user's setting is stored for control RAM;
For connecting PIO register and the SPI register of DA chip, import the medium of DA chip by the Wave data information in RAM; Wherein, SPI register is for transmitting the information of opening and producing undulating path number, and PIO register is used for the information of the discrete point value of transmitted waveform.
2., according to claim 1 based on the controller control method that the waveform customization excitation of AVALON bus exports, it is characterized in that: the channel end of described DA chip also arranges the power amplifier chip of the driving force for strengthening DA chip.
3., based on the controller control method that the waveform customization excitation of AVALON bus exports, it is characterized in that: described controller control method is realized by following steps:
The unlatching that user sets by step one, microprocessor produces undulating path number, Wave data information: waveform each cycle is always counted, the multiplicity of wave period and wave period, and a series of discrete point value of waveform comprising waveform shape and waveforms amplitude to be stored on FPGA sheet in RAM successively;
And when the multiplicity of the wave period arranged is between 1-65534, waveform disappears after repeating predetermined number of times, when the multiplicity of the wave period arranged is 65535, waveform can repeat until arrange new waveform or manually stop always;
Step 2, the Wave data information that step one stored, as configuration parameter, then send configuration-direct, to start DA switching controller by microprocessor to DA switching controller;
The Wave data information of step 3, DA switching controller memory ram storage in read step one repeatedly, then writes in corresponding PIO register and SPI register respectively by Wave data information;
Step 4, under the acting in conjunction of time interval controls device, complete the configuration of Wave data information;
Step 5, startup DA chip are changed, and make the respective channel port generation data interaction of PIO register and SPI register and DA chip; So far, nuclear energy in IP is set in advance according to user and the Wave data information control DA chip that inputs, produce the task waveform of expection, the excitation being finally integrated into the driving force with setting exports.
4. according to claim 3 based on the controller control method that the waveform customization excitation of AVALON bus exports, it is characterized in that: the unlatching that user sets by microprocessor described in step one produces undulating path number, Wave data information: waveform each cycle is always counted, the multiplicity of wave period and wave period, and the process that a series of discrete point value of waveform comprising waveform shape and waveforms amplitude is stored on FPGA sheet in RAM is successively:
Step one by one, initialization DA chip;
Step one two, the unlatching generation undulating path number set by DA switching controller reading user;
Step one three, to be read waveform each cycle by DA switching controller and always to count num, and judge whether the waveform each cycle num that always counts is zero; If so, then DA chip exports clearing; If not, then next step is carried out;
Step one four, the unlatching of step one two being read produce waveform each cycle that undulating path number and step one three read and always count in RAM that num is stored on FPGA sheet;
The step First Five-Year Plan, be stored in the RAM on FPGA sheet by the multiplicity of wave period described in DA switching controller read step one;
Step one six, be stored to time interval controls device by wave period described in DA switching controller read step one;
Step one seven, by two discrete point values of waveform described in DA switching controller read step one: waveform shape and waveforms amplitude are also stored in the RAM on FPGA sheet.
5. according to claim 3 or 4, encourage based on the waveform customization of AVALON bus the controller control method exported, it is characterized in that: open the situation producing undulating path number described in step one two and comprise: open all passages and produce consistent waveform, or only open one of them passage and produce waveform.
6. according to claim 5 based on the controller control method that the waveform customization excitation of AVALON bus exports, it is characterized in that: the Wave data information of the memory ram storage in read step one repeatedly of DA switching controller described in step 3, then process Wave data information write respectively in corresponding PIO register and SPI register is
Step 3 one, the multiplicity of wave period according to step one user setting, DA switching controller reads the discrete point value of the waveform stored in RAM repeatedly: waveform shape and waveforms amplitude also send to PIO register;
The unlatching of user's setting that step 3 two, DA switching controller are stored in described in read step one in RAM repeatedly produces undulating path number, and sends to SPI register;
Step 3 three, DA switching controller are repeatedly stored in the wave period in RAM described in read step one and send to time interval controls device;
The Wave data information in RAM is stored in: waveform each cycle is always counted, the multiplicity of wave period described in step 3 four, FPGA program repeat read step one.
7. according to claim 3, based on the controller control method that the waveform customization excitation of AVALON bus exports described in 4 or 6, it is characterized in that: DA switching controller described in step 3 one reads the discrete point value of the waveform stored in RAM repeatedly: waveform shape and waveforms amplitude also send to the process of PIO register to be, wave period is set by the time interval between time interval controls device control waveform cycle mid point and point, often arrive the end time of wave period setting, time interval controls device produces a high level enable signal, now DA switching controller is enabled signal enabling, start next the group waveforms amplitude read in RAM,
And, DA conversion instruction is started when microprocessor sends, and the multiplicity of wave period is not when reaching this two conditions of multiplicity of specifying, DA switching controller repeatedly reads the waveforms amplitude that stores in RAM and sends to PIO register to start to produce waveform with control DA chip.
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