CN107086803B - A kind of capacitor voltage balance control strategy of modularization multi-level converter - Google Patents
A kind of capacitor voltage balance control strategy of modularization multi-level converter Download PDFInfo
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- CN107086803B CN107086803B CN201710464858.7A CN201710464858A CN107086803B CN 107086803 B CN107086803 B CN 107086803B CN 201710464858 A CN201710464858 A CN 201710464858A CN 107086803 B CN107086803 B CN 107086803B
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/4835—Converters with outputs that each can have more than two voltages levels comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/49—Combination of the output voltage waveforms of a plurality of converters
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
The invention discloses a kind of capacitor voltage balance control strategies of modularization multi-level converter, it is different from conventional measures, the present invention considers the current switching state of submodule and capacitance voltage when putting into submodule, and the higher submodule of priority will be put into labeled as 1, it cuts off the higher submodule of priority and is labeled as 0, then the submodule marked respectively to two kinds is ranked up and switching operation, under the premise of guaranteeing that voltage fluctuation of capacitor is lesser, reduce the switching frequency of submodule, and reduces capacitance voltage and sort the occupied time, it can make inverter under lower submodule switching frequency, complete submodule capacitor voltage balance control.
Description
Technical field
The invention belongs to power electronic system technical fields, and in particular to a kind of capacitor electricity of modularization multi-level converter
Flatten weighing apparatus control strategy.
Background technique
With flourishing for power electronic technique, it is based on modularization multi-level converter (modular multilevel
Converter, MMC) D.C. high voltage transmission (high voltage direct current, HVDC) technology be considered as most
It is appropriate for one of the technology of mesohigh transmission of electricity.It is compared with other voltage source converter topologys, modularization multi-level converter
With significant advantage；Due to the form using basic operation sub-module cascade, which avoids a large amount of switching devices and directly goes here and there
The problems such as connection, there is no consistent triggerings, reduce the manufacture difficulty of equipment；The topology also possess simultaneously lower switching frequency and
Inverter loss, has very strong economy, therefore the topology is applied to rapidly new-energy grid-connected, offshore wind farm is sent in recent years
The occasions such as out.
The submodule capacitor voltage balance control of inverter is always the emphasis paid close attention in Practical Project, typical three-phase
The system structure of MMC inverter as shown in Figure 1, inverter includes 6 bridge arms altogether, wherein every bridge arm include N number of submodule with
An and bridge arm reactance.Bridge arm current positive direction is enabled as shown in Figure 1, putting into the submodule capacitor of state when bridge arm current is positive
It is electrically charged, when bridge arm current is negative, the submodule for putting into state is discharged.Each submodule capacitor is independent mutually, and submodule
It is unbalanced that the difference of charge and discharge time and capacitor will be such that its capacitance voltage occurs, and influences the normal operation of inverter entirety.
Traditional capacitor voltage balance control strategy are as follows: first detect the capacitance voltage in bridge arm current direction and each submodule
And it is ranked up；If bridge arm current charges to sub- module capacitance, puts into and correspond to according to the sequence of capacitance voltage from low to high
The submodule of quantity；If bridge arm current discharges to sub- module capacitance, phase is put into according to the sequence of capacitance voltage from high to low
The submodule answered.The problem of this method, is not accounting for the original state of submodule, greatly increase in operational process
Submodule switching frequency, this will lead to the switching frequency of power electronic devices and the rising of switching loss, to reduce module
Change the operational efficiency of multilevel converter.In addition to this, when voltage class rises, bridge arm submodule quantity can be greatly increased,
So that the more time can be occupied by being ranked up to all submodules, biggish delay is introduced in triggering control.
Summary of the invention
In view of above-mentioned, the present invention provides a kind of capacitor voltage balance control strategy of modularization multi-level converter, energy
Under the premise of guaranteeing that voltage fluctuation of capacitor is lesser, the switching frequency of submodule is reduced, and is reduced occupied by capacitance voltage sequence
Time.
A kind of capacitor voltage balance control strategy of modularization multi-level converter, includes the following steps:
(1) for any bridge arm of inverter, the submodule that investment state is in current bridge arm is labeled as 1, is in
The submodule of excision state is labeled as 0；
(2) wave component of each submodule capacitor voltage in bridge arm is calculated, and then acquires the capacitance voltage of entire bridge arm
Stability bandwidth ε；
(3) compare voltage fluctuation of capacitor rate ε and stability bandwidth threshold epsilonmSize: if ε >=εm, then (4) are entered step；If ε <
εm, then step (5) are jumped directly to；
(4) upper lower limit value for determining submodule capacitor voltage, the direction for enabling bridge arm current flow to low-pressure end from high-voltage end are
Just, it otherwise is negative；And then according to bridge arm current direction and the relationship of submodule capacitor voltage and upper lower limit value section, to submodule
Block label is updated；
(5) according to formula Δ Non=Non-NmarkCalculate the investment departure Δ N of bridge arm submoduleon, NmarkTo count
The bridge arm submodule number that current markers are 1, NonIt is counted for control system by respective algorithms (nearest level approaches modulation algorithm)
Submodule quantity is put into needed for obtained current bridge arm；
(6) according to investment departure Δ NonAnd bridge arm current carries out switching control to bridge arm submodule.
The wave component of each submodule capacitor voltage in bridge arm is calculated in the step (2) according to following formula:
Δuc,i=uc,i-Ucn
Wherein: Δ uc,iFor the wave component of i-th of submodule capacitor voltage in bridge arm, uc,iFor i-th of submodule in bridge arm
The capacitance voltage of block, UcnFor submodule capacitor voltage rated value and Ucn=Udc/ N, UdcFor the DC side voltage rating of inverter, i
For natural number and 1≤i≤N, N are the submodule number in bridge arm.
The voltage fluctuation of capacitor rate ε of entire bridge arm is calculated in the step (2) according to following formula:
Stability bandwidth threshold epsilon in the step (3)mIt is set as 5%~10%.
The upper lower limit value of submodule capacitor voltage is determined in the step (4) according to following formula:
Uup=Ucn(1+εm) Ulow=Ucn(1-εm)
Wherein: UupAnd UlowThe respectively upper limit value and lower limit value of submodule capacitor voltage, UcnFor submodule capacitor voltage
Rated value and Ucn=Udc/ N, UdcFor the DC side voltage rating of inverter, N is the submodule number in bridge arm.
The standard being updated in the step (4) to sub- module marks is as follows:
If bridge arm current >=0, the submodule that capacitance voltage in bridge arm is greater than upper limit value is labeled as 0, capacitance voltage is small
It is labeled as 1 in the submodule of lower limit value, submodule of the capacitance voltage in upper lower limit value section keeps former label constant；If bridge arm
The submodule that capacitance voltage in bridge arm is greater than upper limit value is then labeled as 1 by electric current < 0, and capacitance voltage is less than the submodule of lower limit value
Block is labeled as 0, and submodule of the capacitance voltage in upper lower limit value section keeps former label constant.
It is as follows to the standard of bridge arm submodule progress switching control in the step (6):
As Δ NonWhen > 0: if bridge arm current >=0, marking the submodule for being investment and from being labeled as all in bridge arm
The minimum Δ N of capacitance voltage is put into 0 submoduleonA submodule, while by remaining submodule complete resection；If bridge arm is electric
< 0 is flowed, then marks the submodule investment for being and the investment capacitance voltage highest from the submodule labeled as 0 for all in bridge arm
Δ NonA submodule, while by remaining submodule complete resection；
As Δ NonWhen < 0: if bridge arm current >=0, the minimum N of investment capacitance voltage from the submodule labeled as 1on
A submodule, while by remaining submodule complete resection；If bridge arm current < 0, electricity is put into from the submodule labeled as 1
Hold the highest N of voltageonA submodule, while by remaining submodule complete resection；
As Δ NonWhen=0: then mark the submodule for being to put into for all in bridge arm, it is all that the submodule for being is marked to cut
It removes.
Different from conventional measures, the present invention considers the current switching state of submodule and capacitor electricity when putting into submodule
Pressure, and the higher submodule of priority will be put into labeled as 1, the excision higher submodule of priority is then right respectively labeled as 0
The submodule of two kinds of labels is ranked up and switching operation, under the premise of guaranteeing that voltage fluctuation of capacitor is lesser, reduces submodule
The switching frequency of block, and reduce capacitance voltage and sort the occupied time, inverter can be made in lower submodule switching frequency
Under rate, meet the balance requirement of submodule capacitor voltage.Therefore, advantageous effects of the invention are summarized as follows:
(1) control strategy of the present invention simply and efficiently realizes the capacitance voltage equilibrium of a large amount of submodules.
(2) control strategy of the present invention is under the premise of unobvious increase submodule capacitor voltage degree of unbalancedness and stability bandwidth,
Significantly reduce the switching frequency of submodule and the switching loss of power electronic devices.
(3) control strategy of the present invention can be thrown by setting voltage fluctuation of capacitor threshold value to regulate and control the submodule of controlled bridge arm
Cut frequency and voltage fluctuation of capacitor rate.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of modularization multi-level converter.
Fig. 2 is the flow diagram of capacitor voltage balance control strategy of the present invention.
Fig. 3 is the simulation waveform of each submodule capacitor voltage of bridge arm in A phase in the case of voltage fluctuation of capacitor threshold value is 9%
Figure.
Specific embodiment
In order to more specifically describe the present invention, with reference to the accompanying drawing and specific embodiment is to technical solution of the present invention
And its relative theory is described in detail.
As shown in Figure 1, in the present embodiment modularization multi-level converter use six bridge arm structure of three-phase, each bridge arm by
Several half-bridge submodules and a bridge arm reactor are composed in series, for the three-phase alternating current of AC network to be converted to direct current
Electricity.Half-bridge submodule output voltage exists just with 0 two kinds of level, and bridge arm reactor is able to suppress the bridge arm change of current, in DC Line Fault
When play the role of that fault current is inhibited to rise, the protection devices such as IGBT.Half-bridge submodule is by two IGBT pipe T1~T2 and one
A capacitor C is constituted；Wherein, the output end of IGBT pipe T1 is connected and constitutes the one of half-bridge submodule with the input terminal of IGBT pipe T2
End, the input terminal of IGBT pipe T1 are connected with one end of capacitor C, and the output end of IGBT pipe T2 is connected with the other end of capacitor C and structure
At the other end of half-bridge submodule.
Capacitor voltage balance control strategy of the present invention is used for above-mentioned converter structure, detailed process is as shown in Figure 2:
(1) submodule for being now in investment state is labeled as 1 first, the submodule in excision state is labeled as 0.
(2) by taking bridge arm in A phase as an example, the wave component of each submodule capacitor voltage is calculated using following formula:
Δuc,i=uc,i-Ucn(i=1,2 ..., N)
Wherein, uc,iFor the capacitance voltage of i-th of submodule in bridge arm in A phase, the rated value U of submodule capacitor voltagecnBy
Following formula calculates, UdcFor the DC side voltage rating of inverter, N is the submodule number in bridge arm.
(3) the voltage fluctuation of capacitor rate ε of entire bridge arm is calculated using following formula:
Wherein: max | Δ uC, i| for maximum voltage fluctuation of capacitor component in N number of submodule.
(4) compare ε and threshold epsilonmSize, when ε be more than or equal to εmWhen, it carries out step (5)；When ε is less than εmWhen, directly into
Row step (7).
(5) the upper limit value U of following formula computational submodule capacitance voltage is utilizedupWith lower limit value Ulow:
Uup=Ucn(1+εm)
Ulow=Ucn(1-εm)
(6) bridge arm current i is enabledarm,apDirection is identical with Fig. 1 to be positive, otherwise is negative.Work as iarm,apIt, will when more than or equal to 0
The submodule that all capacitance voltages are greater than upper limit value is labeled as 0, and the submodule that all capacitance voltages are less than lower limit value is labeled as 1,
Holding label between upper lower limit value is constant；Work as iarm,apWhen less than 0, all capacitance voltages are greater than to the submodule of upper limit value
Labeled as 1, the submodule that all capacitance voltages are less than lower limit value is labeled as 0, and the holding label between upper lower limit value is constant.
(7) statistics is N labeled as the quantity of 1 submodulemark, what the current needs that upper controller is calculated were put into
Submodule quantity is Non, the departure Δ N of the two is calculated with following formulaon:
ΔNon=Non-Nmark
(8) as Δ NonWhen greater than 0: if iarm,apMore than or equal to 0, the submodule for being is marked to put by all, and marking
To put into the minimum Δ N of voltage in 0 submoduleonA submodule, by remaining submodule complete resection；If iarm,apLess than 0,
The submodule investment for being is marked by all, and puts into the highest Δ N of voltage in the submodule labeled as 0onA submodule, will
Remaining submodule complete resection.
As Δ NonWhen less than 0: if iarm,apMore than or equal to 0, the minimum N of investment voltage in the submodule labeled as 1onIt is a
Submodule, by remaining submodule complete resection；If iarm,apLess than 0, investment voltage is highest in the submodule labeled as 1
NonA submodule, by remaining submodule complete resection.
As Δ NonWhen equal to 0: mark the submodule for being to put into for all, it is all to mark the submodule excision for being.
So far the capacitor voltage balance control of modularization multi-level converter is completed.
It is as shown in table 1 using the modularization multi-level converter parameter of present embodiment control strategy in conjunction with Fig. 1:
Table 1
The voltage fluctuation of capacitor threshold epsilon of setting is taken respectivelymIt is 0% to 14%, wherein εmI.e. traditional capacitor electricity when taking 0%
Press balance control method.According to simulation result, the submodule of bridge arm is averaged switching frequency f in the A phase under different settingssw,ave
With maximum capacitor voltage fluctuation rate εmaxIt is as shown in table 2:
Table 2
As can be seen from Table 2 using after capacitor voltage balance strategy of the present invention, obviously do not increase in voltage fluctuation of capacitor rate
In the case where big, the submodule switching frequency that is averaged has obtained significant reduction.Simultaneously as voltage fluctuation of capacitor threshold epsilonmIt is one
A value that can be set, so that inverter becomes more flexible to the control of voltage fluctuation of capacitor rate and submodule switching frequency.
When the voltage fluctuation of capacitor threshold epsilon of settingmWhen being 9%, 20 submodule capacitor voltages for obtaining bridge arm in A phase are imitative
For true waveform as shown in figure 3, compared to the 0% of corresponding traditional control method, switching frequency is reduced to 153Hz from 2021Hz, and
Maximum capacitor voltage fluctuation rate has only risen to 10.1% from 8.3%.
The above-mentioned description to embodiment is for that can understand and apply the invention convenient for those skilled in the art.
Person skilled in the art obviously easily can make various modifications to above-described embodiment, and described herein general
Principle is applied in other embodiments without having to go through creative labor.Therefore, the present invention is not limited to the above embodiments, ability
Field technique personnel announcement according to the present invention, the improvement made for the present invention and modification all should be in protection scope of the present invention
Within.
Claims (3)
1. a kind of capacitor voltage balance control strategy of modularization multi-level converter, includes the following steps:
(1) for any bridge arm of inverter, the submodule that investment state is in current bridge arm is labeled as 1, in excision
The submodule of state is labeled as 0；
(2) wave component of each submodule capacitor voltage in bridge arm is calculated according to following formula；
Δuc,i=uc,i-Ucn
Wherein: Δ uc,iFor the wave component of i-th of submodule capacitor voltage in bridge arm, uc,iFor i-th submodule in bridge arm
Capacitance voltage, UcnFor submodule capacitor voltage rated value and Ucn=Udc/ N, UdcFor the DC side voltage rating of inverter, i is certainly
So number and 1≤i≤N, N are the submodule number in bridge arm；
And then the voltage fluctuation of capacitor rate ε for acquiring entire bridge arm is calculated according to following formula；
(3) compare voltage fluctuation of capacitor rate ε and stability bandwidth threshold epsilonmSize: if ε >=εm, then (4) are entered step；If ε < εm,
Then jump directly to step (5)；
(4) upper lower limit value for determining submodule capacitor voltage, the direction for enabling bridge arm current flow to low-pressure end from high-voltage end are positive, instead
Be negative；And then according to bridge arm current direction and the relationship of submodule capacitor voltage and upper lower limit value section, to submodule mark
Note is updated, specific standards are as follows: if bridge arm current >=0, the submodule that capacitance voltage in bridge arm is greater than upper limit value is marked
It is 0, the submodule that capacitance voltage is less than lower limit value is labeled as 1, and submodule of the capacitance voltage in upper lower limit value section keeps former
It marks constant；If bridge arm current < 0, the submodule that capacitance voltage in bridge arm is greater than upper limit value is labeled as 1, capacitance voltage is small
It is labeled as 0 in the submodule of lower limit value, submodule of the capacitance voltage in upper lower limit value section keeps former label constant；
(5) according to formula Δ Non=Non-NmarkCalculate the investment departure Δ N of bridge arm submoduleon, NmarkIt is current to count
Labeled as 1 bridge arm submodule number, NonSon is put into needed for the current bridge arm being calculated for control system by respective algorithms
Module number；
(6) according to investment departure Δ NonAnd bridge arm current carries out switching control to bridge arm submodule, specific standards are as follows:
As Δ NonWhen > 0: if bridge arm current >=0, marking the submodule investment for being and from labeled as 0 for all in bridge arm
The minimum Δ N of capacitance voltage is put into submoduleonA submodule, while by remaining submodule complete resection；If bridge arm current
The submodule that labels all in bridge arm are then is put into and investment capacitance voltage is highest from the submodule labeled as 0 by < 0
ΔNonA submodule, while by remaining submodule complete resection；
As Δ NonWhen < 0: if bridge arm current >=0, the minimum N of investment capacitance voltage from the submodule labeled as 1onA submodule
Block, while by remaining submodule complete resection；If bridge arm current < 0, capacitance voltage is put into from the submodule labeled as 1
Highest NonA submodule, while by remaining submodule complete resection；
As Δ NonWhen=0: then mark the submodule for being to put into for all in bridge arm, it is all to mark the submodule excision for being.
2. capacitor voltage balance control strategy according to claim 1, it is characterised in that: the fluctuation in the step (3)
Rate threshold epsilonmIt is set as 5%~10%.
3. capacitor voltage balance control strategy according to claim 1, it is characterised in that: in the step (4) according to
Lower formula determines the upper lower limit value of submodule capacitor voltage:
Uup=Ucn(1+εm)Ulow=Ucn(1-εm)
Wherein: UupAnd UlowThe respectively upper limit value and lower limit value of submodule capacitor voltage, UcnFor submodule capacitor voltage rated value
And Ucn=Udc/ N, UdcFor the DC side voltage rating of inverter, N is the submodule number in bridge arm.
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| CN108054944B (en) * | 2018-01-25 | 2019-05-07 | 湖南大学 | A kind of 50 electric harmonic generator control methods |
| CN108832826B (en) * | 2018-05-25 | 2020-10-23 | 广东电网有限责任公司电力调度控制中心 | MMC capacitor voltage balance control method suitable for FPGA |
| CN109067222A (en) * | 2018-08-07 | 2018-12-21 | 西安西电电力系统有限公司 | A kind of IGBT control method based on MMC-HVDC |
| CN109149946A (en) * | 2018-09-20 | 2019-01-04 | 南京工程学院 | A kind of DC/DC current transformer voltage balance control policy optimization method |
| CN109274285B (en) * | 2018-10-24 | 2020-04-03 | 南方电网科学研究院有限责任公司 | Capacitance voltage balancing method of hybrid modular multilevel converter |
| CN111600495B (en) * | 2019-02-21 | 2023-04-18 | 国家电网有限公司 | Submodule control method and device of MMC (modular multilevel converter) with damping resistor |
| CN112467777B (en) * | 2020-11-16 | 2022-06-21 | 国网浙江省电力有限公司电力科学研究院 | Method for controlling asymmetric direct current by using modular combined direct current transformer |
| CN112600451B (en) * | 2020-11-17 | 2021-11-16 | 西安西电电力系统有限公司 | Flexible direct current converter valve power module capacitor voltage equalizing method |
| CN115549439B (en) * | 2022-11-29 | 2023-05-23 | 东南大学 | MMC switching loss optimization method and equipment under low-power operation |
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| JP2014018028A (en) * | 2012-07-11 | 2014-01-30 | Toshiba Corp | Semiconductor power conversion equipment |
| JP2016123159A (en) * | 2014-12-24 | 2016-07-07 | 株式会社東芝 | Electric power converter |
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