CN108832826B - MMC capacitor voltage balance control method suitable for FPGA - Google Patents

MMC capacitor voltage balance control method suitable for FPGA Download PDF

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CN108832826B
CN108832826B CN201810513480.XA CN201810513480A CN108832826B CN 108832826 B CN108832826 B CN 108832826B CN 201810513480 A CN201810513480 A CN 201810513480A CN 108832826 B CN108832826 B CN 108832826B
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capacitor voltage
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CN108832826A (en
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孙吉波
王宇
杨银国
刘崇茹
钱峰
凌博文
徐春华
包博
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North China Electric Power University
Electric Power Dispatch Control Center of Guangdong Power Grid Co Ltd
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Electric Power Dispatch Control Center of Guangdong Power Grid Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4835—Converters with outputs that each can have more than two voltages levels comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage

Abstract

The invention discloses an MMC (modular multilevel converter) capacitor voltage balance control method suitable for an FPGA (field programmable gate array), belonging to the technical field of operation and control of an electric power system. The invention divides a plurality of subintervals according to the fluctuation range of the capacitance voltage during normal operation, matches the sub-modules into corresponding subinterval groups according to the capacitance voltage acquired in real time, and further determines the reading sequence of each group according to the current direction of the bridge arm. Meanwhile, when grouping, the switching frequency of the device is further reduced by considering the switching state of the previous moment aiming at the sub-modules of which the capacitor voltage is close to the rated value and following the principle of keeping the original state unchanged as much as possible. The invention has the advantages that the sequencing of the sub-module capacitor voltage is avoided, the quick voltage-sharing control can be realized on the premise of ensuring the voltage-sharing control effect of the sub-modules, and the switching frequency of the device can be reduced.

Description

MMC capacitor voltage balance control method suitable for FPGA
Technical Field
The invention belongs to the technical field of operation and control of power systems, and particularly relates to an MMC capacitor voltage balance control method suitable for an FPGA.
Background
A Modular Multilevel Converter (MMC) is a novel Voltage Source Converter (VSC) designed by adopting a modular structure. Compared with the traditional converters with two-level and three-level topological structures, the topological structure of the MMC sub-module (SM) cascade connection has the advantages of low switching frequency, good output waveform quality, low requirement on switch consistency, good expansibility and the like, becomes a research hotspot in the field of flexible direct current transmission, and obtains more and more engineering applications.
MMC direct current side voltage relies on the electric capacity of dispersion in each submodule piece to provide the support, and submodule piece electric capacity voltage balance is the important prerequisite of MMC steady operation. In actual engineering, in order to obtain higher voltage level and transmission capacity, a single bridge arm usually comprises hundreds of sub-modules, and the acquisition of capacitance and voltage-sharing control calculation of a large number of sub-modules puts higher requirements on the performance of a controller. Therefore, in engineering, a Field Programmable Gate Array (FPGA) with a parallel architecture is generally used for valve level control, that is, sub-module capacitor voltage equalization and trigger pulse generation.
However, even if a high-performance controller such as an FPGA is used, the conventional voltage-sharing control method needs to sequence all capacitor voltages of the sub-modules of the same bridge arm, and then determines the sub-modules to be switched on according to the number of the sub-modules to be switched on and the current direction of the bridge arm, which are output by the upper layer control. When the bridge arm current is in the charging direction, starting triggering from the submodule with lower voltage; and when the bridge arm current is in the discharging direction, starting triggering from the submodule with higher voltage. In the traditional method, on one hand, the calculation amount of sequencing is large, and on the other hand, the repeated switching of the sub-modules can be caused by the small change of the capacitor voltage, so that high switching loss is caused.
In view of this, the invention designs a capacitor voltage balance control method of a modular multilevel converter suitable for a field programmable gate array, which can realize rapid voltage balance control and reduce the switching frequency of devices on the premise of ensuring the voltage balance control effect of sub-modules.
Disclosure of Invention
According to the problems mentioned in the background art, the invention discloses an MMC capacitor voltage balance control method suitable for an FPGA, which is characterized by comprising the following steps:
step 1: according toSetting the fluctuation range of the capacitor voltage in normal operation, and setting the upper limit U of the capacitor voltageMAXAnd lower limit UMIN；
Step 2: dividing the sub-modules into M + N groups according to the voltage of the capacitor and the switching state of the last moment, wherein the M + N groups comprise 2N groups of sub-modules considering the switching state of the last moment;
and step 3: according to the sub-module capacitance voltage value U acquired in real timeC(i) Matching the sub-modules into corresponding sub-interval groups (i is more than or equal to 1 and less than or equal to n) and the switch state FP (i) at the last moment (i is more than or equal to 1 and less than or equal to n), and recording the serial numbers of the sub-modules of each group;
and 4, step 4: determining the reading sequence of each group according to the current direction of the current bridge arm;
and 5: according to the number n of the submodules to be put intoonN output first in the reading order determined in step 4onThe submodules are conducted, and the rest n-nonThe sub-module is turned off.
In the step 1, the upper limit of the voltage UMAXAnd lower voltage limit UMINIs preset and respectively set as an overvoltage protection setting value and an undervoltage protection setting value of the capacitance voltage of the MMC valve control submodule, and the capacitance voltage of the normally operated submodule is in UMIN,UMAX]Within the interval.
In step 2, the sub-modules are grouped according to the principle that [ U ] is firstly groupedMIN,UMAX]The intervals are equally divided into M-2 groups, and then the corresponding subinterval layer heights are:
Figure BDA0001673275120000021
the demarcation threshold between the ith group and the (i + 1) th group is:
UTH(i)＝UMIN+(i-1)ΔU (2)
the condition that the sub-module capacitor voltage exceeds U (U) under the condition that the MMC is started or stopped or has a fault or the like in the terminal is consideredMIN,UMAX]The interval condition, so the capacitor voltage is larger than the upper limit and smaller than the lower limit, and the capacitor voltage is divided into M groups according to the voltage, and the sub-module switching frequency is reducedThe rate is used as a further optimization object; for N groups of the capacitor voltage near the rated value, the trigger state of the sub-module at the previous time is considered in the grouping process, and the N groups are further expanded into N groups of the turned-on sub-modules and N groups of the turned-off sub-modules, so that the sub-modules considering the switch state at the previous time have 2N groups, and all the sub-modules count M + N groups.
In the step 3, the sub-modules are matched with the groups in a way that the parallel characteristic of the FPGA is utilized, the received capacitor voltage of the sub-modules does not need to be stored, the sub-modules are directly compared with the M-1 inter-group boundary threshold value in a pipeline form synchronously and in parallel, and the groups corresponding to the corresponding sub-modules are determined according to the comparison result.
In the step 3, recording the numbers of the sub-modules of each group is realized by adopting a first-in first-out register, and each group corresponds to one FIFO; according to the capacitor voltage UC(i) And UTH(1)～UTH(M-1) determining corresponding FIFO groups through a lookup table according to the comparison result, enabling write-in signals of the corresponding FIFO groups, and writing the sub-module number i (i is more than or equal to 1 and less than or equal to n) into the FIFO;
bit width of FIFO write data is not less than
Figure BDA0001673275120000022
And the data depth of the FIFO is not less than the number n of the submodules of the bridge arm.
The reading order of the respective packets is divided into two cases,
when the bridge arm current direction charges the sub-module capacitor, reading the capacitor voltage from the group with lower capacitor voltage to the group with higher capacitor voltage in sequence;
when the bridge arm current direction discharges the sub-module capacitor, reading the capacitor voltage from the group with higher capacitor voltage to the group with lower capacitor voltage in sequence;
in the above two cases, for 2N groups of sub-modules considering the switching state at the previous time, the sub-module group turned on at the previous time is preferentially read.
In the step 5, the number n of the submodules to be put intoonFrom the upper control, the upper control is polar control, which means that the outer ring control is includedThe upper layer control generates the number n of sub-modules to be conducted of each bridge arm through calculationONAnd passed to the underlying control.
In the step 5, the conduction refers to T of the current sub-module1＝1，T2When the voltage is equal to 0, placing a capacitor in a charge-discharge loop of the bridge arm; is turned off when T1＝0，T2When the capacitance is 1, the capacitance is bypassed and is not charged and discharged.
The invention is characterized in that the parallel characteristic of the FPGA is fully utilized, and the approximate distribution of the capacitance voltage can be obtained through grouping and a set matching rule, so that the capacitance voltage of the submodule does not need to be sequenced, and the processing speed is improved. Meanwhile, for the sub-modules with the capacitance voltage near the rated value, the switching state at the last moment is considered during grouping, the principle that the original state is kept unchanged as much as possible is followed, the switching frequency of the power electronic device is reduced, and the operation economy of the MMC is improved.
Drawings
FIG. 1a is a system model diagram of an MMC in an embodiment of the MMC capacitor voltage equalization control method for an FPGA of the present invention;
FIG. 1b is a block diagram of sub-modules in an embodiment of the present invention;
FIG. 2 is a flow chart of sub-module grouping implementation in an embodiment of the invention;
FIG. 3 is a diagram illustrating a sequence of reading each group when the bridge arm current is in the capacitor charging direction according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a sequence of reading each group when the bridge arm current is in the capacitor discharging direction according to an embodiment of the present invention;
fig. 5 is a waveform of the capacitor voltage of the upper arm of phase a in the embodiment of the present invention.
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the attached drawings and specific examples.
As shown in fig. 1a, in the present embodiment, the MMC is built on a real-time digital simulator (RTDS), and a single-ended MMC system is adopted to verify the design of the present inventionA voltage-sharing control method. The Modular multilevel Converter MMC (Modular Multi-level Converter) used in this embodiment is a bridge-type topology structure, where n Submodules (SM) are respectively connected in series to an upper bridge arm and a lower bridge arm, and the upper bridge arm and the lower bridge arm respectively pass through respective reactors (L)0) Is connected with a three-phase alternating current power supply;
as shown in fig. 1b, the sub-module (SM) is composed of a half bridge (T1, T2) composed of 2 power electronic devices, 2 antiparallel diodes (D1, D2) and a dc energy storage capacitor (C), the 2 power electronic devices constitute a series structure, and two ends of each of the two series connected power electronic devices are connected in parallel with a diode in an antiparallel manner; each submodule is a two-terminal element and can realize conversion between full module voltage and 0 voltage through a switch under the condition of 2-direction current; according to different current directions, the charging and discharging of the capacitor can be realized.
The system parameters of the single-ended MMC are shown in table 1:
TABLE 1 MMC experimental system Main Circuit parameters
Figure BDA0001673275120000031
Figure BDA0001673275120000041
In the example, an ML605 development board produced by Xilinx is used, a Virtex-6 series FPGA chip is equipped on the board, a single board card is used to realize voltage-sharing control of 6 corresponding bridge arms, the adopted system clock is 100MHz, and the valve control period is 10 us.
As shown in fig. 2, the specific implementation method of the present invention is as follows:
step 1: setting the upper limit U of the capacitor voltage according to the fluctuation range of the capacitor voltage in normal operationMAXAnd lower limit UMIN(ii) a I.e. determining the upper limit U of the capacitor voltageMAXAnd lower limit UMIN；
In this example UMAX＝2.2kV，UMIN＝1.8kV。
Step 2: according to the capacitor voltage and the last time switch stateThe modules are divided into M + N groups; wherein the grouping principle is that firstly [ U ] is adoptedMIN,UMAX]The intervals are equally divided into M-2 groups, and then the corresponding subinterval layer heights are:
Figure BDA0001673275120000042
the demarcation threshold between the ith group and the (i + 1) th group is:
UTH(i)＝UMIN+(i-1)ΔU (2)
the condition that the sub-module capacitor voltage exceeds U (U) under the condition that the MMC is started or stopped or has a fault or the like in the terminal is consideredMIN,UMAX]In the case of the interval, the capacitor voltage is larger than the upper limit and smaller than the lower limit, and therefore, the capacitor voltage occupies one group, and the capacitor voltage can be divided into M groups in total according to the voltage. In addition, the rated value U for the capacitor voltageCREFThe capacitance voltage of the nearby sub-modules has already achieved a good balancing effect, so that the switching frequency of the sub-modules can be reduced as a further optimization target. The method comprises the steps of selecting N groups of groups corresponding to N groups of capacitor voltages near a rated value, considering the trigger state of a submodule at the previous moment in the grouping process, further expanding the N groups into N groups of conducted submodules and N groups of turned-off submodules, wherein the submodules are divided into M + N groups, and the submodules considering the switch state at the previous moment are divided into 2N groups.
In this example, M is 20 and N is 2. Accordingly, the layer height Δ U of each subinterval is calculated to be 0.0222kV according to equation (1). The demarcation threshold between the jth group and the jth +1 group can be obtained according to equation (2): u shapeTH(j)＝1.8+0.0222×(j-1)kV(1≤j≤M-1)。
And step 3: according to the sub-module capacitance voltage value U acquired in real timeC(i) Matching the sub-modules into corresponding sub-interval groups (i is more than or equal to 1 and less than or equal to n) and the switch state FP (i) at the last moment (i is more than or equal to 1 and less than or equal to n), and recording the serial numbers of the sub-modules of each group; the matching mode of the sub-modules and each group is that the parallel characteristic of the FPGA is utilized, the received capacitor voltage of the sub-modules does not need to be stored, and the sub-modules are directly compared with the M-1 inter-group boundary threshold value synchronously and parallelly in a pipeline mode. The comparison is realized by a comparatorEach comparator contains two inputs, one of which is a given threshold and the other of which is the sub-module capacitance voltage value collected in real time. And determining the corresponding grouping of the corresponding sub-modules according to the comparison result, thereby avoiding the step of comparison and re-exchange which are carried out in a circulating manner in a sequencing algorithm and quickly obtaining the sub-module numbering sequence with the capacitance and voltage arrangement.
Recording the sub-module number of each packet can be implemented by using a First Input First Output (FIFO), and each packet corresponds to one FIFO. According to the capacitor voltage UC(i) And UTH(1)～UTH(M-1) determining the corresponding FIFO grouping according to the comparison result, enabling the write-in signal of the FIFO grouping, and writing the submodule number i (i is more than or equal to 1 and less than or equal to n) into the FIFO. Because the comparison result and the corresponding grouping have one-to-one correspondence, the FIFO grouping which actually corresponds to the FIFO grouping is determined by adopting a lookup table mode.
When the comparison result shows that the submodules are positioned in the N groups above and below the rated value, the on-off state of the submodule at the previous moment is further taken into account, namely the submodule conducted at the previous moment is written into the FIFOONOff submodule write FIFOOFF。
For example, when UC(i)>UTH(j) The output of the comparison result is 1; on the contrary, when U isC(i)≤UTH(j) The comparison result is output as 0. Assume that in the 1 st clock cycle, the 1 st sub-module and UTH(1)～UTH(M-1) As a result of comparison
Figure BDA0001673275120000051
Namely UC(1) Is only greater than UTH(1) Then write 1 into FIFO2. Assume that at the 2 nd clock cycle, the 2 nd sub-module and UTH(1)～UTH(M-1) As a result of comparison
Figure BDA0001673275120000052
UC(2) Less than all thresholds, then UTH(1) I.e. then write 2 into FIFO1。
For a single bridge arm containing n sub-modules, each sub-module is codedThe binary bit width corresponding to the number is
Figure BDA0001673275120000053
(
Figure BDA0001673275120000054
As a function of rounding up) so that the bit width of the FIFO write data should not be less than
Figure BDA0001673275120000055
Meanwhile, under the condition of good voltage-sharing effect of the capacitor, all the submodules may fall into the same group, so that the data depth of the FIFO is not lower than the number n of the bridge arm submodules.
According to packet matching rules, FIFOiThe capacitor voltage of the sub-modules in (1) is less than FIFOi+1The aim of the capacitor voltage balance control is to keep the capacitor voltage of each submodule close to a rated value; for 2N packets around the nominal value, considering the switching state at the previous moment, the FIFO is preferentially readON。
Therefore, as shown in fig. 3, when the bridge arm current charges the sub-module capacitor, the number of the sub-module in the FIFO is read from bottom to top; as shown in fig. 4, when the bridge arm current discharges the sub-module capacitance, the sub-module number in the FIFO is read from top to bottom,
and 4, step 4: determining the reading sequence of each group according to the current direction of the current bridge arm; when the bridge arm current direction charges the sub-module capacitor, reading the groups with lower capacitor voltage to the groups with higher capacitor voltage in sequence; when the bridge arm current direction discharges the sub-module capacitors, the groups with higher capacitor voltage are sequentially read to the groups with lower capacitor voltage. On the basis of the principle, aiming at 2N groups of sub-modules considering the switching state at the previous moment, the sub-module groups turned on at the previous moment are preferentially read, so that the sub-modules with the capacitance voltage near the rated value are promoted to maintain the original switching state as far as possible, and the switching frequency of the device is reduced.
And 5: according to the number n of the submodules to be put intoonAccording to the reading order determined in step 4N output firstonThe submodules are conducted, and the rest n-nonThe sub-module is switched off; wherein the number n of the submodules to be put intoonThe upper-layer control is a polar control and refers to four control links including outer ring control, inner ring control, circulation suppression and nearest level modulation, and the upper-layer control generates the number n of sub-modules to be conducted of each bridge arm through calculationONAnd passed to the underlying control.
In the step, after the upper layer control finishes the control calculation, the number n of the sub-modules to be conducted of each bridge arm is finally generatedonAnd passed to the underlying control. The bottom layer control is based on the number n of the submodules to be conductedonSelecting a finally-switched-in sub-module and a switched-off sub-module according to the bridge arm current direction and the sub-module capacitance voltage, applying a switching-on control signal and a switching-off control signal, and completing closed-loop control on the MMC by upper-layer control and bottom-layer control together; compared with the upper layer control, the core of the invention belongs to the bottom layer control, also called valve control.
In this step, the conduction is T of the submodule in FIG. 11＝1，T2When the voltage is equal to 0, placing a capacitor in a charge-discharge loop of the bridge arm; is turned off when T1＝0，T2When the capacitance is 1, the capacitance is bypassed and is not charged and discharged.
As shown in fig. 5, in the simulation experiment waveform of the a-phase upper arm capacitor voltage collected in this example, it can be seen that the fluctuation amount of the sub-module capacitor voltage is about 3.90% of the rated value, and the control effect is good. The correctness of the capacitance voltage balance control method realized by using the FPGA is verified. Table 2 compares the performance of the conventional pressure equalization process and the inventive process when N is 0. When the traditional voltage-sharing control method is adopted, the capacitor voltage of the submodules can be kept well balanced, the fluctuation rate of the capacitor voltage is only 3.29%, but the corresponding switching frequency is as high as 5618Hz as all the submodules are completely sequenced in each control period. When the method is adopted for control, along with the increase of the grouping number M, the resolution effect on the difference of the capacitance and the voltage of the sub-modules is better and better, so that the fluctuation rate of the capacitance and the voltage is gradually reduced, but the switching frequency of the corresponding sub-modules is increased. When the number M of the packets is increased from 20 to 40, the fluctuation rate of the capacitor voltage is reduced from 3.90% to 3.57%, and the average switching frequency is increased from 424Hz to 996Hz, which is still far lower than that of the traditional method. It can be expected that the control effect of the capacitor voltage balance is closer to the traditional control method as M is continuously increased.
TABLE 2 pressure equalization method Performance comparison (N ═ 0)
Figure BDA0001673275120000061
Table 3 compares the performance of the conventional pressure equalization process and the inventive process at M ═ 20. When N is increased from 0 to 6, the fluctuation rate of the capacitor voltage is increased from 3.90% to 4.39%, and the corresponding average switching frequency is decreased from 424Hz to 119 Hz. Namely, with the increase of the N value, the switching frequency of the device can be further reduced on the premise of not remarkably sacrificing the voltage-sharing effect, and the remarkable optimization effect is achieved.
TABLE 3 pressure equalization method Performance comparison (M ═ 20)
Figure BDA0001673275120000071

Claims (6)

1. An MMC capacitor voltage balance control method suitable for an FPGA is characterized by comprising the following steps:
step 1: setting the upper limit U of the capacitor voltage according to the fluctuation range of the capacitor voltage in normal operationMAXAnd lower limit UMIN；
Step 2: dividing the sub-modules into M + N groups according to the voltage of the capacitor and the switching state of the last moment, wherein the M + N groups comprise 2N groups of sub-modules considering the switching state of the last moment;
and step 3: according to the sub-module capacitance voltage value U acquired in real timeC(i) And the switching state FP (i) at the previous moment, matching the sub-modules into corresponding sub-interval groups, and recording the serial number i of the sub-modules of each group, wherein i is more than or equal to 1 and less than or equal to n, and n is the number of the sub-modules of the bridge arm;
and 4, step 4: determining the reading sequence of each group according to the current direction of the current bridge arm;
and 5: according to the number n of the submodules to be put intoonN to be output first in the reading order of each packet determined in step 4onThe submodules are conducted, and the rest n-nonThe sub-module is switched off;
in step 2, the sub-modules are grouped according to the principle that [ U ] is firstly groupedMIN,UMAX]The intervals are equally divided into M-2 groups, and then the corresponding subinterval layer heights are:
Figure FDA0002625681440000011
the demarcation threshold between the ith group and the (i + 1) th group is:
UTH(i)＝UMIN+(i-1)ΔU (2)
the condition that the sub-module capacitor voltage exceeds U (U) under the condition that the MMC is started or stopped or has a fault or the like in the terminal is consideredMIN,UMAX]The voltage of the capacitor is larger than the upper limit and smaller than the lower limit, and the capacitor voltage is divided into M groups according to the voltage, and the switching frequency of the sub-modules is reduced to be used as a further optimization object; for N groups of the capacitor voltage near a rated value, considering the trigger state of the sub-module at the previous moment in the grouping process, and further expanding the N groups into N groups of the turned-on sub-modules and N groups of the turned-off sub-modules, so that the sub-modules considering the switching state at the previous moment have 2N groups, and all the sub-modules count M + N groups;
in the step 3, the sub-modules are matched with the groups in a way that the parallel characteristic of the FPGA is utilized, the received capacitor voltage of the sub-modules does not need to be stored, the sub-modules are directly compared with the M-1 inter-group boundary threshold value in a pipeline form synchronously and in parallel, and the groups corresponding to the corresponding sub-modules are determined according to the comparison result.
2. The MMC capacitor voltage balance control method for FPGA of claim 1, wherein in step 1, the upper voltage limit U is setMAXAnd lower voltage limit UMINAre preset, respectively setFor the overvoltage protection setting value and the undervoltage protection setting value of the MMC valve control submodule capacitor voltage, the normally running submodule capacitor voltage is in UMIN,UMAX]Within the interval.
3. The MMC capacitor voltage balance control method suitable for FPGA of claim 1, wherein in step 3, record each sub-module number of group is realized by using FIFO register, and each group corresponds to a FIFO; according to the capacitor voltage UC(i) And UTH(1)～UTH(M-1) determining corresponding FIFO groups through a lookup table according to the comparison result, enabling write-in signals of the corresponding FIFO groups, and writing the sub-module number i into the FIFO, wherein i is more than or equal to 1 and less than or equal to n;
bit width of FIFO write data is not less than
Figure FDA0002625681440000021
And the data depth of the FIFO is not less than the number n of the submodules of the bridge arm.
4. The MMC capacitor voltage balance control method for FPGA of claim 1, wherein the reading sequence of each group is divided into two cases,
when the bridge arm current direction charges the sub-module capacitor, reading the capacitor voltage from the group with lower capacitor voltage to the group with higher capacitor voltage in sequence;
when the bridge arm current direction discharges the sub-module capacitor, reading the capacitor voltage from the group with higher capacitor voltage to the group with lower capacitor voltage in sequence;
in the above two cases, for 2N groups of sub-modules considering the switching state at the previous time, the sub-module group turned on at the previous time is preferentially read.
5. The MMC capacitor voltage balance control method suitable for FPGA of claim 1, wherein in step 5, the number n of submodules to be put into useonThe control method is from an upper layer control which generates the guidance waiting of each bridge arm through calculationNumber n of general modulesONAnd the control is transmitted to the bottom layer control, and the upper layer control is the polar control, which means four control links including outer ring control, inner ring control, circulation suppression and nearest level modulation.
6. The MMC capacitor voltage balance control method for FPGA according to claim 1, wherein in step 5, the conducting means T of the current sub-module1＝1，T2When the voltage is equal to 0, placing a capacitor in a charge-discharge loop of the bridge arm; is turned off when T1＝0，T2When the capacitance is 1, the capacitance is bypassed and is not charged and discharged.
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