CN107070206A - A kind of quasi-resonant switching converter detected based on valley - Google Patents

A kind of quasi-resonant switching converter detected based on valley Download PDF

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Publication number
CN107070206A
CN107070206A CN201710364904.6A CN201710364904A CN107070206A CN 107070206 A CN107070206 A CN 107070206A CN 201710364904 A CN201710364904 A CN 201710364904A CN 107070206 A CN107070206 A CN 107070206A
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triode
connects
pmos
nmos tube
electrode
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CN107070206B (en
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周泽坤
张家豪
董瑞凯
石跃
王卓
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/175—Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention belongs to technical field of power management, a kind of quasi-resonant switching converter detected based on valley is particularly related to.The circuit of the present invention, which is mainly, makes switch converters approximate duty in boundary conduction mode, realizes Sofe Switch based on LC vibration design valley value detection circuits, power tube is realized no-voltage, Zero Current Switch, by the way that Q is greatly reducedGDCome solve conventional high-tension LED driving because switching loss is serious caused by hard switching the problem of, so as to reach the purpose of efficient operation.

Description

A kind of quasi-resonant switching converter detected based on valley
Technical field
The invention belongs to technical field of power management, a kind of quasi-resonant switching detected based on valley is particularly related to Converter.
Background technology
Switch converters are as a class circuit important in power management chip, with its wide output area, high conversion efficiency The features such as be widely used in the fields such as consumer electronics, industrial design, Aero-Space.
Switch converters are made up of switch controller and power stage circuit, and the circuit appropriate by designing controls power tube The voltage or electric current for being switched on and off making its output offer constant are load supplying.For example when load is LED, switch converters Constant current is exported, LED maintains brightness constant, as shown in Figure 1.
Traditional LED is driven to hard switching, i.e., detected by peak value and valley to inductive current, to control power tube On off state, constantly to output capacitance discharge and recharge to realize the low current ripple of LED.But the LED of hard switching driving meetings The problem of there is surge current：Open power tube when system detectio is down to valley to inductive current, power tube drain potential by Vi+VF moments under freewheeling state are pulled to ground level.Because there is the equivalent parasitic capacitance to ground, then work(in the drain electrode of power tube The electric charge that rate pipe is opened in moment parasitic capacitance is poured in power tube, is poured into very big surge current, is caused larger power to damage Consumption, it is also possible to burning for power tube can be caused, this point will become more apparent with the rise of applied voltage.This has resulted in tradition LED drivings reliability is relatively low, and power is the problem of be difficult to do big.
The content of the invention
The purpose of the present invention, is exported and low reliable to solve low-power of the tradition LED drivings caused by hard switching Property the problem of, the present invention propose it is a kind of based on valley detect quasi-resonant switching converter.
The technical scheme is that：A kind of quasi-resonant switching converter detected based on valley, including power stage topology, Peak point current sampling module and valley detection module；Characterized in that,
The power stage topology is made up of power tube, Schottky diode, inductance, output capacitance and load；Output capacitance In parallel with load, the anode of load is connected with power supply and Schottky diode negative terminal, and the negative terminal of load is followed by Xiao Te by inductance The drain electrode of the anode and power tube of based diode；
The peak point current sampling module is made up of sampling resistor and electric current limit comparator；Sampling resistor is connected across power tube Between source electrode and ground, electric current limit comparator negative terminal connects power tube source electrode, just terminates reference voltage, and output connects power tube driving mould Block；
The valley detection module includes the first PMOS M1, the second PMOS M2, the 3rd PMOS M5, the 4th PMOS M8, the 5th PMOS M9, the tenth PMOS M10, the first NMOS tube M3, the second NMOS tube M4, the 3rd NMOS tube M6, the 4th NMOS Pipe M7, the 5th NMOS tube M11, the first triode Q1, the second triode Q2, the 3rd triode Q3, the 4th triode Q4, the five or three Pole pipe Q5, the 6th triode Q6, the 7th triode Q7, the 8th triode Q8, the first current source, the second current source, the first electric current It is comparator, the second current comparator, the first electric capacity, the second electric capacity, the 3rd electric capacity, the first phase inverter, the second phase inverter, the 3rd anti- Phase device, the 4th phase inverter, the 5th phase inverter, d type flip flop, the 3rd current source, the 6th NMOS tube and the 7th NMOS tube；Wherein,
First PMOS M1 source electrode connects power supply, its grid and drain interconnection, and its drain electrode connects the first current source；
Second PMOS M2 source electrode connects power supply, and its grid connects the first PMOS M1 drain electrode；First NMOS tube M3 leakage Pole and grid connect the second PMOS M2 drain electrode, and the first triode Q1 colelctor electrode and base stage connect the first NMOS tube M3 source electrode, Second triode Q2 colelctor electrode and base stage connects, the first triode Q1 emitter stage, the second triode Q2 grounded emitter；
3rd PMOS M5 source electrode connects power supply, and its grid connects the first PMOS M1 drain electrode；3rd NMOS tube M6 leakage Pole connects power supply, and its grid connects the 4th PMOS M8 drain electrode；3rd PMOS M5 drain electrode and the 3rd NMOS tube M6 source electrode connect The colelctor electrode for being followed by the 3rd triode Q3 is connect, the 3rd triode Q3 base stage connects the first NMOS tube M3 source electrode, the 3rd triode Q3 emitter stage connects the second current source；
Second NMOS tube M4 drain electrode connects power supply, and its grid connects the second PMOS M2 drain electrode；8th triode Q8 hair Emitter-base bandgap grading connects power supply, and its base stage connects the 7th triode Q7 colelctor electrode, the second NMOS tube M4 source electrode and the 8th triode Q8 collection Electrode connects the colelctor electrode for being followed by the 4th triode Q4, the second NMOS tube M4 source electrodes, the 8th triode Q8 colelctor electrodes and the four or three The tie point of pole pipe Q4 colelctor electrodes after the second electric capacity by being grounded；4th triode Q4 emitter stages connect the 5th triode Q5 current collection Pole and base stage, the 5th triode Q5 grounded emitter；The company of 4th triode Q4 emitter stages and the 5th triode Q5 colelctor electrodes Contact connects the tie point of the 3rd triode Q3 emitter stages and the second current source；
7th triode Q7 emitter stage connects power supply, and its base stage and colelctor electrode interconnection, its base stage connect the 8th triode Q8's Base stage；7th triode Q7 colelctor electrode connects the 6th triode Q6 colelctor electrode, and the 6th triode Q6 base stage connects the five or three pole Pipe Q5 base stage, the 6th triode Q6 grounded emitter；
4th PMOS M8 source electrode connects power supply, and its grid connects the first PMOS M1 drain electrode；4th NMOS tube M7 leakage Pole connects the 4th PMOS M8 drain electrode, and the 4th NMOS tube M7 grid connects the 3rd PMOS M5 drain electrodes, the 3rd NMOS tube M6 source electrodes With the tie point of the 3rd triode Q3 colelctor electrodes, the 4th NMOS tube M7 source ground；
5th PMOS M9 source electrode connects power supply, and its grid connects the first PMOS M1 drain electrode；Tenth PMOS M10 source Pole connects the 5th PMOS M9 drain electrode, and the tenth PMOS M10 grid connects the 4th PMOS M8 drain electrode；5th NMOS tube M11 Drain electrode connect the tenth PMOS M10 drain electrode, the 5th NMOS tube M11 grid connects the 4th PMOS M8 drain electrode, the 5th NMOS Pipe M11 source ground；
The normal phase input end of first current comparator connects the second reference voltage source, and its anti-phase input terminates the 8th triode Q8 Colelctor electrode；The normal phase input end of second current comparator connects the first reference voltage source, and its anti-phase input terminates the 8th triode Q8 colelctor electrode；
The output end of input the second current comparator of termination of first phase inverter, the output termination the 6th of the first phase inverter The grid of NMOS tube, the drain electrode of the 6th NMOS tube connects the 3rd current source, the drain electrode of the 6th NMOS tube and the tie point of the 3rd current source By being grounded after the 3rd electric capacity；The tie point of the drain electrode of 6th NMOS tube, the 3rd current source and the 3rd electric capacity connects the second phase inverter Input；
The drain electrode of 7th NMOS tube connects the drain electrode of the 6th NMOS tube, and the grid of the 7th NMOS tube connects the logic control of power tube Signal, its source ground；
The output end of first current comparator passes sequentially through the 3rd phase inverter and the 4th phase inverter be followed by d type flip flop D it is defeated Enter end；Tenth PMOS M10 drains and the tie points of the 5th NMOS tube M11 drain electrodes passes sequentially through the 5th phase inverter and the 6th anti-phase Device is followed by the clock signal input terminal of d type flip flop；The output termination d type flip flop for connecing the second phase inverter puts 1 signal end；D is triggered The Q output of device connects power tube drive module.
The first reference voltage is more than the second reference voltage in such scheme.
The beneficial effects of the invention are as follows：The circuit of the present invention makes power tube realize no-voltage, Zero Current Switch, by significantly Reduction QGD come solve conventional high-tension LED driving because switching loss is serious caused by hard switching the problem of, so as to reach efficient work The purpose of work.
Brief description of the drawings
Fig. 1 tradition LED driving structure figures
Fig. 2 quasi-resonant switching transformer configuration figures proposed by the present invention
The valley value detection circuit figure of Fig. 3 present invention
(a) valley detection core circuit
(b) valley detection comparator
(c) valley detection logic control
The Sofe Switch waveform diagram of Fig. 4 present invention
Fig. 5 zero currents, ZVT design；
The actual circuit simulation waveform of Fig. 6 present invention.
Embodiment
Below in conjunction with the accompanying drawings, technical scheme is described in detail：
When power switch is in opening, the pressure drop of sampling resistor gradually increases with the rising of inductive current.When adopting When the voltage of sample resistance is equal to electric current limit comparator anode reference voltage, electric current limit comparator output voltage turns over low by height, Controller control power tube shut-offs.Hereafter the energy stored on inductance is discharged into defeated by Schottky diode as continued flow tube Go out on electric capacity and load.As inductive current is reduced to zero, its two terminal potential be intended to it is equal, due to load negative terminal current potential be Vi-VO, power tube drain potential finally also would tend to Vi-VO.However, due to the equivalent parasitic capacitance to ground of power tube and outer C, the equivalent capacity C of Schottky diode junction electric capacity formation are held in power-upDPresence, power tube drain potential can not be mutated, the electricity Hold and inductance formation LC vibrations.Timing at the time of inductive current is reduced to 0, power tube drain voltage and inductive current can divide It is not expressed as：
VDrain=(VIN-VO)+VOcosω0t
WhereinFor resonant frequency.Inductive current and voltage waveform are drawn as shown in Figure 4 respectively.
By above-mentioned analysis, power tube drain voltage is after inductive current drops to zero, discounting for parasitic electricity In the case of resistance, it may occur that sustained oscillation, the amplitude of concussion is VO.And in actual conditions, due to the presence of dead resistance, such as electricity DCR resistance, diode and power tube spurious impedance of sense etc., cause power tube drain voltage waveform actual for a damping vibration attenuation Waveform.But in a cycle, power tube drain voltage shock range still can be approximately VO.Therefore, in order to realize ZVS, it is necessary to Power tube drain electrode valley point voltage is set to no-voltage, i.e. VO=Vi/ 2, it is now 1/2 harmonic period, is designated as tValley；Simultaneously can be with See, inductive current is also zero at valley, realize ZCS, therefore system can be by detecting the valley point voltage of LC resonance come real Existing Sofe Switch, so as to effectively reduce the switching loss of power tube.
Valley value detection circuit is as shown in figure 3, MOSFET is in saturation region, and BJT is in quiescent current distribution during amplification region For：IM1=IM2=Ibias, IM1=k1IM5, IQ1=k2IQ3=k2IQ4, IQ5=IQ8=k3IQ6=k3IQ7.And k2>k1>k3.Work as inductance Electric current drops to zero, when resonance starts, CValleyDetect that electric current I is extracted in the change of power tube drain terminal current potentialValley, IValleyWith dVDrain/ dt increases and increased.Work as IValley≥IQ4+IQ3When, Q5Cut-off, IValley/2>IM5When L2Current potential is reduced.Now by M6Pipe And M7The negative-feedback of pipe formation is by L2Current potential is clamped to VTH7+VOV7。L2Current potential, which continues reduction, can cause by M9~M11It is anti-that pipe is formed Phase device is overturn, L3Current potential turns over low.
Now M7Pipe is with IValleyIncrease be transitioned into saturation region from linear zone.M in saturation region7Pipe has high-gain, So that gain around feedback is lifted, the quick adjustment of M6 tube grid current potentials is realized, I is offsetValley/ 2 increment, makes L2Electricity Position maintains to stablize relatively.
Work as IValley/ 2 in VDrainClose to valley, I is dropped toM5When following, L2Current potential is begun to ramp up, by M7Pipe is pressed into linear zone, M6Pipe ends, L3Current potential is by low high jump.Now the rising edge d type flip flop in Fig. 3 will sample the state, it is believed that be correctly detecting Valley point, digital Gate is sent to by con1 values this moment, the conducting power pipe after Driver is handled.
I is setQ8=IQ5, by L under stable state2It is set to high level, M4Pipe ends.After resonance starts, with IValleyGradually increase Greatly, Q is flowed through5Electric current will reduce formed objects amount, flow through Q8Electric current also with Q5Together reduce.Reach L1L after upset point1Open Begin to reduce, L1By C1Delay when dropping to REF2 con1 turn over height, inputted as d type flip flop, wait L3Power is opened after sampling Pipe.
On the other hand, when resonant frequency is too low, tValleyAccounting is larger in switch periods, and switch converters deviate BCM moulds Formula, causes ILEDWith Ipeak/ 2 deviations are larger.Therefore design con2 to limit lowest resonant frequency, in designed tValley (max) enforced opening power tube afterwards.Specific embodiment is：Work as IValleyWhen just starting increase, L1Current potential is reduced to REF1, Con2 turns over height therewith, and fixed current is to electric capacity C2Charging, starts timing；It is digital when being correctly detecting power tube drain terminal valley Gate turns over 1, electric capacity C2Rapid electric discharge, terminates timing.If in tValley(max) fail to detect power tube drain terminal valley in, then scheme Schmitt inverter upset in 3, by Q set, enforced opening power tube.L1Current potential continues to drop to after REF2, M4Pipe is turned on simultaneously Into saturation region, there is provided current canceling IValley/ 2 increment.Con1 keeps turning over high state during this period, waits L2Current potential it is upper Rise along correctly sampling the state.
Resonance starts rear L1、L2, con1, con2 situation of change provided by Fig. 5, wherein：Starting point is respectively 0 curve For IValley, the curve of monotone decreasing is power tube Drain terminal voltages.It (is second in bracket that 1~4 corresponding dotted line is represented respectively Situation when the identical designation dotted line of root occurs)：
1：L1Start to reduce (rise), con2 is turned over high (maintenance high level)；
2：Q5End (conducting)；
3：Con1 is turned over high (low)；
4：L2Reduce (rise).
The quasi resonant convertor simulation waveform implemented using such scheme is as shown in Figure 6.It is numeral respectively from top to bottom GATE signals, power tube drain terminal current potential, inductive current.It can be seen that, when inductive current drops to zero, resonance starts, power Pipe drain terminal voltage practically drops to zero, substantially reduces Driver to CGDCharging interval.Now power tube is opened, switching loss It is smaller, improved efficiency.It thus can further increase input voltage and switching frequency, so as to be issued to height in high-power output The purpose of efficiency.

Claims (1)

1. a kind of quasi-resonant switching converter detected based on valley, including power stage topology, peak point current sampling module and paddy It is worth detection module；Characterized in that,
The power stage topology is made up of power tube, Schottky diode, inductance, output capacitance and load；Output capacitance is with bearing Carry in parallel, the anode of load is connected with power supply and Schottky diode negative terminal, and the negative terminal of load is followed by Schottky two by inductance The drain electrode of the anode and power tube of pole pipe；
The peak point current sampling module is made up of sampling resistor and electric current limit comparator；Sampling resistor is connected across power tube source electrode Between ground, electric current limit comparator negative terminal connects power tube source electrode, just terminates reference voltage, and output connects power tube drive module；
The valley detection module include the first PMOS M1, the second PMOS M2, the 3rd PMOS M5, the 4th PMOS M8, 5th PMOS M9, the tenth PMOS M10, the first NMOS tube M3, the second NMOS tube M4, the 3rd NMOS tube M6, the 4th NMOS tube M7, the 5th NMOS tube M11, the first triode Q1, the second triode Q2, the 3rd triode Q3, the 4th triode Q4, the five or three pole Pipe Q5, the 6th triode Q6, the 7th triode Q7, the 8th triode Q8, the first current source, the second current source, the first electric current ratio Compared with device, the second current comparator, the first electric capacity, the second electric capacity, the 3rd electric capacity, the first phase inverter, the second phase inverter, the 3rd anti-phase Device, the 4th phase inverter, the 5th phase inverter, d type flip flop, the 3rd current source, the 6th NMOS tube and the 7th NMOS tube；Wherein,
First PMOS M1 source electrode connects power supply, its grid and drain interconnection, and its drain electrode connects the first current source；
Second PMOS M2 source electrode connects power supply, and its grid connects the first PMOS M1 drain electrode；First NMOS tube M3 drain electrode and Grid connects the second PMOS M2 drain electrode, and the first triode Q1 colelctor electrode and base stage connect the first NMOS tube M3 source electrode, second Triode Q2 colelctor electrode and base stage connects, the first triode Q1 emitter stage, the second triode Q2 grounded emitter；
3rd PMOS M5 source electrode connects power supply, and its grid connects the first PMOS M1 drain electrode；3rd NMOS tube M6 drain electrode connects Power supply, its grid connects the 4th PMOS M8 drain electrode；After 3rd PMOS M5 drain electrode and the 3rd NMOS tube M6 source electrode connection The 3rd triode Q3 colelctor electrode is connect, the 3rd triode Q3 base stage connects the first NMOS tube M3 source electrode, the 3rd triode Q3's Emitter stage connects the second current source；
Second NMOS tube M4 drain electrode connects power supply, and its grid connects the second PMOS M2 drain electrode；8th triode Q8 emitter stage Power supply is connect, its base stage connects the 7th triode Q7 colelctor electrode, the second NMOS tube M4 source electrode and the 8th triode Q8 colelctor electrode Connection is followed by the 4th triode Q4 colelctor electrode, the second NMOS tube M4 source electrodes, the 8th triode Q8 colelctor electrodes and the 4th triode The tie point of Q4 colelctor electrodes after the second electric capacity by being grounded；4th triode Q4 emitter stages connect the 5th triode Q5 colelctor electrode and Base stage, the 5th triode Q5 grounded emitter；The tie point of 4th triode Q4 emitter stages and the 5th triode Q5 colelctor electrodes Connect the tie point of the 3rd triode Q3 emitter stages and the second current source；
7th triode Q7 emitter stage connects power supply, and its base stage and colelctor electrode interconnection, its base stage connect the 8th triode Q8 base stage； 7th triode Q7 colelctor electrode connects the 6th triode Q6 colelctor electrode, and the 6th triode Q6 base stage connects the 5th triode Q5's Base stage, the 6th triode Q6 grounded emitter；
4th PMOS M8 source electrode connects power supply, and its grid connects the first PMOS M1 drain electrode；4th NMOS tube M7 drain electrode connects 4th PMOS M8 drain electrode, the 4th NMOS tube M7 grid connects the 3rd PMOS M5 drain electrodes, the 3rd NMOS tube M6 source electrodes and the The tie point of three triode Q3 colelctor electrodes, the 4th NMOS tube M7 source ground；
5th PMOS M9 source electrode connects power supply, and its grid connects the first PMOS M1 drain electrode；Tenth PMOS M10 source electrode connects 5th PMOS M9 drain electrode, the tenth PMOS M10 grid connects the 4th PMOS M8 drain electrode；5th NMOS tube M11 leakage Pole connects the tenth PMOS M10 drain electrode, and the 5th NMOS tube M11 grid connects the 4th PMOS M8 drain electrode, the 5th NMOS tube M11 Source ground；
The normal phase input end of first current comparator connects the second reference voltage source, and its anti-phase input terminates the 8th triode Q8 collection Electrode；The normal phase input end of second current comparator connects the first reference voltage source, and its anti-phase input terminates the 8th triode Q8's Colelctor electrode；
The output end of input the second current comparator of termination of first phase inverter, the output of the first phase inverter terminates the 6th NMOS tube Grid, the drain electrode of the 6th NMOS tube connects the 3rd current source, and the tie point of the drain electrode of the 6th NMOS tube and the 3rd current source passes through the It is grounded after three electric capacity；The tie point of the drain electrode of 6th NMOS tube, the 3rd current source and the 3rd electric capacity connects the input of the second phase inverter End；
The drain electrode of 7th NMOS tube connects the drain electrode of the 6th NMOS tube, and the grid of the 7th NMOS tube connects the logic control letter of power tube Number, its source ground；
The output end of first current comparator passes sequentially through the 3rd phase inverter and the 4th phase inverter is followed by the D inputs of d type flip flop； Tenth PMOS M10 drains to be passed sequentially through after the 5th phase inverter and hex inverter with the 5th NMOS tube M11 tie points drained Connect the clock signal input terminal of d type flip flop；The output termination d type flip flop for connecing the second phase inverter puts 1 signal end；The Q of d type flip flop Output termination power tube drive module.
CN201710364904.6A 2017-05-22 2017-05-22 A kind of quasi-resonant switching converter based on valley detection Expired - Fee Related CN107070206B (en)

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CN109327938A (en) * 2018-11-21 2019-02-12 电子科技大学 A kind of the inductive current valley detection method and constant current control method of LED drive circuit
CN109496008A (en) * 2017-09-12 2019-03-19 上海明石光电科技有限公司 LED drive circuit, LED electron rectifier and LED illumination device
CN117118203A (en) * 2023-10-24 2023-11-24 江苏展芯半导体技术有限公司 Step-down converter

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