CN107066707B - A kind of adjustable design method for tracing and device using snapshot - Google Patents
A kind of adjustable design method for tracing and device using snapshot Download PDFInfo
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The present invention proposes that a kind of adjustable using snapshot designs method for tracing and device, it is related to integrated circuit adjustable design field, the method comprising the steps of 1, the capacity of setting trace cache and snapshot caching, and the width of the width limitation and snapshot signal that determine trace signals limits；Step 2, it is limited according to the width of the trace signals and the snapshot signal, generates register cluster and iteration mask register cluster, so that it is determined that the trace signals and the snapshot signal；Step 3, according to the trace signals and the snapshot signal, setting tracking structure, wherein the tracking structure includes tracking controller, trigger, tracking bus, trace cache, snapshot caching.The present invention can significantly improve the state recovery rate of tune-up data, increase the observability of silicon post debugging, shorten the silicon post debugging time；Present invention may determine that the recovery key signal of property；The present invention can reduce the runing time of trace signals selection method.
Description
Technical field
The present invention relates to integrated circuit adjustable design field, in particular to a kind of adjustable using snapshot
Design method for tracing and device.
Background technique
With the increase of IC design complexity and the increase of Rapid Product pressure, adjustable is designed to silicon
The support technology of post debugging.Since design complexities are high, software analog rate is slow, Time Delay Model precision is low etc., factors are restricted, silicon
Preceding to verify the correctness that not can guarantee hardware design, some design mistakes are omitted to after silicon, or even after chip puts goods on the market
It is just found, brings about great losses, silicon post debugging is as one of Quality Control Links last before volume production, it may be verified that chip after flow
Correctness, and the mistake omitted before silicon is detected, positions and diagnoses, since chip observability is poor after flow, so that adjusting after silicon
Examination becomes the important bottleneck in lsi development process, or even needs to expend the development time of more than half, and adjustable is set
Meter assists the debug circuit of silicon post debugging by increasing in chip design stage, to improve the Observable of chip when silicon post debugging
Property, shorten the silicon post debugging time.
Adjustable based on tracking is configured as the design scheme of mainstream, can by increasing trace cache in the chips
The continuous real-time tracking capability clapped, and one of the major technique for having become silicon post debugging are provided in silicon post debugging, and extensively more
Applied to business etc. in processors, such as the processor and IBM Power series processors of ARM framework.One complete tracking
Design generally includes: trigger module, tracking controller, trace cache, as shown in Figure 1.Trigger module is for monitoring in debugging
Trigger event or trigger sequence, when specified trigger event or sequence generation, trigger unit can monitor triggering information simultaneously
Inform tracking controller.Tracking controller receives the trigger signal of trigger module, open signal tracking, by tracking data storage
Into trace cache.Tracking controller can also configure the tuning parameters such as the trigger event in trigger unit according to debugging demand.
Trace cache can real-time storage tracking data.After trace cache is filled with tracking data, the data in trace cache can be passed through
Debugging interface is output to outside piece, to restore and mistake debugging for subsequent state.
The method of the existing tracking design of industry is the important function signal or related to processor instruction stream of selection
Function signal, and by these function signals by debug bus be connected on trace cache.Such as the debugging framework of ARM is general
It is in caching the storage such as the location counter of processor, instruction to on-chip trace.Such methods facilitate the tune of software level
Examination, but the debugging of circuit staging error is helped it is limited, how after flow it is fine-grained it is accurate search, diagnosis and Position Design it is wrong
Accidentally become the bottleneck of silicon post debugging.
State recovery is the major technique of circuit-level error detection and localization, is restored using known circuit logic state
The method of unknown circuit logic state restores the state value for knowing more circuits internal signal by state, to improve electricity
The observability on road assists diagnosis and positioning wrong in silicon post debugging.The basic principle is that utilizing the logic function of logic unit
It can be carried out logical derivation, restore unknown signaling state using known signal state.Usually there are three types of the recovery policies of logic gate: preceding
It is backward to restore and combine to restore to recovery.Forward direction restores to be the output for inferring logic gate using the input of logic gate, backward to restore
It is the input for inferring logic gate using the output of logic gate, combines the output and part restored be in conjunction with logic gate and input and infer not
The input known.These recovery operations are as shown in Figure 2.For sequential logic gate, operation also can be recovered, but need to consider timing
Relationship.Restore principle using these, state can be constructed and restore simulator, the tracking data that it is obtained using trace cache are as defeated
Enter, the data for restoring not track are compared to know more gate leve signal conditions by the data obtained with analog simulation
Compared with, can circuit-level detect, positioning and diagnosis silicon before design mistake.State recovery rate is evaluation trace signals to not tracking
The index of signaling protein14-3-3 ability.State recovery rate is defined as: all known buffer status is total after state is restored
The ratio of the total number for the buffer status that number and tracking obtain.In same number of trace signals and same tracking period
Under, state recovery rate is big, and more with regard to representing the internal register state that can be known, internal observability is just bigger, more has
Help the debugging of circuit staging error.
Domestic and international researcher proposes through parser circuitry and therefrom selects certain to restore important signal for state and make
For trace signals, i.e., in the selection of trace signals using the trace signals selection method based on state recovery rate, and will track
Signal is connected on trace cache by tracking bus and multiplex networks.It is relevant to debugging when the tracking period starts
The data of trace signals are stored in trace cache.Within the tracking period, each beat of data of trace signals is stored in
In trace cache, until trace cache does not have vacant memory space.In tune-up data analysis, need to will be deposited in trace cache
The tracking data export of each clock cycle of storage, and state recovery is carried out, to assist the debugging of mistake.It studies at present more
The trace signals selection method based on state recovery rate, be broadly divided into two classes: trace signals based on probability selection and being based on
The trace signals of simulation select.Selection method based on probability is tied by comprehensively considering the topology of the combinational circuit between register
The logical implication of structure and logic gate using probability analysis method estimated state recovery rate, and iteratively selects so that state is restored
Rate reaches maximum trace signals.Selection method based on simulation goes predicted state recovery rate using actual analogue data, and
Trace signals are selected with this.
Existing state recovery method only carries out logical derivation from the topological structure of simple combinational circuit, is limited to complexity
Logical construction, state recovery rate is low, limited to the help of silicon post debugging.The existing debugging technique restored based on state is to chase after
Tracking data of the track signal within the tracking period pass through the logical derivation of logic gate, the recovery of iteration as known signal
Other signals, signaling protein14-3-3 are the recovery operations of logic-based door, for complicated logic gate structure, such as multi input with
Nor gate, the probability for restoring other unknown signalings using individually known input or output are lower.The method is limited to combination and patrols
The logical complexity of the structure and basic logical gate collected carries out the shape that state is restored using trace signals in complicated circuit
State recovery rate is low.
In addition, cannot to obtain within a short period of time high state extensive for the existing trace signals selection method restored based on state
The trace signals of multiple rate.The method speed of service based on probability is fast, but probability Estimation precision is low, and obtained state recovery rate is compared with mould
Quasi- method is low；Method based on simulation can obtain higher state recovery rate, but runing time is too long.These deficiencies constrain base
In the selection method utilization in practice of state recovery rate.
Summary of the invention
In view of the deficiencies of the prior art, the present invention proposes that a kind of adjustable using snapshot designs method for tracing and dress
It sets.
The present invention proposes that a kind of adjustable using snapshot designs method for tracing, comprising:
Step 1, the capacity of setting trace cache and snapshot caching determines width limitation and the snapshot signal of trace signals
Width limitation；
Step 2, it is limited according to the width of the trace signals and the snapshot signal, generates register cluster and iteration selection
Register cluster, so that it is determined that the trace signals and the snapshot signal；
Step 3, according to the trace signals and the snapshot signal, setting tracking structure, wherein the tracking structure packet
Include tracking controller, trigger, tracking bus, trace cache, snapshot caching.
For the trace cache for storing the trace signals, the trace cache includes the width and depth of trace cache
Degree, wherein the width is to track the signal numbers of the trace signals simultaneously, the depth be track the trace signals when
Clock periodicity.
The snapshot caching, for storing the snapshot signal, wherein the snapshot signal is connected by transmission network
Onto snapshot caching.
It include cluster snapshot in the snapshot signal, wherein the tufted state is register in all clusters in present clock period
State set.
It further include selection trace signals step, wherein register cluster is generated by sweep forward, estimates each deposit
Device cluster bring global state recovery rate, and select to improve the state recovery rate most register clusters as tracking cluster,
And it regard cluster input as trace signals, register is as snapshot signal in the cluster of register cluster, until the width of trace signals is pre-
If threshold value.
The present invention also proposes that a kind of adjustable using snapshot designs follow-up mechanism, comprising:
It determines that width limits module, for the capacity of trace cache and snapshot caching to be arranged, determines the width of trace signals
Limitation and the width of snapshot signal limit；
It determines signaling module, for limiting according to the width of the trace signals and the snapshot signal, generates register
Cluster and iteration mask register cluster, so that it is determined that the trace signals and the snapshot signal；
Setting tracking construction module, for tracking structure to be arranged according to the trace signals and the snapshot signal, wherein
The tracking structure includes tracking controller, trigger, tracking bus, trace cache, snapshot caching.
For the trace cache for storing the trace signals, the trace cache includes the width and depth of trace cache
Degree, wherein the width is to track the signal numbers of the trace signals simultaneously, the depth be track the trace signals when
Clock periodicity.
The snapshot caching, for storing the snapshot signal, wherein the snapshot signal is connected by transmission network
Onto snapshot caching.
It include cluster snapshot in the snapshot signal, wherein the tufted state is register in all clusters in present clock period
State set.
It further include selection trace signals module, wherein register cluster is generated by sweep forward, estimates each deposit
Device cluster bring global state recovery rate, and select to improve the state recovery rate most register clusters as tracking cluster,
And it regard cluster input as trace signals, register is as snapshot signal in the cluster of register cluster, until the width of trace signals is pre-
If threshold value.
As it can be seen from the above scheme the present invention has the advantages that
First point, the present invention can significantly improve the state recovery rate of tune-up data, increase the Observable of silicon post debugging
Property, shorten the silicon post debugging time.By tracking the input of snapshot signal and the original state of snapshot signal, present invention may determine that
Property recovers state value of the snapshot signal in entire debugging cycle, these state values for being resumed out can also recover it
His unknown signaling, to improve the state recovery rate of entire tracing scheme.
Second point, present invention may determine that the recovery key signal of property.In traditional tracking design and state restore, remove
Tracking data, other signals that can be resumed are extremely limited.The present invention is combined by obtaining the original state of snapshot signal
Trace signals deterministic can recover state of the snapshot signal within the tracking period.
Thirdly, the present invention can reduce the runing time of trace signals selection method.The present invention passes through mask register
Cluster, so that it is determined that trace signals and snapshot signal.It selects a register cluster that can determine multiple trace signals simultaneously, accelerates and chase after
The speed of track signal behavior.Since the selection time is short, it can be directed to selection result, carry out multiple iteration optimization.
Detailed description of the invention
Fig. 1 is the adjustable design framework figure based on tracking；
Fig. 2 is the exemplary diagram that state is restored；
Fig. 3 is the example circuit diagram that cluster restores；
Fig. 4 is the follow-up mechanism figure proposed by the present invention using snapshot；
Fig. 5 is snapshot tracking instance graph；
Fig. 6 is trace signals selection method flow chart；
Fig. 7 is the flow chart using the tracking design of snapshot.
Specific embodiment
The method that state using snapshot of the invention is restored specifically: for selected register cluster, in conjunction with register
The snapshot of register, i.e., the original state of register in cluster can recover entire in the cluster input of cluster and the cluster of register cluster
State of the register cluster within the entirely tracking period.One register cluster is several register groups by extracting in circuit at this
A little registers are known as register in cluster.Tufted state indicates that register is in the state set of present clock period, also referred to as cluster in all clusters
Snapshot, and forerunner's register of register is known as cluster input in cluster, and the forerunner of register in cluster is directly affected by combinational logic
It is originally inputted also referred to as cluster input.Fig. 3 show the register cluster extracted from circuit, it includes deposit in 4 clusters
Device, i.e. { B, C, D, E }, and cluster input set is { A }, by obtaining cluster original state and cluster input in the state in all tracking periods
Value, can recover register cluster the tufted state value in all tracking periods can because according to cluster original state and cluster initial input
To learn the tufted state in next tracking period, with this recursion, the tufted state in hereafter all tracking periods can be learnt, such as 1 institute of table
Show, if it is known that cluster original state, i.e., the known state of { B, C, D, E } in the period 0, and keep track cluster input, i.e., known A
In the value in period 0 to period 4, { B, C, D, E } can be recovered in the state in period 1 to 5 using these values, can recover and chase after
All tufted states in the track period, as shown in gray shade part in table 1, if taking traditional state recovery method, i.e., not
Using cluster original state, then selecting in Fig. 3 any 1 as trace signals, register cluster cannot be all recovered completely and is being chased after
The institute in track period is stateful.
Table 1
Relative to tradition tracking design, tracing scheme of the invention is significantly improved in hardware design, such as Fig. 4 institute
Show, the present invention needs to capture two distinct types of signal: trace signals and snapshot signal, and traditional tracking design does not capture
Snapshot signal, trace signals each cycle within the tracking period all needs to capture, and its original state is only captured for snapshot signal, is
Meet capture to require, tracking design scheme of the invention needs to increase snapshot caching, that is, shares two kinds of caching:
Trace cache and snapshot caching.
Trace cache is for storing trace signals, its general width and depth are limited, and width representative can chase after simultaneously
The signal number of track, depth represent the clock periodicity that can be tracked, such as: the trace cache of 16*1024 can be tracked simultaneously
16 trace signals, and keep track 1024 periods.
Snapshot caching is the newly-increased caching of tracking design of the invention, and to store snapshot signal, i.e. selected tracking is posted
The original state of storage cluster, selected snapshot signal are connected on snapshot caching by transmission network, the snapshot of each difference cluster
Signal can successively capture in the different tracking periods, if these register clusters do not have Temporal dependency relationship, and its snapshot
The sum of signal number is not more than the width of snapshot caching, then the snapshot of multiple register clusters can also capture simultaneously.
As shown in figure 5, the snapshot of three register clusters { A, B, C } is stored into snapshot caching, it can be three tracking periods
The snapshot of interior successive capture register cluster A, B and C can also capture register cluster if meeting snapshot caching wide constraint simultaneously
A, the snapshot of B and C.
Since snapshot signal improves state recovery rate in caching present invention uses snapshot, therefore corresponding trace signals select
Method also has change, can be decomposed into register cluster using the trace signals select permeability of snapshot and generate and register cluster selection
Problem, trace signals and snapshot signal are determined that, since debugging design overhead is limited, trace register cluster is same by trace register cluster
When need to meet trace signals width WTWith snapshot signal width WSConstraint.
Trace signals selection method using snapshot of the invention can be divided into two steps: the fasciation of register cluster at and register
Cluster selection, i.e., first by sweep forward generation register cluster, then estimate each register cluster can bring global state it is extensive
Multiple rate, and select to improve state recovery rate most clusters as tracking cluster, and regard cluster input as trace signals, deposit in cluster
Device is as snapshot signal, until the width of trace signals meets design requirement (i.e. width meets a preset threshold), trace signals
Selection method process is as shown in Figure 6.
Use the specific design procedure of the tracing scheme of snapshot are as follows:
Step 1: buffer memory capacity and signal bondage are determined.The capacity for designing trace cache and snapshot caching determines tracking letter
Number width limitation and snapshot signal width limit.
Step 2: trace signals and snapshot signal selection.It is limited according to the width of trace signals and snapshot signal, generation is posted
Storage cluster and iteration mask register cluster, so that it is determined that trace signals and snapshot signal.
Step 3: the whole tracking structure of design.It determines complete tracking scheduling scheme, designs entire tracking structure, including
Tracking controller, trigger, tracking bus, trace cache, snapshot caching etc..
The present invention also proposes that a kind of adjustable using snapshot designs follow-up mechanism, comprising:
It determines that width limits module, for the capacity of trace cache and snapshot caching to be arranged, determines the width of trace signals
Limitation and the width of snapshot signal limit；
It determines signaling module, for limiting according to the width of the trace signals and the snapshot signal, generates register
Cluster and iteration mask register cluster, so that it is determined that the trace signals and the snapshot signal；
Setting tracking construction module, for tracking structure to be arranged according to the trace signals and the snapshot signal, wherein
The tracking structure includes tracking controller, trigger, tracking bus, trace cache, snapshot caching.
For the trace cache for storing the trace signals, the trace cache includes the width and depth of trace cache
Degree, wherein the width is to track the signal numbers of the trace signals simultaneously, the depth be track the trace signals when
Clock periodicity.
The snapshot caching, for storing the snapshot signal, wherein the snapshot signal is connected by transmission network
Onto snapshot caching.
It include cluster snapshot in the snapshot signal, wherein the tufted state is register in all clusters in present clock period
State set.
It further include selection trace signals module, wherein register cluster is generated by sweep forward, estimates each deposit
Device cluster bring global state recovery rate, and select to improve the state recovery rate most register clusters as tracking cluster,
And it regard cluster input as trace signals, register is as snapshot signal in the cluster of register cluster, until the width of trace signals is pre-
If threshold value.
Claims (8)
1. a kind of adjustable using snapshot designs method for tracing characterized by comprising
Step 1, the capacity of setting trace cache and snapshot caching determines the width of the width limitation and snapshot signal of trace signals
Limitation；
Step 2, it is limited according to the width of the trace signals and the snapshot signal, generates register cluster and iteration selection deposit
Device cluster, so that it is determined that the trace signals and the snapshot signal；
Step 3, according to the trace signals and the snapshot signal, setting tracking structure, wherein the tracking structure includes chasing after
Track controller, trigger, tracking bus, trace cache, snapshot caching；
Wherein further include selection trace signals step, register cluster is generated by sweep forward, estimates each register cluster
Bring global state recovery rate, and select to improve the state recovery rate most register clusters as tracking cluster, and will
Cluster input is used as trace signals, and register is as snapshot signal in the cluster of register cluster, until the width of trace signals meets one
Preset threshold.
2. designing method for tracing using the adjustable of snapshot as described in claim 1, which is characterized in that the trace cache
For storing the trace signals, the trace cache includes the width and depth of trace cache, wherein the width is simultaneously
The signal number of the trace signals is tracked, the depth is to track the clock periodicity of the trace signals.
3. designing method for tracing using the adjustable of snapshot as described in claim 1, which is characterized in that the snapshot is slow
It deposits, for storing the snapshot signal, wherein the snapshot signal is connected on the snapshot caching by transmission network.
4. designing method for tracing using the adjustable of snapshot as described in claim 1, which is characterized in that the snapshot signal
In include cluster snapshot, wherein the tufted state be all clusters in register present clock period state set.
5. a kind of adjustable using snapshot designs follow-up mechanism characterized by comprising
It determines that width limits module, for the capacity of trace cache and snapshot caching to be arranged, determines the width limitation of trace signals
It is limited with the width of snapshot signal；
It determines signaling module, for limiting according to the width of the trace signals and the snapshot signal, generates register cluster simultaneously
Iteration mask register cluster, so that it is determined that the trace signals and the snapshot signal；
Setting tracking construction module, for according to the trace signals and the snapshot signal, setting tracking structure, wherein described
Tracking structure includes tracking controller, trigger, tracking bus, trace cache, snapshot caching；
Trace signals module is selected, for generating register cluster by sweep forward, estimates each register cluster bring
Global state recovery rate, and select to improve the state recovery rate most register clusters as tracking cluster, and cluster is inputted
As trace signals, register is as snapshot signal in the cluster of register cluster, until the width of trace signals meets a default threshold
Value.
6. designing follow-up mechanism using the adjustable of snapshot as claimed in claim 5, which is characterized in that the trace cache
For storing the trace signals, the trace cache includes the width and depth of trace cache, wherein the width is simultaneously
The signal number of the trace signals is tracked, the depth is to track the clock periodicity of the trace signals.
7. designing follow-up mechanism using the adjustable of snapshot as claimed in claim 5, which is characterized in that the snapshot is slow
It deposits, for storing the snapshot signal, wherein the snapshot signal is connected on the snapshot caching by transmission network.
8. designing follow-up mechanism using the adjustable of snapshot as claimed in claim 5, which is characterized in that the snapshot signal
In include cluster snapshot, wherein the tufted state be all clusters in register present clock period state set.
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Application publication date: 20170818 Assignee: Zhongke Jianxin (Beijing) Technology Co.,Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract record no.: X2022990000752 Denomination of invention: A Design for Debuggability Tracing Method and Device Using Snapshots Granted publication date: 20190730 License type: Exclusive License Record date: 20221009 |
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