CN107066707A - The adjustable design method for tracing and device of a kind of use snapshot - Google Patents
The adjustable design method for tracing and device of a kind of use snapshot Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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Abstract
The present invention proposes the adjustable design method for tracing and device of a kind of use snapshot, it is related to integrated circuit adjustable design field, the method comprising the steps of 1, the capacity for setting trace cache to be cached with snapshot, and the width limitation and the width of snapshot signal for determining trace signals are limited；Step 2, limited according to the width of the trace signals and the snapshot signal, generation register cluster and iteration mask register cluster, so that it is determined that the trace signals and the snapshot signal；Step 3, according to the trace signals and the snapshot signal, set and follow the trail of structure, wherein the tracking structure includes tracking controller, trigger, follows the trail of bus, trace cache, snapshot caching.The present invention can significantly improve the state recovery rate of tune-up data, increase the observability of silicon post debugging, shorten the silicon post debugging time；Present invention may determine that the recovery key signal of property；The present invention can reduce the run time of trace signals system of selection.
Description
Technical field
The present invention relates to integrated circuit adjustable design field, more particularly to a kind of adjustable of use snapshot
Design method for tracing and device.
Background technology
With the increase and the increase of Rapid Product pressure of IC design complexity, adjustable is designed to silicon
The support technology of post debugging.Because design complexities are high, software analog rate is slow, the low factor restriction of Time Delay Model precision, silicon
Preceding checking can not ensure the correctness of hardware design, and some design mistakes are omitted to after silicon, or even after chip puts goods on the market
Just it is found, brings about great losses, silicon post debugging is used as last one of Quality Control Links before volume production, it may be verified that chip after flow
Correctness, and the mistake omitted before silicon is detected, positions and diagnoses, because chip observability is poor after flow so that adjusted after silicon
Examination turns into the important bottleneck in lsi development flow, or even needs to expend the development time of more than half, and adjustable is set
The debug circuit that silicon post debugging is aided in by increasing in chip design stage is counted, to improve the Observable of chip during silicon post debugging
Property, shorten the silicon post debugging time.
Adjustable based on tracking is configured as the design of main flow, by increasing trace cache in the chips, can
The continuous real-time tracking capability clapped, and one of major technique as silicon post debugging, and extensively are provided more in silicon post debugging
Applied to business etc. in processor, such as processor of ARM frameworks and IBM Power series processors.One complete tracking
Design is generally included：Trigger module, tracking controller, trace cache, as shown in Figure 1.Trigger module is used to monitor in debugging
Trigger event or trigger sequence, when specified trigger event or sequence generation, trigger element can monitor triggering information simultaneously
Inform tracking controller.Tracking controller receives the trigger signal of trigger module, and open signal is followed the trail of, and will follow the trail of data storage
Into trace cache.Tracking controller can also be according to tuning parameters such as the trigger events in debugging demand configuration trigger element.
Trace cache can real-time storage tracking data.After trace cache is filled with tracking data, the data in trace cache can be passed through
Debugging interface is output to outside piece, is recovered for follow-up state and mistake debugging.
The existing method for following the trail of design of industrial quarters is the important function signal or related to processor instruction stream of selection
Function signal, and these function signals are connected on trace cache by debugging bus.Such as ARM debugging framework is general
It is during the storage such as the location counter of processor, instruction is cached to on-chip trace.This kind of method contributes to the tune of software level
Examination, but limited is helped to the debugging of circuit staging error, how fine-grained accurate lookup, diagnosis and Position Design are wrong after flow
Turn into the bottleneck of silicon post debugging by mistake.
State recovery is the major technique of circuit-level error detection and localization, and it is recovered using known circuit logic state
The method of unknown circuit logic state, recovers to understand the state value of more circuits internal signal, so as to improve electricity by state
Wrong diagnosis and positioning in the observability on road, auxiliary silicon post debugging.Its general principle is the logic work(using logic unit
Logical derivation can be carried out, unknown signaling state is recovered using known signal state.Generally there is the recovery policy of three kinds of gates：Before
It is backward to recover and combination recovery to recovery.Forward direction recovers to be the output for inferring gate using the input of gate, backward to recover
It is the input for utilizing the output of gate to infer gate, combination recovers to be that the output and part input for combining gate are inferred not
The input known.These recovery operations are as shown in Figure 2.For sequential logic gate, operation is also can be recovered, but needs to consider sequential
Relation.Using these recovery principles, state can be built and recover simulator, the tracking data that it is obtained using trace cache are as defeated
Enter, recover the data do not followed the trail of, so as to know more gate leve signal conditions, compared by the data obtained with analog simulation
Compared with, can circuit-level detect, positioning and diagnosis silicon before design mistake.State recovery rate is to evaluate trace signals to not following the trail of
The index of signaling protein14-3-3 ability.State recovery rate is defined as：All knowable buffer status is total after state is recovered
The ratio of total number of the number with following the trail of the buffer status obtained.In same number of trace signals and same tracking cycle
Under, state recovery rate is big, and the internal register state that can be known with regard to representing is more, and internal observability is just bigger, more has
Help the debugging of circuit staging error.
Domestic and international researcher proposes by parser circuitry and therefrom selects some signals important for state recovery to make
For trace signals, i.e., in the selection of trace signals using the trace signals system of selection based on state recovery rate, and it will follow the trail of
Signal is connected on trace cache by following the trail of bus and multiplex networks.It is related to debugging when the tracking cycle starts
The data of trace signals are to be stored in trace cache.Within the tracking cycle, each beat of data of trace signals is stored in
In trace cache, until trace cache does not have vacant memory space.When tune-up data is analyzed, it will need to be deposited in trace cache
The tracking data export of each clock cycle of storage, and state recovery is carried out, so as to aid in the debugging of mistake.Study at present more
The trace signals system of selection based on state recovery rate, be broadly divided into two classes：Trace signals based on probability are selected and are based on
The trace signals selection of simulation.System of selection based on probability by considering register between combinational circuit topology knot
The logical implication of structure and gate, using probability analysis method estimated state recovery rate, and iteratively, selection causes state to recover
Rate reaches the trace signals of maximum.System of selection based on simulation goes predicted state recovery rate using actual analogue data, and
Trace signals are selected with this.
Existing state recovery method only carries out logical derivation from the topological structure of simple combinational circuit, is limited to complexity
Logical construction, state recovery rate is low, and the help to silicon post debugging is limited.The existing debugging technique recovered based on state is to chase after
Tracking data of the track signal within the tracking cycle pass through the logical derivation of gate, the recovery of iteration as known signal
Other signals, signaling protein14-3-3 is the recovery operation of logic-based door, for complicated logic gate structure, such as multi input with
Nor gate, it is relatively low using the probability that individually known input or output recover other unknown signalings.The method is limited to combination and patrolled
The structure and the logical complexity of basic logical gate collected, the shape that state is recovered to obtain is carried out in complicated circuit using trace signals
State recovery rate is low.
In addition, can not to obtain high state within a short period of time extensive for the existing trace signals system of selection recovered based on state
The trace signals of multiple rate.The method speed of service based on probability is fast, but probability Estimation precision is low, and obtained state recovery rate is compared with mould
Plan method is low；Method based on simulation can obtain higher state recovery rate, but run time is long.These deficiencies constrain base
In the system of selection utilization in practice of state recovery rate.
The content of the invention
In view of the shortcomings of the prior art, the present invention proposes the adjustable design method for tracing and dress of a kind of use snapshot
Put.
The present invention proposes a kind of adjustable design method for tracing of use snapshot, including：
Step 1, the capacity that trace cache is cached with snapshot is set, width limitation and the snapshot signal of trace signals is determined
Width is limited；
Step 2, limited according to the width of the trace signals and the snapshot signal, generation register cluster and iteration selection
Register cluster, so that it is determined that the trace signals and the snapshot signal；
Step 3, according to the trace signals and the snapshot signal, set and follow the trail of structure, wherein the tracking structure bag
Include tracking controller, trigger, follow the trail of bus, trace cache, snapshot caching.
The trace cache is used to store the trace signals, and the trace cache includes the width and depth of trace cache
Degree, wherein the width is follows the trail of the signal numbers of the trace signals simultaneously, the depth for follow the trail of the trace signals when
Clock periodicity.
The snapshot caching, for storing the snapshot signal, wherein the snapshot signal is connected by transmission network
Onto snapshot caching.
The snapshot signal includes cluster snapshot, wherein the tufted state be all clusters in register in present clock period
State set.
Also include selection trace signals step, wherein, register cluster, each deposit of estimation are generated by sweep forward
The global state recovery rate that device cluster is brought, and select to improve the state recovery rate most register clusters as tracking cluster,
And using cluster input as trace signals, register is as snapshot signal in the cluster of register cluster, until the width of trace signals is pre-
If threshold value.
The present invention also proposes a kind of adjustable design follow-up mechanism of use snapshot, including：
Determine that width limits module, for the capacity for setting trace cache to be cached with snapshot, determine the width of trace signals
Limitation and the width of snapshot signal are limited；
Signaling module is determined, is limited for the width according to the trace signals and the snapshot signal, generates register
Cluster and iteration mask register cluster, so that it is determined that the trace signals and the snapshot signal；
Set and follow the trail of construction module, for according to the trace signals and the snapshot signal, setting and following the trail of structure, wherein
The tracking structure includes tracking controller, trigger, follows the trail of bus, trace cache, snapshot caching.
The trace cache is used to store the trace signals, and the trace cache includes the width and depth of trace cache
Degree, wherein the width is follows the trail of the signal numbers of the trace signals simultaneously, the depth for follow the trail of the trace signals when
Clock periodicity.
The snapshot caching, for storing the snapshot signal, wherein the snapshot signal is connected by transmission network
Onto snapshot caching.
The snapshot signal includes cluster snapshot, wherein the tufted state be all clusters in register in present clock period
State set.
Also include selection trace signals module, wherein, register cluster, each deposit of estimation are generated by sweep forward
The global state recovery rate that device cluster is brought, and select to improve the state recovery rate most register clusters as tracking cluster,
And using cluster input as trace signals, register is as snapshot signal in the cluster of register cluster, until the width of trace signals is pre-
If threshold value.
From above scheme, the advantage of the invention is that：
First point, the present invention can significantly improve the state recovery rate of tune-up data, increase the Observable of silicon post debugging
Property, shorten the silicon post debugging time.By following the trail of the input of snapshot signal and the original state of snapshot signal, present invention may determine that
Property recovers state value of the snapshot signal in whole debugging cycle, and these state values for being resumed out can also recover it
His unknown signaling, so as to improve the state recovery rate of whole tracing scheme.
Second point, present invention may determine that the recovery key signal of property.In traditional tracking design and state recover, remove
Tracking data, other signals that can be resumed are extremely limited.The present invention is combined by obtaining the original state of snapshot signal
Trace signals, it may be determined that property recovers state of the snapshot signal within the tracking cycle.
Thirdly, the present invention can reduce the run time of trace signals system of selection.The present invention passes through mask register
Cluster, so that it is determined that trace signals and snapshot signal.One register cluster of selection can determine multiple trace signals simultaneously, accelerate and chase after
The speed of track signal behavior.Because selection time is short, selection result can be directed to, multiple iteration optimization is carried out.
Brief description of the drawings
Fig. 1 is the adjustable design framework figure based on tracking；
Fig. 2 is the exemplary plot that state is recovered；
Fig. 3 is the example circuit diagram that cluster recovers；
Fig. 4 is the follow-up mechanism figure of use snapshot proposed by the present invention；
Fig. 5 is that snapshot follows the trail of instance graph；
Fig. 6 is trace signals system of selection flow chart；
Fig. 7 is the flow chart of the tracking design using snapshot.
Embodiment
The present invention use snapshot state recover method be specially：For selected register cluster, with reference to register
The snapshot of register, i.e., the original state of register in cluster, you can recover whole in the cluster input of cluster and the cluster of register cluster
State of the register cluster within the whole tracking cycle.Some registers that one register cluster is extracted in circuit are constituted, this
A little registers are referred to as register in cluster.Register is in the state set of present clock period, also referred to as cluster in all clusters of cluster state representation
Snapshot, and forerunner's register of register is referred to as cluster input in cluster, and the forerunner of register in cluster is directly affected by combinational logic
It is originally inputted also referred to as cluster input.Fig. 3 show a register cluster extracted from circuit, and it includes depositing in 4 clusters
Device, i.e. { B, C, D, E }, and cluster input set is { A }, by obtaining the state of cluster original state and cluster input in all tracking cycles
Value, can recover tufted state value of the register cluster in all tracking cycles, because according to cluster original state and cluster initial input, can
To learn the tufted state in next tracking cycle, with this recursion, the tufted state in hereafter all tracking cycles can be learnt, such as the institute of table 1
Show, if it is known that cluster original state, i.e., the known state of { B, C, D, E } in the cycle 0, and keep track cluster input, i.e., known A
In the value in cycle 0 to cycle 4, the state of { B, C, D, E } in the cycle 1 to 5 can be recovered using these values, you can recover and chase after
All tufted states in the track cycle, as shown in gray shade part in table 1, if taking traditional state recovery method, i.e., not
Use cluster original state, then selection Fig. 3 in any 1 as trace signals, register cluster can not be all recovered completely and is being chased after
The institute in track cycle is stateful.
Table 1
Design is followed the trail of relative to tradition, tracing scheme of the invention is significantly improved in hardware design, such as Fig. 4 institutes
Show, the present invention needs to capture two distinct types of signal：Trace signals and snapshot signal, and traditional tracking design is not captured
Snapshot signal, trace signals each cycle within the tracking cycle all needs capture, and its original state is only captured for snapshot signal, is
Meet capture to require, tracking design of the invention needs increase snapshot caching, that is, has two kinds of caching：
Trace cache and snapshot caching.
Trace cache is that, for storing trace signals, its general width and depth are limited, and width is represented and can chased after simultaneously
The signal number of track, depth represents the clock periodicity that can be followed the trail of, for example：16*1024 trace cache can be followed the trail of simultaneously
16 trace signals, and keep track 1024 cycles.
Snapshot caching is that the tracking of the present invention designs newly-increased caching, is posted to store snapshot signal, i.e. selected tracking
The original state of storage cluster, selected snapshot signal is connected on snapshot caching by transmission network, the snapshot of each different cluster
Signal can successively be captured in the different tracking cycles, if these register clusters do not have Temporal dependency relation, and its snapshot
Signal number sum is not more than the width of snapshot caching, then the snapshot of multiple register clusters can also be captured simultaneously.
As shown in figure 5, the snapshot of three register clusters { A, B, C } is stored into snapshot caching, the cycle can be followed the trail of at three
Interior priority capture register cluster A, B and C snapshot, if meeting snapshot caching wide constraint, register cluster can be also captured simultaneously
A, B and C snapshot.
Snapshot signal improves state recovery rate in due to being cached present invention uses snapshot, therefore corresponding trace signals are selected
Method also has change, can be decomposed into what register cluster generation was selected with register cluster using the trace signals select permeability of snapshot
Problem, trace signals and snapshot signal are determined that, because debugging design overhead is limited, trace register cluster is same by trace register cluster
When need to meet trace signals width WTWith snapshot signal width WSConstraint.
The trace signals system of selection of the use snapshot of the present invention can be divided into two steps：The fasciation of register cluster into and register
Cluster is selected, i.e., generate register cluster by sweep forward first, then estimate that the global state that each register cluster can be brought is extensive
Rate, and select to improve state recovery rate most clusters as tracking cluster again, and using cluster input as trace signals, cluster is interior to be deposited
Device is as snapshot signal, until the width of trace signals meets design requirement (i.e. width meets a predetermined threshold value), trace signals
System of selection flow is as shown in Figure 6.
Specific design step using the tracing scheme of snapshot is：
Step one：Determine buffer memory capacity and signal bondage.The capacity of trace cache and snapshot caching is designed, it is determined that following the trail of letter
Number width limitation and snapshot signal width limit.
Step 2：Trace signals and snapshot signal selection.Limited according to the width of trace signals and snapshot signal, generation is posted
Storage cluster and iteration mask register cluster, so that it is determined that trace signals and snapshot signal.
Step 3：Design is overall to follow the trail of structure.It is determined that complete tracking scheduling scheme, the whole tracking structure of design, including
Tracking controller, trigger, tracking bus, trace cache, snapshot caching etc..
The present invention also proposes a kind of adjustable design follow-up mechanism of use snapshot, including：
Determine that width limits module, for the capacity for setting trace cache to be cached with snapshot, determine the width of trace signals
Limitation and the width of snapshot signal are limited；
Signaling module is determined, is limited for the width according to the trace signals and the snapshot signal, generates register
Cluster and iteration mask register cluster, so that it is determined that the trace signals and the snapshot signal；
Set and follow the trail of construction module, for according to the trace signals and the snapshot signal, setting and following the trail of structure, wherein
The tracking structure includes tracking controller, trigger, follows the trail of bus, trace cache, snapshot caching.
The trace cache is used to store the trace signals, and the trace cache includes the width and depth of trace cache
Degree, wherein the width is follows the trail of the signal numbers of the trace signals simultaneously, the depth for follow the trail of the trace signals when
Clock periodicity.
The snapshot caching, for storing the snapshot signal, wherein the snapshot signal is connected by transmission network
Onto snapshot caching.
The snapshot signal includes cluster snapshot, wherein the tufted state be all clusters in register in present clock period
State set.
Also include selection trace signals module, wherein, register cluster, each deposit of estimation are generated by sweep forward
The global state recovery rate that device cluster is brought, and select to improve the state recovery rate most register clusters as tracking cluster,
And using cluster input as trace signals, register is as snapshot signal in the cluster of register cluster, until the width of trace signals is pre-
If threshold value.
Claims (10)
1. a kind of adjustable design method for tracing of use snapshot, it is characterised in that including：
Step 1, the capacity that trace cache is cached with snapshot is set, width limitation and the width of snapshot signal of trace signals is determined
Limitation；
Step 2, limited according to the width of the trace signals and the snapshot signal, generation register cluster and iteration selection deposit
Device cluster, so that it is determined that the trace signals and the snapshot signal；
Step 3, according to the trace signals and the snapshot signal, set and follow the trail of structure, wherein the tracking structure includes chasing after
Track controller, trigger, tracking bus, trace cache, snapshot caching.
2. as claimed in claim 1 using the adjustable design method for tracing of snapshot, it is characterised in that the trace cache
For storing the trace signals, the trace cache includes the width and depth of trace cache, wherein the width is simultaneously
The signal number of the trace signals is followed the trail of, the depth is to follow the trail of the clock periodicity of the trace signals.
3. as claimed in claim 1 using the adjustable design method for tracing of snapshot, it is characterised in that the snapshot delays
Deposit, for storing the snapshot signal, wherein the snapshot signal is connected on the snapshot caching by transmission network.
4. as claimed in claim 1 using the adjustable design method for tracing of snapshot, it is characterised in that the snapshot signal
Include cluster snapshot, wherein the tufted state is state set of the register in present clock period in all clusters.
5. as claimed in claim 1 using the adjustable design method for tracing of snapshot, it is characterised in that also chased after including selection
Track signals step, wherein, register cluster is generated by sweep forward, the global state that each register cluster of estimation is brought is extensive
Rate, and select the register clusters most to state recovery rate improvement to believe as tracking cluster, and using cluster input as tracking again
Number, register is as snapshot signal in the cluster of register cluster, until the width predetermined threshold value of trace signals.
6. a kind of adjustable design follow-up mechanism of use snapshot, it is characterised in that including：
Determine that width limits module, for the capacity for setting trace cache to be cached with snapshot, determine the width limitation of trace signals
Limited with the width of snapshot signal；
Signaling module is determined, is limited for the width according to the trace signals and the snapshot signal, generation register cluster is simultaneously
Iteration mask register cluster, so that it is determined that the trace signals and the snapshot signal；
Set and follow the trail of construction module, for according to the trace signals and the snapshot signal, setting and following the trail of structure, wherein described
Following the trail of structure includes tracking controller, trigger, follows the trail of bus, trace cache, snapshot caching.
7. as claimed in claim 6 using the adjustable design follow-up mechanism of snapshot, it is characterised in that the trace cache
For storing the trace signals, the trace cache includes the width and depth of trace cache, wherein the width is simultaneously
The signal number of the trace signals is followed the trail of, the depth is to follow the trail of the clock periodicity of the trace signals.
8. as claimed in claim 6 using the adjustable design follow-up mechanism of snapshot, it is characterised in that the snapshot delays
Deposit, for storing the snapshot signal, wherein the snapshot signal is connected on the snapshot caching by transmission network.
9. as claimed in claim 6 using the adjustable design follow-up mechanism of snapshot, it is characterised in that the snapshot signal
Include cluster snapshot, wherein the tufted state is state set of the register in present clock period in all clusters.
10. as claimed in claim 6 using the adjustable design follow-up mechanism of snapshot, it is characterised in that also including selection
Trace signals module, wherein, register cluster, the global state that each register cluster of estimation is brought are generated by sweep forward
Recovery rate, and select the register clusters most to state recovery rate improvement to be used as tracking as tracking cluster, and using cluster input
Register is as snapshot signal in signal, the cluster of register cluster, until the width predetermined threshold value of trace signals.
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Application publication date: 20170818 Assignee: Zhongke Jianxin (Beijing) Technology Co.,Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract record no.: X2022990000752 Denomination of invention: A Design for Debuggability Tracing Method and Device Using Snapshots Granted publication date: 20190730 License type: Exclusive License Record date: 20221009 |