CN107066356A - A kind of storage method of server B MC configuration datas - Google Patents
A kind of storage method of server B MC configuration datas Download PDFInfo
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- CN107066356A CN107066356A CN201710348742.7A CN201710348742A CN107066356A CN 107066356 A CN107066356 A CN 107066356A CN 201710348742 A CN201710348742 A CN 201710348742A CN 107066356 A CN107066356 A CN 107066356A
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- ufm
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- configuration
- bmc
- order
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1417—Boot up procedures
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- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
The invention discloses a kind of storage method of server B MC configuration datas, this method obtains BMC configuration information using FPGA, register is arrived into configuration information storage, during server power-off restarting, when BMC is in dead state, the configuration information that FPGA is read in register carries out server partition configuration;After BMC is brought back to life, new configuration information is produced, whether the newer configuration informations of PFGA are consistent with the configuration information stored, if unanimously, without operation, otherwise storing new configuration information and reopening server using the new configuration information.Compared with prior art, the present invention can realize the automatic storage and acquisition of dynamic data, improve the utilization rate of flash chip, realize that server is initially configured in the state of being brought back to life without waiting for BMC, the stability and reliability of lifting system.
Description
Technical field
The present invention relates to technical field of data storage, specifically a kind of storage method of server B MC configuration datas.
Background technology
With continuing to develop for information technology, server is more widely applied, to the performance configuration each side of server
Propose higher requirement.Server carries out remote monitoring management, configuration to whole system from Management Controller (BMC) mostly
Deng operation.The high-end server of tide independent research realizes the tunnel of subregion 8 (8-cpu) server or the service of double 4 tunnels via BMC
The configuration of device.But the upper of both the above configuration is differed, it is necessary to send the configuration bit on 4 tunnels and 8 tunnels by BMC
GPIO 0(GPIO:General Purpose Input Output, referred to as universal input/output, GPIO) and GPIO 1 arrive
Chip FPGA (Field-Programmable Gate Array programmable gate arrays), FPGA is by judging GPIO0 and GPIO1
Low and high level it is electric to realize in different configuration of start.
In actual use due to there is a situation where to restart after accident power-off, power down when need FPGA to wait 40s time
Reacquisition BMC configuration bit GPIO 0 and GPIO 1 state are gone, and because BMC is in death within the time for waiting 40s
State, the state for causing GPIO 0 and GPIO 1 is indefinite state, to realize that server is not to wait for BMC and brings back to life the feelings that can but start shooting
Condition is, it is necessary to obtain the first two GPIO of power down state, so needing to realize dynamic GPIO data storage before power down.
Traditional mode typically realizes the storage to dynamic data using plug-in flash, to ensure to match somebody with somebody during accident power-off
Putting data can preserve in time, and can read configuration data in next starting up.This mode can not only take circuit
Plate suqare, and increase purchase cost.
The content of the invention
To overcome the shortcomings of that above-mentioned prior art is present, number is configured it is an object of the invention to provide a kind of server B MC
According to storage method, this method realizes the storage of dynamic data, improves the utilization rate of flash chip, the stability of lifting system
And reliability.
The technical solution adopted for the present invention to solve the technical problems is:A kind of storage side of server B MC configuration datas
Method, it is characterized in that:FPGA obtains BMC configuration information, and configuration information storage is arrived into register, server power-off restarting mistake
Cheng Zhong, when BMC is in dead state, the configuration information that FPGA is read in register carries out server partition configuration;BMC is brought back to life
Afterwards, new configuration information is produced, whether the newer configuration informations of PFGA are consistent with the configuration information stored, if unanimously, do not entered
Row operation, otherwise stores new configuration information and reopens server using the new configuration information.
Further, the register is UFM, in the configuration information storage to the UFM IP kernels inside UFM.
Further, the configuration information arrives UFM IP kernels by the storage of wishbone interfaces.
Further, the FPGA includes user logic module and UFM, and the user logic module obtains BMC configuration
Information, and be connected with UFM by wishbone interfaces.
Further, the user logic module includes top-level module, UFM orders submodule and UFM module for reading and writing, described
Top-level module obtains BMC configuration informations, sends and orders to UFM orders submodule, and UFM orders submodule receives the order, and
Subcommand is sent to UFM module for reading and writing, UFM module for reading and writing, which has been performed, returns to identification information to top-level module after the subcommand.
Further, the order includes reading to enable order, writes enable order, data storage command and data acquisition life
Order, when BMC is in dead state, top-level module, which is sent, reads to enable order and data retrieval commands to the UFM orders submodule
Block, after BMC is brought back to life, top-level module sends data storage and writes enable order.
Further, the subcommand includes UFM open commands, data read command, data write command and data erasing life
Order.
Further, the order is reads to enable during order, and UFM module for reading and writing performs data read command, and the order is
When writing enable order, UFM module for reading and writing first carries out data erasing order, then performs data write command.
Further, the wishbone interfaces pass through UFM register access UFM.
Further, described access includes the reading and writing and erasing to configuration data.
The beneficial effects of the invention are as follows:Compared with prior art, the present invention is accessed using FPGA by wishbone interfaces
The UFM ip cores itself having, under the dead states of BMC, realize the power-off restarting of server, without additionally adding plug-in flash
It can be achieved, improve the utilization rate of UFM chips, while reducing the area occupied of fpga chip, reduce design cost, together
When improve the stability and reliability of whole system;
After the completion of BMC initialization, GPIO configuration datas are sent to FPGA, FPGA passes through internal Wishbone interfaces
UFM registers are accessed, the UFM that operation is stored data in inside chip FPGA is written and read to register, configuration data is realized
Automatic storage, when BMC powers off dead state, FPGA directly obtains the configuration data before power-off by wishbone interfaces,
Realize the automatic acquisition of configuration data, it is to avoid carry out the wait of BMC resurrections, save the time, improve operating efficiency.
Brief description of the drawings
Fig. 1 is the overall structure block diagram of the method for the invention;
Fig. 2 is the connection diagram of wishbone interfaces of the present invention;
Fig. 3 is wishbone of the present invention interface definition figure;
To the flow chart of configuration data processing when Fig. 4 is server start;
Fig. 5 is user logic module of the present invention and UFM connection diagram;
Fig. 6 is UFM register instructions and address corresponding table;
Fig. 7 is the flow chart of dynamic data storage of the present invention;
Fig. 8 is the workflow diagram of UFM orders submodule of the present invention;
Fig. 9 is the flow chart that UFM module for reading and writing of the present invention reads data;
Figure 10 is the flow chart that UFM module for reading and writing of the present invention writes data.
Embodiment
For the technical characterstic for illustrating this programme can be understood, below by embodiment, and its accompanying drawing is combined, to this hair
It is bright to be described in detail.Present invention omits the description to common knowledge and handling process to avoid being unnecessarily limiting this hair
It is bright.
As shown in figure 1, a kind of structured flowchart of the storage method of server B MC configuration datas of the present invention, wherein servicing
Device system include including inside control manager BMC and fpga chip, fpga chip user logic (user logic) module and
UFM IP kernels (UFM, User Flash Memory, user's nonvolatile storage;IP kernel, full name IP core
(intellectual property core), refer to one party provide, form be logic unit, chip design it is reusable
Module.), the user logic and UFM IP kernels are connected by wishbone interfaces, and wishbone interfaces include master
(master) interface and from (slave) interface, user logic, which pass through wishbone master and wishbone slave, to be carried out
Signal is transmitted, and data read-write operation is carried out to UFM.
As shown in Figure 2,3, UFM is connected by wishbone interfaces by master and slave interface with FPGA user logics.The FPGA
The chip for the model LCMX02-2000HC that chip is produced from lattice manufacturers, the wishbone main frames mouthful are located at FPGA
User logic module on, the UFM be located at FPGA inside EFB (Embedded Function Block) module in, pass through
EFB registers (EFB Register Map) connect wishbone from interface, realize the communication of the master and slave interfaces of wishbone.
Wishbone main interfaces to from interface send master clock signal, reset signal, input data signal, address signal,
Show the input signals such as a valid data transmission periodic signal, the realistic energy signal of data, valid bus periodic signal,
Wishbone sends the output signals such as outputting data signals, answer signal from interface to main interface.
As shown in figure 4, in the normal startup optimization of server, FPGA obtains BMC configuration information and described will match somebody with somebody confidence
Breath is stored into UFM.Server exception power-off start during, due to BMC have one 40s time indefinite state (or
Make definite the state of dying, initialization unfinished state), if when electric on server, BMC does not complete initialization, then PFGA judge whether into
Configuration information of going storage operation, that is, judge whether UFM storages position is 1, if it is, the configuration data of UFM accesses is read, it is complete
Start into server is configured, and otherwise continues interpretation BMC init state, until BMC is brought back to life, carries out GPIO data configurations,
Server is booted up;If BMC completes initialization (i.e. BMC is in resurrection state) during Server Restart, FPGA is obtained
BMC new configuration data simultaneously checks whether the configuration data changes, i.e., whether BMC re-starts GPIO data configurations, such as
Fruit is, then sends data storage order by wishbone, UFM by data storage it is complete after by UFM storage marks position 1, now
Judge whether server completes start, if having completed start, server is shut down, otherwise read the configuration number of UFM accesses
According to the start for completing server is configured;
As shown in figure 5, the specific embodiment of the present invention, calls FPGA's using TOP_DOWM mentality of designing
UFM IP kernels.The user logic module includes top-down top layer (TOP layers) module, UFM orders submodule and UFM read-writes
Module, wherein top-level module mainly realize the example to order submodule, as the FPGA BMC received configuration data GPIO 0
When being changed with GPIO 1, send and order to following UFM orders submodule, these orders include reading to enable, write enable, number
According to storage, data acquisition, UFM Module cycles receive these orders, and the order word modules are read and write for different orders to UFM
Module issues UFM unlatchings, reading and writing data, the subcommand of data erasing, and UFM module for reading and writing has been performed after above-mentioned subcommand, returned
Successful flag bit is read and write, top-level module is last transmitted to.
Wishbone interfaces are by UFM register access UFM.As shown in fig. 6, Wishbone interfaces are directly to UFM
Corresponding register under send instructions and command code, access different addresses, complete the reading and writing data to UFM.
Further, UFM reading and writing datas use top-down design, by top-level module to bottom UFM module for reading and writing, by
One function is transmitted.
Top layers of module are mainly realized docks with user logic module, receives GPIO 0 and 1 low and high levels that BMC is sent
Signal.After server power failure, as shown in fig. 7, during re-powering, if BMC initialization is not completed, will be obtained from UFM
GPIO 0 and 1 configuration data is taken to carry out 4 tunnels or the configuration of 8 tunnels of system boot.BMC initialization completions are treated, if GPIO 0
Or the level signals of GPIO 0 and 1 that GPIO 1 is sent with BMC before server power failure are changed, then pass through UFM subcommands
Module wipes original UFM inside modules data, and new GPIO 0 and 1 to UFM is write by UFM module for reading and writing.UFM order submodules
The reading and writing data complement mark position of transmission, also is stored in UFM modules, writes flag bit if 0, illustrates that server enters for the first time
The tunnel of row 4 or the start configuration of 8 tunnels, the GPIO data of start are directly obtained by BMC.Start shooting next time and then obtain GPIO numbers from UFM
According to.
As shown in figure 8, UFM order submodules primary recipient handles the order that top layers of module are sent, each order is sent
UFM module for reading and writing is given, UFM module enables are carried out to it, reads, writes, the selection of function is wiped, and sends read-write and completes position to top
Layer.Specifically, UFM orders submodule receives the order of top-level module, it is that UFM GPIO 0/1 write enable order to judge the order
Or UFM GPIO 0/1 read to enable order, and open corresponding UFM orders, such as receive UFM GPIO 0/1 and read to enable life
Order, be transmitted successively reading data subcommand to UFM module for reading and writing, make reading data mark position 1, close UFM orders, return reading
Data complement mark is to Top layers;Such as receive UFM GPIO 0/1 and write enable order, be then sequentially completed erasing UFM subcommands, hair
Send write data subcommand to UFM module for reading and writing, make to write Data Labels position 1, close UFM orders, return back read data complement mark
To Top layers.
The UFM module for reading and writing is mainly based upon writing for wishbone main interface codes, is responsible for address decoding, sends life
Order and command code control the read-write of each register to UFM registers, complete the operations such as basic page number read-write erasing.UFM is read
The base unit write is page, and the base unit of erasing is sector.
Specifically, as shown in figure 9, when UFM modules receive UFM orders submodule transmission when writing data to UFM orders,
Wishbone interfaces are first turned on, when status register is idle, initial address is read in setting, then carries out the write-in of data,
Wishbone interfaces are closed when status register is idle, the write-in of GPIO configuration datas is completed;As shown in Figure 10, when UFM modules
Receive UFM orders submodule transmission from UFM read data order when, open wishbone interfaces, in status register
Write address, the data number and timer that read are set when idle, a data are often read, counter subtracts 1, until being counted as 0, pass
Wishbone interfaces are closed, the reading of GPIO configuration datas is completed.
Preferably, the fpga chip that the present invention is produced from lattice (Lai Disi) manufacturer, loads UFM IP kernels, by life
Into UFM.V files be loaded under project file, carry out dynamic data timely storage.UFM is located at the EFB inside FPGA
, it is necessary to which first generation EFB IP kernels recall UFM in (Embedded Function Block) module.
Simply the preferred embodiment of the present invention described above, for those skilled in the art,
Without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications are also regarded as this hair
Bright protection domain.
Claims (10)
1. a kind of storage method of server B MC configuration datas, it is characterized in that:FPGA obtains BMC configuration information, matches somebody with somebody described
Register is arrived in confidence breath storage;During server power-off restarting, when BMC is in dead state, FPGA is read in register
Configuration information carry out server partition configuration;After BMC is brought back to life, new configuration information is produced, the newer configuration informations of PFGA are with depositing
Whether the configuration information of storage is consistent, if unanimously, without operation, otherwise storing new configuration information and utilizing the new configuration
Information restarts server.
2. a kind of storage method of server B MC configuration datas according to claim 1, it is characterized in that:The register
For UFM, the configuration information is stored into the UFM IP kernels inside UFM.
3. a kind of storage method of server B MC configuration datas according to claim 2, it is characterized in that:It is described to match somebody with somebody confidence
Breath arrives UFM IP kernels by the storage of wishbone interfaces.
4. a kind of storage method of server B MC configuration datas according to claim 3, it is characterized in that:The FPGA bags
User logic module and UFM are included, the user logic module obtains BMC configuration information, and passes through wishbone interfaces with UFM
Connection.
5. a kind of storage method of server B MC configuration datas according to claim 4, it is characterized in that:The user patrols
Collecting module includes top-level module, UFM orders submodule and UFM module for reading and writing, and the top-level module obtains BMC configuration informations, to
UFM orders submodule sends order, and UFM orders submodule receives the order, and sends subcommand, UFM to UFM module for reading and writing
Module for reading and writing, which has been performed, returns to identification information to top-level module after the subcommand.
6. the storage method of 5 a kind of server B MC configuration datas according to claim, it is characterized in that:The order bag
Reading is included to enable order, write enable order, data storage command and data retrieval commands, when BMC is in dead state, top layer mould
Block, which is sent, reads to enable order and data retrieval commands to the UFM orders submodule, and after BMC is brought back to life, top-level module sends number
Order is enabled according to storing and writing.
7. a kind of storage method of server B MC configuration datas according to claim 6, it is characterized in that:The subcommand
Including UFM open commands, data read command, data write command and data erasing order.
8. a kind of storage method of server B MC configuration datas according to claim 7, it is characterized in that:The order is
When reading to enable order, UFM module for reading and writing performs data read command, and the order is writes during enable order, and UFM module for reading and writing is first held
Row data erasing order, then perform data write command.
9. a kind of storage method of server B MC configuration datas according to claim any one of 1-8, it is characterized in that:Institute
State wishbone interfaces and pass through UFM register access UFM.
10. a kind of storage method of server B MC configuration datas according to claim 8, it is characterized in that:It is described to access bag
Include the reading and writing and erasing to configuration data.
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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CN107682179A (en) * | 2017-08-31 | 2018-02-09 | 郑州云海信息技术有限公司 | A kind of server collocation method and device based on prestored information |
CN107885522A (en) * | 2017-10-31 | 2018-04-06 | 郑州云海信息技术有限公司 | A kind of method of online change server configuration |
CN108170247A (en) * | 2017-12-21 | 2018-06-15 | 曙光信息产业(北京)有限公司 | BMC power loss recovery method and apparatus |
CN109254798A (en) * | 2018-08-29 | 2019-01-22 | 郑州云海信息技术有限公司 | Server starts method, apparatus, server and computer readable storage medium |
CN113835770A (en) * | 2021-11-30 | 2021-12-24 | 四川华鲲振宇智能科技有限责任公司 | Online replacement method and system for server management module |
CN114816022A (en) * | 2022-04-28 | 2022-07-29 | 苏州浪潮智能科技有限公司 | Server power supply abnormity monitoring method, system and storage medium |
CN117076365A (en) * | 2023-10-13 | 2023-11-17 | 成都申威科技有限责任公司 | Method and system for controlling data transmissible peripheral interface of computer |
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CN102594331A (en) * | 2011-12-29 | 2012-07-18 | 中国西电电气股份有限公司 | Field programmable gate array (FPGA) interior-based analog parallel interface circuit and implementation method thereof |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107682179A (en) * | 2017-08-31 | 2018-02-09 | 郑州云海信息技术有限公司 | A kind of server collocation method and device based on prestored information |
CN107885522A (en) * | 2017-10-31 | 2018-04-06 | 郑州云海信息技术有限公司 | A kind of method of online change server configuration |
CN108170247A (en) * | 2017-12-21 | 2018-06-15 | 曙光信息产业(北京)有限公司 | BMC power loss recovery method and apparatus |
CN109254798A (en) * | 2018-08-29 | 2019-01-22 | 郑州云海信息技术有限公司 | Server starts method, apparatus, server and computer readable storage medium |
CN113835770A (en) * | 2021-11-30 | 2021-12-24 | 四川华鲲振宇智能科技有限责任公司 | Online replacement method and system for server management module |
CN113835770B (en) * | 2021-11-30 | 2022-02-18 | 四川华鲲振宇智能科技有限责任公司 | Online replacement method and system for server management module |
CN114816022A (en) * | 2022-04-28 | 2022-07-29 | 苏州浪潮智能科技有限公司 | Server power supply abnormity monitoring method, system and storage medium |
CN114816022B (en) * | 2022-04-28 | 2023-08-04 | 苏州浪潮智能科技有限公司 | Method, system and storage medium for monitoring server power supply abnormality |
CN117076365A (en) * | 2023-10-13 | 2023-11-17 | 成都申威科技有限责任公司 | Method and system for controlling data transmissible peripheral interface of computer |
CN117076365B (en) * | 2023-10-13 | 2024-01-30 | 成都申威科技有限责任公司 | Method and system for controlling data transmissible peripheral interface of computer |
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