CN107065374B - A kind of array substrate of Electronic Paper, Electronic Paper and its driving method - Google Patents
A kind of array substrate of Electronic Paper, Electronic Paper and its driving method Download PDFInfo
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- CN107065374B CN107065374B CN201710212254.3A CN201710212254A CN107065374B CN 107065374 B CN107065374 B CN 107065374B CN 201710212254 A CN201710212254 A CN 201710212254A CN 107065374 B CN107065374 B CN 107065374B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field
- G02F1/166—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect
- G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
- G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
Abstract
The application discloses the array substrate, Electronic Paper and its driving method of a kind of Electronic Paper, wherein the array substrate includes: Mi i-stage gate electrode side sector wiring, each i-stage gate electrode side sector wiring exports the i-th scanning signal step by step, wherein, i is positive integer, and i=1,2 ... ... n；Mi is positive integer, and Mi≤2；Multiple pixel units arranged in arrays, each pixel unit are connected with an i-stage gate electrode side sector wiring；Wherein, in each pixel unit, when the 1st scanning signal to the (n-1)th scanning signal is useful signal, the n-th scanning signal is for controlling corresponding pixel unit gating.2 multistage gate electrode side gate wirings are all larger than or are equal to by the way that every number of stages is arranged, Mn gate electrode side gate wirings control M1 × M2 that realizes M1+M2+ ... × ... the strobe state of Mn row pixel unit, to reduce the use of gate electrode side sector wiring, and then realize narrow frame.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrates of Electronic Paper, Electronic Paper and its driving side
Method.
Background technique
With the continuous development of display technology, the flat panel display in display technology is because its is small in size, easy to carry etc.
Advantage and be widely used.Meet the reading habit of the mankind, phase by the Electronic Paper and e-book of electronic ink technologies manufacture
Than general flat panel display, Electronic Paper is not likely to produce fatigue, and very power saving after reading for a long time.Compared to book paper,
It has amount of storage big again, easy-to-look-up and environmentally friendly advantage, and therefore, electronic paper technology has good development prospect.
As shown in Figure 1, passing through grid for the conventional wires mode structural schematic diagram used in Electronic Paper in the prior art
The pixel in effective display area (the also referred to as area AA) 01 and driving chip (IC) 02 are directly connected to by side sector wiring 03, will usually be owned
Gate electrode side sector wiring mean allocation, is distributed in the two sides in the area AA, thus reduce the space that gate electrode side gate wirings occupy frame,
To realize narrow frame.
But with the development of narrow frame, the method for above-mentioned realization narrow frame is no longer satisfied the demand of user, therefore,
How to further realize the narrow frame chemical conversion of Electronic Paper is urgent problem to be solved.
Summary of the invention
In view of this, the present invention provides the array substrate, Electronic Paper and its driving method of a kind of Electronic Paper, it is existing to solve
In technology the frame of Electronic Paper can not further narrow frame the problem of.
To achieve the above object, the invention provides the following technical scheme:
A kind of array substrate of Electronic Paper, comprising:
N group gate electrode side sector wiring group, n are positive integer, and n≤2；
The n group gate electrode side sector wiring group includes:
Mi i-stage gate electrode side sector wiring, each i-stage gate electrode side sector wiring export the i-th scanning letter step by step
Number, wherein i is positive integer, and i=1,2 ... ... n；Mi is positive integer, and Mi≤2；
Multiple pixel units arranged in arrays, each pixel unit with an i-stage gate electrode side sector wiring
It is connected, i is positive integer, and i=1,2 ... ... n；
Wherein, in each pixel unit, when the 1st scanning signal to the (n-1)th scanning signal is useful signal
When, n-th scanning signal is for controlling corresponding pixel unit gating.
The present invention also provides a kind of Electronic Paper, the array substrate including Electronic Paper recited above.
The present invention also provides a kind of driving methods of Electronic Paper, wherein
The Electronic Paper includes:
First order gate electrode side sector wiring group and second level gate electrode side sector wiring group；
The first order gate electrode side sector wiring group includes M1 first order gate electrode side sector wiring, each first order
Gate electrode side sector wiring exports the first scanning signal step by step, wherein M1 is positive integer, and M1≤2；
The second level gate electrode side sector wiring group includes M2 second level gate electrode side sector wiring, each second level
Gate electrode side sector wiring exports the second scanning signal step by step, wherein M2 is positive integer, and M2≤2；
Multiple pixel units arranged in arrays, each pixel unit with a first order gate electrode side sector wiring
It is connected with a second level gate electrode side sector wiring；
Each pixel unit includes concatenated first switch tube and second switch；
The first end of the first switch tube is connected with the first end of the first switch in multiple pixel units of same column；Institute
The second end for stating first switch tube is connected with the first end of the second switch, the second end of the second switch and its institute
Pixel unit in pixel electrode be connected；
The control terminal of the first switch tube is connected with a first order gate electrode side sector wiring；
The control terminal of the second switch is connected with a second level gate electrode side sector wiring；
The driving method includes:
The first useful signal is inputted step by step to the M1 first order gate electrode side sector wirings, it is multiple described successively to control
The first switch tube in pixel unit is opened；
The second useful signal is inputted step by step to the M2 second level gate electrode side sector wirings, it is multiple described successively to control
The second switch in pixel unit is opened；
Wherein, in timing, M1 first useful signals are mutually staggered, and M2 second useful signals are mutually wrong
It opens, and M2 second useful signals are corresponding with first useful signal.
It can be seen via above technical scheme that Electronic Paper array substrate provided by the invention, comprising: n group gate electrode side is fan-shaped
Wiring group, n are positive integer, and n≤2；The n group gate electrode side sector wiring group includes: Mi i-stage gate electrode side sector wiring,
Each i-stage gate electrode side sector wiring exports the i-th scanning signal step by step, wherein i is positive integer, and i=1,2 ... ... n；
Mi is positive integer, and Mi≤2；Multiple pixel units arranged in arrays, each pixel unit with an i-stage grid
Side sector wiring is connected, and i is positive integer, and i=1,2 ... ... n；Wherein, in each pixel unit, when the 1st scanning
When signal to the (n-1)th scanning signal is useful signal, n-th scanning signal is for controlling corresponding pixel unit gating.
By the way that multistage gate electrode side gate wirings are arranged in the present invention, the quantity of every grade of gate electrode side sector wiring is all larger than or waits
In 2, to realize M1+M2+ ... Mn gate electrode side gate wirings control M1 × M2 × ... the gating shape of Mn row pixel unit
State, compared with the existing technology in M1 × M2 × ... the strobe state of Mn row pixel unit need M1 × M2 × ... Mn grid
Side sector matches the wire laying mode of line traffic control, and the quantity for reducing gate electrode side sector wiring is (M1 × M2 × ... Mn)-(M1+M2
+ ... Mn), so as to greatly reduce the space that gate electrode side sector wiring occupies frame, enable Electronic Paper frame into one
Step narrows, and narrow frame is further realized in prior art basis.
Meanwhile the present invention also provides a kind of Electronic Papers, using the array substrate of above-mentioned Electronic Paper, since gate electrode side sector is matched
The number of line greatly reduces, and the frame of Electronic Paper can further realize narrow frame, meanwhile, the structure of the driving chip of Electronic Paper
It can be reduced with control complexity, to reduce the cost of driving chip, and then reduce the production cost of Electronic Paper.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the conventional wires mode structural schematic diagram of Electronic Paper in the prior art；
Fig. 2 is the array substrate plan structure signal of 24 row pixel unit strobe cases of control provided in an embodiment of the present invention
Figure；
Fig. 3 is the scanning signal timing diagram on each gate electrode side sector wiring in array substrate shown in Fig. 2；
Fig. 4 is that the array substrate plan structure for controlling 24 row pixel unit strobe cases using prior art wire laying mode is shown
It is intended to；
Fig. 5 be another embodiment of the present invention provides array substrate structural schematic diagram；
Fig. 6 is the driver' s timing schematic diagram of array substrate shown in fig. 5；
Fig. 7 is that the array substrate plan structure for controlling 36 row pixel unit strobe cases using prior art wire laying mode is shown
It is intended to；
Fig. 8 is a kind of the schematic diagram of the section structure of Electronic Paper provided in an embodiment of the present invention.
Specific embodiment
In the prior art, the corresponding one group of gate electrode side sector wiring of every row pixel unit (being also referred to as Gate fanout line), it is right
It can also increase therewith in the number of the higher Electronic Paper of longitudinal resolution, Gate fanout line, occupy side to increase considerably
The size of frame, so that the frame size of Electronic Paper is larger.
Since Electronic Paper and common liquid crystal display device are there are relatively big difference, Electronic Paper is reflection type display device, is not had
There is the limitation of aperture opening ratio requirement, therefore, multiple switch pipe can be made in pixel unit for controlling a pixel unit
Strobe state.Inventor fans by the way that n concatenated switching tubes are arranged in a pixel unit, and by n group gate electrode side as a result,
Shape wiring group carries out a concatenated switching tubes of the n combined " with logic " control in each pixel unit and opens, to control picture
Plain one-cell switching, wherein n is positive integer, and n≤2.
Based on this, Electronic Paper array substrate provided by the invention, comprising: n group gate electrode side sector wiring group, n is positive integer,
And n≤2；The n group gate electrode side sector wiring group includes: Mi i-stage gate electrode side sector wiring, each i-stage grid
Side sector wiring exports the i-th scanning signal step by step, wherein i is positive integer, and i=1,2 ... ... n；Mi is positive integer, and Mi≤
2；Multiple pixel units arranged in arrays, each pixel unit are connected with an i-stage gate electrode side sector wiring, i
For positive integer, and i=1,2 ... ... n；Wherein, in each pixel unit, when the 1st scanning signal to the (n-1)th scanning
When signal is useful signal, n-th scanning signal is for controlling corresponding pixel unit gating.
By the way that multistage gate electrode side gate wirings are arranged in the present invention, the quantity of every grade of gate electrode side sector wiring is all larger than or waits
In 2, to realize M1+M2+ ... Mn gate electrode side gate wirings control M1 × M2 × ... the gating shape of Mn row pixel unit
State, compared with the existing technology in M1 × M2 × ... the strobe state of Mn row pixel unit need M1 × M2 × ... Mn grid
Side sector matches the wire laying mode of line traffic control, and the quantity for reducing gate electrode side sector wiring is (M1 × M2 × ... Mn)-(M1+M2
+ ... Mn), so as to greatly reduce the space that gate electrode side sector wiring occupies frame, enable Electronic Paper frame into one
Step narrows, and narrow frame is further realized in prior art basis.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of array substrate of Electronic Paper, comprising: n group gate electrode side sector wiring group, n is positive whole
Number, and n≤2；The n group gate electrode side sector wiring group includes: Mi i-stage gate electrode side sector wiring, each i-stage grid
Pole side sector wiring exports the i-th scanning signal step by step, wherein i is positive integer, and i=1,2 ... ... n；Mi is positive integer, and Mi
≧2；Multiple pixel units arranged in arrays, each pixel unit are connected with an i-stage gate electrode side sector wiring,
I is positive integer, and i=1,2 ... ... n；Wherein, in each pixel unit, when the 1st scanning signal to the (n-1)th scanning
When signal is useful signal, n-th scanning signal is for controlling corresponding pixel unit gating.
Wherein, each pixel unit is connected with an i-stage gate electrode side sector wiring, and i is positive integer, and i=1,
2 ... ... n；Namely each pixel unit, simultaneously with a first order gate electrode side sector wiring, a second level gate electrode side sector matches
Line, a third level gate electrode side sector wiring ... n-th grade of gate electrode side sector of an i-stage gate electrode side sector wiring ...
Wiring is connected.
Each i-stage gate electrode side sector wiring exports the i-th scanning signal step by step, has in the i-th scanning signal including i-th
Imitate signal.Scanning signal is known as to the useful signal of corresponding scanning signal, such as the first scanning signal is effective in this implementation when effective
When signal be the first useful signal, signal when the second scanning signal is effective is known as the second useful signal, and so on, i-th
When scanning signal is effective, referred to as the i-th useful signal.
The array substrate provided in the present embodiment includes M1 first order gate electrode side sector wiring, each first order gate electrode side
Fan-shaped wiring exports the first scanning signal step by step, in M1 the first scanning signals that M1 first order gate electrode side sector wiring exports
The first useful signal mutually stagger in time between each other namely M1 the first useful signals are not overlapped in timing.
Likewise, array substrate further includes M2 second level gate electrode side sector wiring, each second level gate electrode side sector wiring is defeated step by step
Second scanning signal out, the second useful signal in M2 the second scanning signals that M2 second level gate electrode side sector wiring exports
Mutually stagger namely M2 the second useful signals be not overlapped in timing ... Mi i-stage grid in time between each other
Pole side sector wiring, each i-stage gate electrode side sector wiring export the i-th scanning signal step by step, and Mi i-stage gate electrode side sector is matched
The i-th useful signal in Mi the i-th scanning signals of line output mutually staggers in time between each other namely Mi i-th has
Effect signal is not overlapped in timing.And in timing, M2 the second useful signals are corresponding with first useful signal；M3
A third useful signal is corresponding with second useful signal；Mn the n-th useful signals and (n-1)th useful signal pair
It answers.
It should be noted that do not limited in the present embodiment M1, M2 ... the relationship between Mi ... Mn, M1, M2 ...
Mi ... Mn can may be the different numerical value of value for the identical numerical value of value.Specific value can be according to practical Electronic Paper
Longitudinal resolution and think that border width to be achieved is related.Wherein, the longitudinal direction point of (M1 × M2 × ... Mn) and Electronic Paper
Resolution is equal.
Each pixel unit gated after " with logic " calculates by control in the first useful signal to the n-th useful signal,
Namely in each pixel unit, when the 1st scanning signal to the (n-1)th scanning signal is useful signal, the n-th scanning signal is used for
Control corresponding pixel unit gating.As long as having a scanning signal is non-effective signal, corresponding pixel unit will not be by
Gating.
It should be noted that not limiting the value of n in the present embodiment, as long as it is greater than or equal to 2, can greatly reduce
The number of gate electrode side sector wiring, thus the space that the gate electrode side sector wiring for substantially reducing Electronic Paper occupies, and then reduce side
The width of frame.By the way that multiple grades gate electrode side sector wiring is arranged in the embodiment of the present invention, and multiple grades gate electrode side is fan-shaped
After the logical signal of wiring carries out " with logic " calculating, realize that M1+M2+ ... Mn gate electrode side gate wirings control M1 × M2
× ... the strobe state of Mn row pixel unit, compared with the existing technology in M1 × M2 × ... the gating shape of Mn row pixel unit
State need M1 × M2 × ... Mn gate electrode side sector matches the wire laying mode of line traffic control, and the quantity for reducing gate electrode side sector wiring is
[(M1 × M2 × ... Mn)-(M1+M2+ ... Mn)], so as to greatly reduce the sky that gate electrode side sector wiring occupies frame
Between, Electronic Paper frame is further narrow as, narrow frame is further realized in prior art basis.
Specifically for example, wire laying mode in the prior art is used to realize that longitudinal resolution controls for 1024 Electronic Paper,
I.e. Electronic Paper has 1024 row pixel units, and each gate electrode side sector wiring occupied space is effectively aobvious by 7.5 μm of minimum value calculating
Show that area two sides are respectively necessary for wiring 512, occupied space is 1024/2*7.5=3840 μm, i.e. the frame of Electronic Paper is about
4mm；And Electronic Paper array substrate wire laying mode provided by the invention is used, and it is routed and realizes only with most simple two-stage, i.e. n=2,
M1 is assumed to be 2, then M2 is 512, and 2+512=514 gate electrode side sector wiring is needed to realize control 2*512=1024 row pixel altogether
The strobe state of unit, the frame of Electronic Paper can be changed to 514/2*7.5=1927.5 μm, namely about 1.9mm.If M1=4,
M2 is 256, and 4+256=260 gate electrode side sector wiring is needed to realize the gating shape of control 2*512=1024 row pixel unit altogether
State, the frame of Electronic Paper can be changed to 260/2*7.5=975 μm, namely about 1mm.In other instances, array substrate can be with
Including the third level, the fourth stage, level V etc. gate electrode side sector wiring etc., calculated by formula it is available, longitudinally point
In the case that resolution is constant, when series is more namely when the value of n is bigger, of the gate electrode side sector wiring used
Number is fewer, to so that n is the bigger the better, can compare in the present embodiment and not do according to the actual situation during actual fabrication
It limits.
Illustrate array substrate provided in the present invention below by specific example and its realizes the principle of narrow frame.
Fig. 2, Fig. 3 and Fig. 4 are referred to, Fig. 2 is 24 row pixel unit strobe cases of control provided in an embodiment of the present invention
Array substrate overlooking structure diagram, when Fig. 3 is the scanning signal on each gate electrode side sector wiring in array substrate shown in Fig. 2
Sequence figure, Fig. 4 are the array substrate plan structure signal that 24 row pixel unit strobe cases are controlled using prior art wire laying mode
Figure.
As shown in Fig. 2, the array substrate includes 2 groups of gate electrode side sector wiring groups, respectively M1 first order gate electrode side
Fan-shaped wiring and M2 second level gate electrode side sector wiring, M1, M2 are positive integer, and M1, M2≤2.It is corresponding, each pixel list
Member includes concatenated first switch tube 311 and second switch 312；The first end of first switch tube 311 and multiple pictures of same column
The first end of first switch tube 311 in plain unit is connected；The of the second end of first switch tube 311 and second switch 312
One end is connected, and the second end of second switch 312 is connected with the pixel electrode 40 in the pixel unit where it；First switch tube
311 control terminal is connected with a first order gate electrode side sector wiring；The control terminal of second switch 312 and a second level grid
Pole side sector wiring is connected.
Continuing with referring to fig. 2, M1=4, M2=6 in the present embodiment such as scheme to control M1*M2=24 row pixel unit
Shown, 4 first order gate electrode side sector wirings are respectively G1-1, G1-2, G1-3, G1-4；6 second level gate electrode side sector wirings
Respectively G2-1, G2-2, G2-3, G2-4, G2-5, G2-6.Wherein, each pixel unit is fan-shaped with a first order gate electrode side
Wiring and a second level gate electrode side sector wiring are connected；In this regard, each first order gate electrode side sector wiring is separately connected 6 row pictures
Plain unit, namely as shown in Fig. 2, first order gate electrode side sector wiring G1-1 connects the pixel unit of the 1st row to the 6th row simultaneously
The first of first switch tube 311, first order gate electrode side sector wiring G1-2 while the pixel unit of connection the 7th row to the 12nd row opens
Pipe 311 ... is closed, and the second switch 312 of the 1st row, the 7th row, the 13rd row, the 19th row pixel unit connects a second level
The connection of second switch 312 of the 6th row of gate electrode side sector wiring G2-1 ... ..., the 12nd row, the 18th row, the 24th row pixel unit
One second level gate electrode side sector wiring G2-6, to realize (M1+M2=4+6=) 10 gate electrode side sectors with line traffic control
(M1*M2=4*6=) gating of 24 row pixel units.
The embodiment of the invention also provides a kind of driving methods of Electronic Paper, comprising: fan-shaped to M1 first order gate electrode side
Wiring inputs the first useful signal step by step, successively to control the opening of the first switch tube in multiple pixel units；To M2 second
Grade gate electrode side sector wiring inputs the second useful signal step by step, is beaten with successively controlling the second switch in multiple pixel units
It opens；Wherein, in timing, M1 the first useful signals are mutually staggered, and M2 the second useful signals mutually stagger, and M2 second
Useful signal is corresponding with first useful signal.
Fig. 3 is referred to, the sequential relationship of each gate electrode side sector wiring of array substrate shown in Fig. 2 is shown in Fig. 3,
In each first order gate electrode side sector wiring export the first scanning signal step by step, each second level gate electrode side sector wiring by
Grade exports the second scanning signal, the first useful signal inputted step by step in the present embodiment to 4 first order gate electrode side sector wirings
For high level, 4 the first useful signals are mutually staggered, are not overlapped.Inputted step by step to 6 second level gate electrode side sector wirings
Two useful signals are also high level, and 6 the second useful signals are corresponding with first useful signal.
In real work, the first scanning signal on first order gate electrode side sector wiring is continuing for the first useful signal
In the process, the first switch tube 311 in pixel unit 40 connected to it is opened, at this point, on the gate electrode side sector wiring of the second level
The second effective scanning signal be used to open the second switch of the pixel unit 40 connecting with second level gate electrode side sector wiring
312；To realize the gating for successively controlling 24 row pixel units.
In the present embodiment, it is illustrated so that useful signal is high level as an example, but the embodiment of the present invention does not limit effectively
Signal is high level or low level, specifically depending on actual conditions.It should be noted that first switch tube in the present embodiment
311 and second switch 312 can be N-type transistor, can also be P-type transistor.When first switch tube 311 and second
When switching tube 312 is N-type transistor, the useful signal is high level；When the first switch tube 311 and second switch
312 when being P-type transistor, and the useful signal is low level.The application is to the first switch tube 311, second switch
312 specific type and without limitation, specifically depending on actual conditions.
Fig. 4 is referred to, 24 row pixel units are controlled using wire laying mode in the prior art and need 24 gate electrode side sectors
Wiring, it is assumed that gate electrode side sector wiring the space occupied is 1 unit, then 24 gate electrode side sector wirings in the prior art
Needing the space occupied is 24 units, the area border 05 that a portion is arranged in boundary viewing area namely Fig. 4；And
Using array substrate shown in Fig. 2, then only needing 4+6=10 gate electrode side sector wiring, i.e. the space occupied is 10 units,
Occupied space becomes the 10/24=5/12 of the prior art, the occupancy in space is substantially reduced, so as to compared with the existing technology
Further realize narrow frame.As shown in Fig. 2, if the width of 10 units is less than the width in the area border 50 of Electronic Paper,
All gate electrode side sector wirings can be produced on the area border 50, so that the width of frame is 0, that is, side be omitted
Frame area space so that Electronic Paper becomes frame-free displaying device, and then is more in line with the demand of user.
It on the basis of the above embodiments, is this hair with reference to Fig. 5 and Fig. 6, Fig. 5 in another embodiment of the application
The structural schematic diagram for the array substrate that bright embodiment provides, Fig. 6 are the driver' s timing schematic diagram of array substrate shown in fig. 5；With
Unlike above-described embodiment, Fig. 5 is referred to, gate electrode side sector wiring includes 3 groups in the present embodiment, the respectively M1 first order
Gate electrode side sector wiring, M2 second level gate electrode side sector wiring and M3 third level gate electrode side sector wiring, M1, M2, M3 are
Positive integer, and M1, M2, M3≤2.Corresponding, each pixel unit includes concatenated first switch tube 321, second switch 322
With third switching tube 323；The first end of first switch tube 321 and the first switch tube 321 in multiple pixel units of same column
First end is connected；The second end of first switch tube 321 is connected with the first end of second switch 322, and the of second switch 322
Two ends are connected with the first end of third switching tube 323, the second end of third switching tube 323 and the picture in the pixel unit where it
Plain electrode 41 is connected；The control terminal of first switch tube 321 is connected with a first order gate electrode side sector wiring；Second switch
Control terminal is connected with a second level gate electrode side sector wiring；The control terminal of third switching tube 323 and a third level gate electrode side
Fan-shaped wiring is connected.
Continuing with referring to Fig. 5, M1=4, M2=3, M3=3 in the present embodiment, to control M1*M2*M3=36 row pixel
Unit, in Fig. 5, underlying gate electrode side sector wiring sequentially consist of 4 first order gate electrode side sector wiring G1-1,
G1-2,G1-3,G1-4；3 second level gate electrode side sector wiring G2-1, G2-2, G2-3 and 3 third level gate electrode side sector wirings
G3-1,G3-2,G3-3.The label of each gate electrode side sector wiring is not indicated due to drawing length, in attached drawing 5.Wherein, often
A pixel unit is connected with a first order gate electrode side sector wiring, a second level gate electrode side sector wiring and a third
Grade gate electrode side sector wiring is connected；In this regard, each first order gate electrode side sector wiring connects M2*M3=9 row pixel simultaneously respectively
Unit, namely as shown in figure 5, first order gate electrode side sector wiring G1-1 connects the of the pixel unit of the 1st row to the 9th row simultaneously
The first of one switching tube 321, first order gate electrode side sector wiring G1-2 while the pixel unit of connection the 10th row to the 18th row opens
Close pipe 321 ...；And each second level gate electrode side sector wiring connects M1*M3=12 row pixel unit simultaneously respectively, Ye Jiru
Shown in Fig. 5, second level gate electrode side sector wiring G2-1 connects the 1st the-the 3 row of row, the 10th the-the 12 row of row, the 19th row-the simultaneously
21 rows, the 28th the-the 30 row of row pixel unit second switch 322, second level gate electrode side sector wiring G2-2 connects simultaneously
4th the-the 6 row of row, the 13rd the-the 15 row of row, the 22nd the-the 24 row of row, the 31st the-the 33 row of row pixel unit second switch
322, second level gate electrode side sector wiring G2-3 simultaneously connect the 7th the-the 9 row of row, the 16th the-the 18 row of row, the 25th the-the 27 row of row,
The second switch 322 of the pixel unit of 34th the-the 36 row of row；And each third level gate electrode side sector wiring connects simultaneously respectively
M1*M2=12 row pixel unit, namely as shown in Figure 5, third level gate electrode side sector wiring G3-1 connects [(m*3+ simultaneously
1), m=0,1,2 ... 11] the third switching tube 323 of the pixel unit of row, third level gate electrode side sector wiring G3-2 connect simultaneously
Connect the third switching tube 323 of the pixel unit of [(m*3+2), m=0,1,2 ... 11] row, third level gate electrode side sector wiring
G3-3 connects the third switching tube 323 of the pixel unit of [(m*3+3), m=0,1,2 ... 11] row simultaneously.By to 3 groups of grid
Pole side sector wiring inputs effective scanning signal, realizes that (M1+M2+M3=4+3+3=) 10 gate electrode side sectors match line traffic control
(M1*M2*M3=4*3*3=) gating of 36 row pixel units.
The embodiment of the invention also provides a kind of driving methods of Electronic Paper, comprising: fan-shaped to M1 first order gate electrode side
Wiring inputs the first useful signal step by step, successively to control the opening of the first switch tube in multiple pixel units；To M2 second
Grade gate electrode side sector wiring inputs the second useful signal step by step, is beaten with successively controlling the second switch in multiple pixel units
It opens；Third useful signal is inputted step by step to M3 third level gate electrode side sector wiring, successively to control in multiple pixel units
Third switching tube is opened；Wherein, in timing, M1 the first useful signals are mutually staggered, and M2 the second useful signals are mutually wrong
It opens, and M2 the second useful signals are corresponding with first useful signal；M3 third useful signal mutually staggers, and M3 the
Three useful signals are corresponding with second useful signal.
Fig. 6 is referred to, the sequential relationship of each gate electrode side sector wiring of array substrate shown in Fig. 5 is shown in Fig. 6,
In each first order gate electrode side sector wiring export the first scanning signal step by step, each second level gate electrode side sector wiring by
Grade the second scanning signal of output, each third level gate electrode side sector wiring exports third scanning signal step by step, in the present embodiment
The first useful signal inputted step by step to 4 first order gate electrode side sector wirings is high level, and 4 the first useful signals are mutually wrong
It opens, is not overlapped.The second useful signal inputted step by step to 3 second level gate electrode side sector wirings is also high level, and 3 second
Useful signal is corresponding with first useful signal；The third inputted step by step to 3 third level gate electrode side sector wirings is effectively believed
It number is also high level, and 3 third useful signals are corresponding with second useful signal.
In real work, the first scanning signal on first order gate electrode side sector wiring is continuing for the first useful signal
In the process, first switch tube 321 in pixel unit 41 connected to it is opened, and the on the gate electrode side sector wiring of the second level
Two scanning signals are in the time-continuing process of the second useful signal, and the second switch 322 in pixel unit 41 connected to it is beaten
It opens, at this point, the third effective scanning signal on third level gate electrode side sector wiring is used to open and matches with third level gate electrode side sector
The third switching tube 323 of the pixel unit 41 of line connection, to realize the gating for successively controlling 36 row pixel units.
In the present embodiment, it is illustrated so that useful signal is high level as an example, but the embodiment of the present invention does not limit effectively
Signal is high level or low level, specifically depending on actual conditions.It should be noted that first switch tube in the present embodiment
321, second switch 322 and third switching tube 323 can be N-type transistor, can also be P-type transistor.When first
When switching tube 321, second switch 322 and third switching tube 323 are N-type transistor, the useful signal is high level；When
When the first switch tube 321, second switch 322 and third switching tube 323 are P-type transistor, the useful signal is
Low level.The application does not do the specific type of the first switch tube 321, second switch 322 and third switching tube 323
It limits, specifically depending on actual conditions.
Fig. 7 is referred to, 36 row pixel units are controlled using wire laying mode in the prior art and need 36 gate electrode side sectors
Wiring, it is assumed that gate electrode side sector wiring the space occupied is 1 unit, then 36 gate electrode side sector wirings in the prior art
Needing the space occupied is 36 units, the area border that a portion is arranged in boundary viewing area namely Fig. 7；And it adopts
With array substrate shown in fig. 5, then only needing 4+3+3=10 gate electrode side sector wiring, i.e. the space occupied is 10 units,
Occupied space becomes the 10/36=5/18 of the prior art, the occupancy in space is substantially reduced, so as to compared with the existing technology
Further realize narrow frame.As shown in figure 5, if the width of 10 units is less than the width in the area border 51 of Electronic Paper,
All gate electrode side sector wirings can be produced on the area border 51, so that the width of frame is 0, that is, side be omitted
Frame area space so that Electronic Paper becomes frame-free displaying device, and then is more in line with the demand of user.
Correspondingly, the embodiment of the present application also provides a kind of Electronic Paper, including the array as described in above-mentioned all embodiments
Substrate.As shown in figure 8, being the schematic diagram of the section structure of Electronic Paper provided by the invention, Electronic Paper 800 includes:
The protective film 801 and array substrate being oppositely arranged, array substrate include: pixel electrode 804, substrate 807, TFT806
With gate electrode side sector wiring 805, TFT806 and gate electrode side sector wiring 805 are formed in substrate 807 towards the one of protective film 801
Side, each section connection relationship are as shown in Figure 8.The side of protective film 801 towards substrate 807 is provided with public electrode 802, common electrical
Further include electrocoating film 803 between pole 802 and pixel electrode 804, electrophoresis particle, the electrophoresis grain are mingled among electrocoating film 803
Son is exactly that can move about under the action of electric field.
During electronic paper display, by the mobile position of electric field controls electrophoresis particle, pass through mobile position control light
Reflection case, thus realize needed for brightness.It, can be by electronics since the movement of electrophoresis particle is mobile by electric field
Voltage appropriate is added between the public electrode 802 and pixel electrode 804 in each region of paper, generates echo area and uptake zone figure
Case can form pattern.
The color of the electrophoresis particle may include black and white, form the Electronic Paper of white and black displays, can also include
Other colors do not limit this in the present embodiment to form the Electronic Paper of colored display.
Electronic Paper provided by the invention, using the array substrate of above-mentioned Electronic Paper, due to the number of gate electrode side sector wiring
It greatly reducing, the frame of Electronic Paper can further realize narrow frame, meanwhile, the structure of the driving chip of Electronic Paper and control are multiple
Miscellaneous degree can reduce, to reduce the cost of driving chip, and then reduce the production cost of Electronic Paper.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight
Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of array substrate of Electronic Paper characterized by comprising
N group gate electrode side sector wiring group, n are positive integer, and n≤2；
The n group gate electrode side sector wiring group includes:
Mi i-stage gate electrode side sector wiring, each i-stage gate electrode side sector wiring export the i-th scanning signal step by step,
In, i is positive integer, and i=1,2 ... ... n；Mi is positive integer, and Mi≤2；
Multiple pixel units arranged in arrays, each pixel unit are connected with an i-stage gate electrode side sector wiring,
I is positive integer, and i=1,2 ... ... n；In each pixel unit include be sequentially connected in series first switch tube ... n-th opens
Guan Guan；First end and the second end phase of adjacent switching tube in intermediate multiple switch pipe in concatenated multiple switch pipe
Connect, and the first end of first switch tube is connected with the first end of the first switch tube of the pixel unit of same column；The of n-th switching tube
Two ends are connected with the pixel electrode of place pixel unit；Wherein, the control terminal of first switch tube is fanned with a first order gate electrode side
Shape wiring is connected；The control terminal of second switch is connected with a second level gate electrode side sector wiring；... the control of the n-th switching tube
End processed is connected with n-th grade of gate electrode side sector wiring；
Wherein, in each pixel unit, when the 1st scanning signal to the (n-1)th scanning signal is useful signal, n-th is swept
Signal is retouched for controlling corresponding pixel unit gating.
2. the array substrate of Electronic Paper according to claim 1 characterized by comprising M1 first order gate electrode side fan
Shape wiring and M2 second level gate electrode side sector wiring, M1, M2 are positive integer, and M1, M2≤2.
3. the array substrate of Electronic Paper according to claim 2, which is characterized in that each pixel unit includes series connection
First switch tube and second switch；
The first end of the first switch tube is connected with the first end of the first switch tube in multiple pixel units of same column；It is described
The second end of first switch tube is connected with the first end of the second switch, the second end of the second switch and its place
Pixel unit in pixel electrode be connected；
The control terminal of the first switch tube is connected with a first order gate electrode side sector wiring；
The control terminal of the second switch is connected with a second level gate electrode side sector wiring.
4. the array substrate of Electronic Paper according to claim 3, which is characterized in that the first switch tube and described second
Switching tube is N-type transistor.
5. the array substrate of Electronic Paper according to claim 1 characterized by comprising M1 first order gate electrode side fan
Shape wiring, M2 second level gate electrode side sector wiring and M3 third level gate electrode side sector wiring, M1, M2, M3 are positive integer, and
M1、M2、M3≧2。
6. the array substrate of Electronic Paper according to claim 5, which is characterized in that each pixel unit includes series connection
First switch tube, second switch and third switching tube；
The first end of the first switch tube is connected with the first end of the first switch tube in multiple pixel units of same column；It is described
The second end of first switch tube is connected with the first end of the second switch, the second end of the second switch and described the
The first end of three switching tubes is connected, second end and the pixel electrode phase in the pixel unit where it of the third switching tube
Even；
The control terminal of the first switch tube is connected with a first order gate electrode side sector wiring；
The control terminal of the second switch is connected with a second level gate electrode side sector wiring；
The control terminal of the third switching tube is connected with a third level gate electrode side sector wiring.
7. the array substrate of Electronic Paper according to claim 6, which is characterized in that the first switch tube, described second
Switching tube and the third switching tube are N-type transistor.
8. a kind of Electronic Paper, which is characterized in that the array substrate including the Electronic Paper as described in claim 1-7 any one.
9. a kind of driving method of Electronic Paper, which is characterized in that
The Electronic Paper includes:
First order gate electrode side sector wiring group and second level gate electrode side sector wiring group；
The first order gate electrode side sector wiring group includes M1 first order gate electrode side sector wiring, each first order grid
Side sector wiring exports the first scanning signal step by step, wherein M1 is positive integer, and M1≤2；
The second level gate electrode side sector wiring group includes M2 second level gate electrode side sector wiring, each second level grid
Side sector wiring exports the second scanning signal step by step, wherein M2 is positive integer, and M2≤2；
Multiple pixel units arranged in arrays, each pixel unit with a first order gate electrode side sector wiring and one
A second level gate electrode side sector wiring is connected；
Each pixel unit includes concatenated first switch tube and second switch；
The first end of the first switch tube is connected with the first end of the first switch tube in multiple pixel units of same column；It is described
The second end of first switch tube is connected with the first end of the second switch, the second end of the second switch and its place
Pixel unit in pixel electrode be connected；
The control terminal of the first switch tube is connected with a first order gate electrode side sector wiring；
The control terminal of the second switch is connected with a second level gate electrode side sector wiring；
The driving method includes:
The first useful signal is inputted step by step to the M1 first order gate electrode side sector wirings, successively to control multiple pixels
The first switch tube in unit is opened；
The second useful signal is inputted step by step to the M2 second level gate electrode side sector wirings, successively to control multiple pixels
The second switch in unit is opened；
Wherein, in timing, M1 first useful signals are mutually staggered, and M2 second useful signals mutually stagger,
And M2 second useful signals are corresponding with first useful signal.
10. the driving method of Electronic Paper according to claim 9, which is characterized in that
The Electronic Paper further include: third level gate electrode side sector wiring group；
The third level gate electrode side sector wiring group includes M3 third level gate electrode side sector wiring, each third level grid
Side sector wiring exports third scanning signal step by step, wherein M3 is positive integer, and M3≤2；
Each pixel unit is also connected with a third level gate electrode side sector wiring simultaneously；
Each pixel unit further includes the third switching tube being connected between the second switch and the pixel electrode；
The first end of the third switching tube is connected with the second end of the second switch in the same pixel unit, institute
The second end for stating third switching tube is connected with the pixel electrode；
The control terminal of the third switching tube is connected with the third level gate electrode side sector wiring；
The driving method further include:
Third useful signal is inputted step by step to the M3 third level gate electrode side sector wirings, successively to control multiple pixels
The third switching tube in unit is opened；
Wherein, in timing, M1 first useful signals are mutually staggered, and M2 second useful signals mutually stagger,
And M2 second useful signals are corresponding with first useful signal；The M3 third useful signals are mutually wrong
It opens, and the M3 third useful signals are corresponding with second useful signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710212254.3A CN107065374B (en) | 2017-04-01 | 2017-04-01 | A kind of array substrate of Electronic Paper, Electronic Paper and its driving method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710212254.3A CN107065374B (en) | 2017-04-01 | 2017-04-01 | A kind of array substrate of Electronic Paper, Electronic Paper and its driving method |
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| CN107065374B true CN107065374B (en) | 2019-10-22 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4441507B2 (en) * | 2006-06-05 | 2010-03-31 | 株式会社日立製作所 | Liquid crystal display |
| CN101299124B (en) * | 2008-06-25 | 2010-06-02 | 昆山龙腾光电有限公司 | Array substrates of LCD devices |
| CN101740582B (en) * | 2008-11-26 | 2011-07-27 | 财团法人工业技术研究院 | Transistor array lower plate |
| CN103106881A (en) * | 2013-01-23 | 2013-05-15 | 京东方科技集团股份有限公司 | Gate driving circuit, array substrate and display device |
| CN103760693B (en) * | 2013-12-25 | 2016-06-29 | 深圳市华星光电技术有限公司 | The Wiring structure of array base palte |
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