CN107046021A - A kind of chip grade packaging structure and preparation method thereof - Google Patents
A kind of chip grade packaging structure and preparation method thereof Download PDFInfo
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- CN107046021A CN107046021A CN201710428100.8A CN201710428100A CN107046021A CN 107046021 A CN107046021 A CN 107046021A CN 201710428100 A CN201710428100 A CN 201710428100A CN 107046021 A CN107046021 A CN 107046021A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Abstract
The invention discloses a kind of chip grade packaging structure and preparation method thereof.The preparation method of the chip grade packaging structure includes：Multiple integrated circuits are formed on substrate, integrated circuit includes one or more electronic components and metal interconnection layer；Cut substrate to divide multiple integrated circuits in side of the substrate away from integrated circuit；Shielding metal level is formed in side of the substrate away from integrated circuit, the substrate side wall that the shielding cleaved line of metal level exposes extends to metal interconnection layer；Secondary cut is carried out along line of cut, to obtain multiple discrete chip grade packaging structures.Technical scheme provided in an embodiment of the present invention, realize the preparation of chip cascade screen metal level, avoid the signal interference between chip, formed after chip module without preparing module cascade screen metal level again, reach that facilitating chip module constitutes the beneficial effect of technique, in addition, chip module edge without setting the ground via of module cascade screen metal level again, and then reduce the size of chip module.
Description
Technical field
The present embodiments relate to shielding construction and its technology of preparing, more particularly to a kind of chip grade packaging structure and its system
Preparation Method.
Background technology
Shielding construction can avoid signal from disturbing, and belong to the conventional arrangement of available circuit.
Main shielding construction includes two kinds in the prior art, and one kind is metallic shield, is formed using metal, Neng Gouyu
The barrier shield buckle being correspondingly arranged on circuit board so that chip and electronic component in barrier shield are shielded.It is another to be
The shielding metal level used in chip module, is formed at chip module capsulation material surface, for shielding core using coating process
Each chip and electronic component in piece module.
The shielding of above two shielding construction is partial circuit, including multiple chips and multiple electronic components, although
This partial circuit shielded will not be influenceed by external circuit signals, but chip and electronics member inside this partial circuit
Also there is mutual signal interference between device.In addition, for the shielding metal level used in chip module, due to will be in core
Piece module outward flange sets ground via for shielding metal level, causes becoming large-sized for chip module.
The content of the invention
The present invention provides a kind of chip grade packaging structure and preparation method thereof, to avoid the signal between chip from disturbing, subtracts
Small chip module size, the composition technique of facilitating chip module.
In a first aspect, the embodiments of the invention provide a kind of preparation method of chip grade packaging structure, the chip-scale envelope
The preparation method of assembling structure includes：
One substrate is provided, multiple integrated circuits are formed over the substrate, the integrated circuit includes one or more electricity
Sub- component and metal interconnection layer；
Cut the substrate to divide the multiple integrated circuit, edge in side of the substrate away from the integrated circuit
The line of cut of the cutting, exposes part surface of the metal interconnection layer close to the substrate side；
Shielding metal level is formed in side of the substrate away from the integrated circuit, the shielding metal level is cut described in
The substrate side wall that secant exposes extends to the metal interconnection layer, realizes and electrically connects with the metal interconnection layer；
Secondary cut is carried out along the line of cut, to obtain multiple discrete chip grade packaging structures.
Second aspect, the embodiment of the present invention additionally provides a kind of chip grade packaging structure, the chip grade packaging structure bag
Include：
Substrate；
The integrated circuit on the substrate first surface is formed at, the integrated circuit includes one or more electronics member devices
Part and metal interconnection layer；
It is formed at shielding metal level of the substrate in the other surfaces in addition to the first surface, the shielding metal level
Electrically connected with the metal interconnection layer.
Technical scheme provided in an embodiment of the present invention, by providing a substrate, forms multiple integrated circuits on substrate, collection
Include one or more electronic components and metal interconnection layer into circuit, substrate is cut in side of the substrate away from integrated circuit
To divide multiple integrated circuits, along the line of cut of cutting, expose part surface of the metal interconnection layer close to substrate side, in substrate
Side away from integrated circuit forms shielding metal level, and it is mutual that the substrate side wall that the shielding cleaved line of metal level exposes extends to metal
Join layer, realize and electrically connect with metal interconnection layer, secondary cut is carried out along line of cut, to obtain multiple discrete wafer-level package knots
Structure, realize the preparation of chip cascade screen metal level, it is to avoid the signal interference between chip, is formed after chip module without again
Module cascade screen metal level is prepared, has reached that facilitating chip module constitutes the beneficial effect of technique, in addition, chip module edge
Without setting the ground via of module cascade screen metal level again, and then reduce the size of chip module.
Brief description of the drawings
In order to clearly illustrate the technical scheme of exemplary embodiment of the present, below to needed for description embodiment
The accompanying drawing to be used does a simple introduction.Obviously, the accompanying drawing introduced is a part of embodiment of the invention to be described
Accompanying drawing, rather than whole accompanying drawings, for those of ordinary skill in the art, on the premise of not paying creative work, may be used also
To obtain other accompanying drawings according to these accompanying drawings.
Fig. 1 is a kind of schematic flow sheet of the preparation method of chip grade packaging structure provided in an embodiment of the present invention；
Fig. 2 is the overlooking the structure diagram to form multiple integrated circuit back substrates；
Fig. 3 is the cross-sectional view of the dotted line AB along along Fig. 2；
Fig. 4 a are cross-sectional views when being cut to substrate；
Fig. 4 b are to cut the cross-sectional view after substrate；
Fig. 5 is the cross-sectional view to be formed after shielding metal level；
Fig. 6 is cross-sectional view when carrying out secondary cut；
Fig. 7 is the cross-sectional view of chip grade packaging structure.
Embodiment
Further to illustrate the present invention to reach the technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Accompanying drawing and preferred embodiment, to the specific embodiment party according to a kind of RF IC proposed by the present invention and preparation method thereof
Formula, structure, feature and its effect, are described in detail as after.
The embodiments of the invention provide a kind of preparation method of chip grade packaging structure, the preparation method includes：
One substrate is provided, multiple integrated circuits are formed over the substrate, the integrated circuit includes one or more electricity
Sub- component and metal interconnection layer；
Cut the substrate to divide the multiple integrated circuit, edge in side of the substrate away from the integrated circuit
The line of cut of the cutting, exposes part surface of the metal interconnection layer close to the substrate side；
Shielding metal level is formed in side of the substrate away from the integrated circuit, the shielding metal level is cut described in
The substrate side wall that secant exposes extends to the metal interconnection layer, realizes and electrically connects with the metal interconnection layer；
Secondary cut is carried out along the line of cut, to obtain multiple discrete chip grade packaging structures.
Technical scheme provided in an embodiment of the present invention, by providing a substrate, forms multiple integrated circuits on substrate, collection
Include one or more electronic components and metal interconnection layer into circuit, substrate is cut in side of the substrate away from integrated circuit
To divide multiple integrated circuits, along the line of cut of cutting, expose part surface of the metal interconnection layer close to substrate side, in substrate
Side away from integrated circuit forms shielding metal level, and it is mutual that the substrate side wall that the shielding cleaved line of metal level exposes extends to metal
Join layer, realize and electrically connect with metal interconnection layer, secondary cut is carried out along line of cut, to obtain multiple discrete wafer-level package knots
Structure, realize the preparation of chip cascade screen metal level, it is to avoid the signal interference between chip, is formed after chip module without again
Module cascade screen metal level is prepared, has reached that facilitating chip module constitutes the beneficial effect of technique, in addition, chip module edge
Without setting the ground via of module cascade screen metal level again, and then reduce the size of chip module.
Above is the core concept of the application, below in conjunction with the accompanying drawing in the embodiment of the present invention, to the embodiment of the present invention
In technical scheme be clearly and completely described, it is clear that described embodiment is only a part of embodiment of the invention,
Rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creative labor
Under the premise of dynamic, the every other embodiment obtained belongs to the scope of protection of the invention.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
It is different from other embodiment described here using other to implement, those skilled in the art can be without prejudice in the present invention
Similar popularization is done in the case of culvert, therefore the present invention is not limited by following public specific embodiment.
Secondly, the present invention is described in detail with reference to schematic diagram, when the embodiment of the present invention is described in detail, for purposes of illustration only, table
The schematic diagram of showing device device architecture not makees partial enlargement according to general ratio, and the schematic diagram is example, its
This should not limit the scope of protection of the invention.In addition, the three dimensions of length, width and height should be included in actual fabrication
Size.
Fig. 1 is a kind of schematic flow sheet of the preparation method of chip grade packaging structure provided in an embodiment of the present invention.This reality
The preparation method for applying the chip grade packaging structure of example offer is applied to prepare the encapsulating structure with chip cascade screen metal level.
Specifically, as shown in figure 1, the preparation method of the chip grade packaging structure specifically include it is as follows：
Step 110, one substrate of offer, form multiple integrated circuits over the substrate, and the integrated circuit includes one
Or multiple electronic components and metal interconnection layer.
Preparation method of the present embodiment to chip grade packaging structure so that substrate is silicon substrate as an example is illustrated below.Fig. 2
It is the overlooking the structure diagram to form multiple integrated circuit back substrates.Fig. 3 is the cross-sectional view of the dotted line AB along along Fig. 2.
As shown in Figures 2 and 3 there is provided a substrate 10, multiple integrated circuits 100 are formed over the substrate 10, and integrated circuit 100 includes one
Or multiple electronic components 101 and metal interconnection layer 102.
Exemplary, as shown in Fig. 2 multiple integrated circuits 100 can be with arranged in arrays on the substrate 10.
It should be noted that the size of each electronic component 101 in integrated circuit 100 is smaller, therefore on every substrate 10
The quantity of integrated circuit 100 of formation is more, as shown in Figure 2.Correspondence obtains one after each integrated circuit 100 is handled through subsequent technique
Individual chip grade packaging structure, it is exemplary, chip grade packaging structure can be chip, be it is clearer illustrate it is multiple on substrate
Each integrated circuit 100 is expressed as an independent rectangular block by the arrangement mode of integrated circuit 100, Fig. 2 partial enlarged drawing,
And between adjacent integrated circuit 100 and obvious boundary is not present in actual production, as shown in Figure 3.Referring also to Fig. 2 and Fig. 3 can
Know, Fig. 3, which is illustrated, is not present obvious boundary between three adjacent integrated circuits 100, each integrated circuit 100, closer in fact
The facilities of integrated circuit 100 in the production of border.In addition, with continued reference to Fig. 3, as the general step in integrated circuit technology,
The metal interconnection layer 102 of multiple integrated circuits 100 is formed simultaneously.
It should also be noted that, Fig. 3 is only illustrated so that each integrated circuit 100 includes two transistors as an example, not
The restriction of the species of electronic component 101, quantity and the position that include to integrated circuit 100.In other implementations of the present embodiment
In mode, the electronic component 101 that integrated circuit 100 includes can also include other components in addition to a transistor, for example
Electric capacity or resistance etc., the quantity of electronic component 101 and position can be carried out rational by designer according to actual needs
Set.In addition, multiple integrated circuits 100 can be with identical, as shown in Figure 3；Multiple integrated circuits 100 can also part it is identical or each
Differ, the present embodiment is not specifically limited to this.
Step 120, in side of the substrate away from the integrated circuit cut the substrate to divide the multiple collection
Into circuit, along the line of cut of the cutting, expose part surface of the metal interconnection layer close to the substrate side.
Fig. 4 a are cross-sectional views when being cut to substrate.Fig. 4 b are to cut the cross-section structure signal after substrate
Figure.As shown in fig. 4 a, cut substrate 10 to divide multiple integrated circuits 100 in side of the substrate 10 away from integrated circuit 100.Such as
Shown in Fig. 4 b, along the line of cut 11 of cutting, expose part surface of the metal interconnection layer 102 close to the side of substrate 10.
It should be noted that the cutting in this step is only cut to substrate 10, the cutting technique used can be many
Kind.Exemplary, substrate 10 can be cut using laser cutting parameter, operating personnel can cause laser by the setting of parameter
Cut and stop in the interface of substrate 10 and metal interconnection layer 102, and then realize that accurate substrate 10 is cut.Optionally, also may be used
To be cut using cutter to substrate 10, but its operating speed is likely lower than laser cutting.It is worth noting that, if needing
Will, it can accomplish that any layer metal interconnection layer 102 will not be cut in this step, to avoid the shielding metal being subsequently formed
The generation of the disorderly phenomenon of signal caused by layer is electrically connected with multiple layer metal interconnection layer 102.
It should also be noted that, the width of line of cut 11 is determined by beam width, can as needed it be entered by operating personnel
Row is set.Due to needing to form shielding metal level on the side wall of substrate 10 at follow-up line of cut 11, therefore, the width of line of cut 11 should
It is configured with reference to the preset thickness of shielding metal level, at least should be greater than shielding twice of metal layer thickness, for more convenient shielding
The deposition of metal level, on the premise of the normal work of integrated circuit 100 is not influenceed, what the width of line of cut 11 should be set as far as possible
It is larger.
Step 130, shielding metal level, the shielding metal level are formed in side of the substrate away from the integrated circuit
The substrate side wall exposed through the line of cut extends to the metal interconnection layer, realizes and electrically connects with the metal interconnection layer.
Fig. 5 is the cross-sectional view to be formed after shielding metal level.As shown in figure 5, in substrate 10 away from integrated circuit
100 side forms shielding metal level 20, and it is mutual that the side wall of substrate 10 that the shielding cleaved line 11 of metal level 20 exposes extends to metal
Join layer 102, realize and electrically connect with metal interconnection layer 102.
In the present embodiment, shielding metal level 20 can be formed using multiple coating films mode, it is for instance possible to use film splashes
Penetrate mode or electron-beam evaporation mode is formed.
It should be noted that the corresponding metal level 20 that shields of multiple integrated circuits 100 can be a flood structure, Neng Gou
Formed in same processing step, i.e., the corresponding metal level 20 that shields of adjacent integrated circuit 100 has annexation, as shown in Figure 5.
In the other embodiment of the present embodiment, the corresponding metal level 20 that shields of each integrated circuit 100 can also be formed respectively, this
In the case of, the corresponding metal level 20 that shields of adjacent integrated circuit 100 can be connected and can also be not connected to, can be by adjusting each collection
Coverage into the correspondence shielding metal level 20 of circuit 100 is configured.
It should also be noted that, the partial earthing of metal interconnection layer 102 that metal level 20 is electrically connected is shielded in the present embodiment, with
Realize that the ground connection of shielding metal level 20 is set.
Further, before side of the substrate 10 away from the integrated circuit 100 forms shielding metal level 20, also
It can include：The substrate 10 is thinned in side of the substrate 10 away from the integrated circuit 100.
Step 140, along the line of cut carry out secondary cut, to obtain multiple discrete chip grade packaging structures.
Fig. 6 is cross-sectional view when carrying out secondary cut.Fig. 7 is the cross-section structure signal of chip grade packaging structure
Figure.As shown in fig. 6, secondary cut is carried out along line of cut 11, to obtain multiple chip grade packaging structures as shown in Figure 7.
Optionally, the cutting and the secondary cut can be carried out using same process.Such set causes twice
Cutting can use equipment of the same race, without more exchange device, reduce the equipment cost of cutting.Exemplary, the cutting and institute
Stating secondary cut can be carried out using laser cutting parameter.It is cut by laser speed fast and easily accurate by device parameter regulation realization
Control, be a kind of cutting technique of better performances.It is understood that due to cutting and the effect of secondary cut is respectively point
From substrate 10 and separation metal interconnection layer 102, therefore, in the other embodiment of the present embodiment, cut and secondary cut
It can be carried out using different technique, for example, cutting is using laser cutting, secondary cut is cut using stage property.
Optionally, before secondary cut is carried out along the line of cut, it can also include：Using welded ball array encapsulation or grid
The mode of lattice array package is packaged technique.To form the external pin of chip grade packaging structure, it is easy to the application of chip.
The technical scheme that the present embodiment is provided, by providing a substrate, forms multiple integrated circuits, integrated electricity on substrate
Road includes one or more electronic components and metal interconnection layer, cuts substrate to draw in side of the substrate away from integrated circuit
Divide multiple integrated circuits, along the line of cut of cutting, expose part surface of the metal interconnection layer close to substrate side, it is remote in substrate
The side of integrated circuit forms shielding metal level, and the substrate side wall that the shielding cleaved line of metal level exposes extends to metal interconnection
Layer, realizes with metal interconnection layer and electrically connects, and secondary cut is carried out along line of cut, to obtain multiple discrete wafer-level package knots
Structure, realize the preparation of chip cascade screen metal level, it is to avoid the signal interference between chip, is formed after chip module without again
Module cascade screen metal level is prepared, has reached that facilitating chip module constitutes the beneficial effect of technique, in addition, chip module edge
Without setting the ground via of module cascade screen metal level again, and then reduce the size of chip module.
Present invention also offers a kind of chip grade packaging structure, with continued reference to Fig. 7, chip grade packaging structure includes：Substrate
10, the integrated circuit 100 on the first surface of substrate 10 is formed at, the integrated circuit 100 includes one or more electronics
Component 101 and metal interconnection layer 102, are formed at shielding of the substrate 10 in the other surfaces in addition to the first surface
Metal level 20, the shielding metal level 20 is electrically connected with the metal interconnection layer 102.
Wherein, the substrate 10 can include the substrates such as silicon substrate, glass substrate, quartz substrate and Sapphire Substrate.
Optionally, the shielding metal level 20 can include at least one layer of conductive metal layer.
Specifically, when the shielding metal level 20 includes one layer of conductive metal layer, the material of the shielding metal level 20
Copper can be included.Copper is a kind of higher shielding metal layer material of cost performance, and amount of storage is big, is easily obtained.In the present embodiment
In other embodiment, shielding metal layer material can also be other conductive metallic materials, can be selected as the case may be
Select.
When the shielding metal level 20 includes three layers of conductive metal layer, the shielding metal level 20 can be included close to institute
State the first conductive metal layer of the side of substrate 10, the 3rd conductive metal layer away from the side of substrate 10 and positioned at described the
The second conductive metal layer between one conductive metal layer and the 3rd conductive metal layer, the thickness of first conductive metal layer
Span can be 100-300nm, and the Thickness of second conductive metal layer may range from 10-20 μm, described the
The Thickness of three conductive metal layers may range from 1-5 μm.
Optionally, the material of first conductive metal layer can be the metal materials such as copper, aluminium, silver or gold, and first is conductive
Metal level can be formed as Seed Layer using electroless plating mode (such as sputtering or being evaporated in vacuo).Second conductive gold
The material for belonging to layer can be the metal materials such as copper, aluminium, silver or gold, and generally be formed using electroplating technology.In addition, the described 3rd leads
The material of metal layer can include nickel.3rd conductive metal layer is located at the outermost layer of shielding metal level 20, using corrosion resistance
Stronger metallic nickel materials the 3rd conductive metal layer of formation enables the 3rd conductive metal layer to be used as protective layer, it is to avoid first leads
Metal layer and the second conductive metal layer are corroded, it is ensured that shielding metal level 20 has preferable shielding character.It is appreciated that
, in the other embodiment of the present embodiment, the material of the 3rd conductive metal layer can also be similar to nickel characteristic for other
Metal material.
When the shielding metal level 20 includes at least two conductive metal layer, between conductive metal layer described in arbitrary neighborhood
Dielectric materials layer can be included.The present embodiment is not specifically limited to the number of plies of dielectric materials layer, and designer can be according to reality
Border needs to be selected.
In the present embodiment, at least one layer of conductive metal layer can include at least one layer of patterned conductive metal level.
Patterned conductive metal level can be used for realizing specific circuit structure, reach the effect of conductive metal layer multiplexing.
It should be noted that when shielding metal level 20 including multilayer conductive metal level, the kind of each conducting metal layer material
Class can part it is identical or different.In practical application, different chip grade packaging structures are different to the demand of shield effectiveness, can
The conductive metal layer number of plies and material included according to conditions such as usage scenarios to shielding metal level 20 is configured.
It should also be noted that, structure, material and the thickness of shielding metal level 20 can influence to shield metal level 20
Shield effectiveness.Therefore, during design shielding metal level 20, application scenarios etc. need to be considered to chip grade packaging structure shield effectiveness
Requirement and above-mentioned tripartite's noodles part.
The chip grade packaging structure that the present embodiment is provided includes substrate, is formed at the integrated circuit on substrate first surface,
Integrated circuit includes one or more electronic components and metal interconnection layer, is formed at other tables of substrate in addition to first surface
Shielding metal level on face, shielding metal level is electrically connected with metal interconnection layer, is realized the preparation of chip cascade screen metal level, is kept away
The signal interference between chip is exempted from, has been formed after chip module without preparing module cascade screen metal level again, reached simplified core
Piece module constitutes the beneficial effect of technique, in addition, chip module edge is without the ground connection for setting module cascade screen metal level again
Via, and then reduce the size of chip module.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art it is various it is obvious change,
Readjust, be combined with each other and substitute without departing from protection scope of the present invention.Therefore, although by above example to this
Invention is described in further detail, but the present invention is not limited only to above example, is not departing from present inventive concept
In the case of, other more equivalent embodiments can also be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (14)
1. a kind of preparation method of chip grade packaging structure, it is characterised in that including：
One substrate is provided, multiple integrated circuits are formed over the substrate, the integrated circuit includes one or more electronics member
Device and metal interconnection layer；
The substrate is cut in side of the substrate away from the integrated circuit to divide the multiple integrated circuit, along described
The line of cut of cutting, exposes part surface of the metal interconnection layer close to the substrate side；
Shielding metal level is formed in side of the substrate away from the integrated circuit, the shielding metal level is through the line of cut
The substrate side wall exposed extends to the metal interconnection layer, realizes and electrically connects with the metal interconnection layer；
Secondary cut is carried out along the line of cut, to obtain multiple discrete chip grade packaging structures.
2. preparation method according to claim 1, it is characterised in that the cutting and the secondary cut use identical work
Skill is carried out.
3. preparation method according to claim 2, its feature is being, the cutting and the secondary cut use laser
Cutting technique is carried out.
4. preparation method according to claim 1, it is characterised in that in side of the substrate away from the integrated circuit
Formed before shielding metal level, in addition to：
The substrate is thinned in side of the substrate away from the integrated circuit.
5. preparation method according to claim 1, it is characterised in that it is described along the line of cut carry out secondary cut it
Before, in addition to：
Technique is packaged by the way of welded ball array encapsulation or Background Grid array packages.
6. preparation method according to claim 1, it is characterised in that the multiple integrated circuit is in square over the substrate
Battle array arrangement.
7. a kind of chip grade packaging structure, it is characterised in that including：
Substrate；
Be formed at the integrated circuit on the substrate first surface, the integrated circuit include one or more electronic components with
And metal interconnection layer；
It is formed at shielding metal level of the substrate in the other surfaces in addition to the first surface, the shielding metal level and institute
State metal interconnection layer electrical connection.
8. chip grade packaging structure according to claim 7, it is characterised in that the substrate includes silicon substrate, glass lined
Bottom, quartz substrate and Sapphire Substrate.
9. chip grade packaging structure according to claim 7, it is characterised in that the shielding metal level includes at least one layer
Conductive metal layer.
10. chip grade packaging structure according to claim 9, it is characterised in that the shielding metal level is led including one layer
During metal layer, the material of the shielding metal level includes copper.
11. chip grade packaging structure according to claim 9, it is characterised in that the shielding metal level is included close to institute
State substrate side the first conductive metal layer, away from the substrate side the 3rd conductive metal layer and led positioned at described first
The second conductive metal layer between metal layer and the 3rd conductive metal layer；
The Thickness scope of first conductive metal layer is 100-300nm, the Thickness of second conductive metal layer
Scope is 10-20 μm, and the Thickness scope of the 3rd conductive metal layer is 1-5 μm.
12. chip grade packaging structure according to claim 11, it is characterised in that the material of the 3rd conductive metal layer
Including nickel.
13. chip grade packaging structure according to claim 9, it is characterised in that the shielding metal level includes at least two
During layer conductive metal layer, include dielectric materials layer between conductive metal layer described in arbitrary neighborhood.
14. chip grade packaging structure according to claim 9, it is characterised in that at least one layer of conductive metal layer bag
Include at least one layer of patterned conductive metal level.
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| CN114137280A (en) * | 2021-11-26 | 2022-03-04 | 成都芯进电子有限公司 | Hall effect current sensor |
| CN114547854A (en) * | 2022-01-13 | 2022-05-27 | 芯和半导体科技(上海)有限公司 | Chip packaging electromagnetic modeling system, method and device |
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| CN205881898U (en) * | 2016-07-18 | 2017-01-11 | 苏州日月新半导体有限公司 | Integrated circuit package |
| CN206806335U (en) * | 2017-06-08 | 2017-12-26 | 安徽安努奇科技有限公司 | A kind of chip grade packaging structure |
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| CN114137280A (en) * | 2021-11-26 | 2022-03-04 | 成都芯进电子有限公司 | Hall effect current sensor |
| CN114547854A (en) * | 2022-01-13 | 2022-05-27 | 芯和半导体科技(上海)有限公司 | Chip packaging electromagnetic modeling system, method and device |
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