CN107026140A - With welding positive semiconductor chip and the method for manufacturing semiconductor chip - Google Patents

With welding positive semiconductor chip and the method for manufacturing semiconductor chip Download PDF

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Publication number
CN107026140A
CN107026140A CN201611271992.7A CN201611271992A CN107026140A CN 107026140 A CN107026140 A CN 107026140A CN 201611271992 A CN201611271992 A CN 201611271992A CN 107026140 A CN107026140 A CN 107026140A
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Prior art keywords
metallic region
semiconductor chip
solder
devices
principal spread
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CN201611271992.7A
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CN107026140B (en
Inventor
A·格拉赫
T·卡利希
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Robert Bosch GmbH
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Robert Bosch GmbH
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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  • Engineering & Computer Science (AREA)
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Abstract

Semiconductor chip includes the semiconductor components and devices with the first principal spread direction and the second principal spread direction, the main extension plane that first principal spread direction and the formation of the second principal spread direction are arranged perpendicular to the stacking direction of semiconductor chip, welding first and second metallic region and dielectric regions are directly arranged on semiconductor components and devices, first metallic region and the second metallic region are electrically separated by dielectric regions, second metallic region is along the first principal spread direction and the first metallic region at a distance of the first spacing, it is characterized in that, the first solder of the 4th thickness degree under unwelded state with the three times at least corresponding to the first spacing is arranged in the first metallic region, the 3rd metallic region is arranged on the first solder, at least 5 times of threeth spacing of border of 3rd metallic region along the first principal spread direction and semiconductor components and devices equivalent to the 4th thickness degree of the first solder under unwelded state, first, second, 3rd metallic region and the sealed connection of the first solder material.

Description

With welding positive semiconductor chip and the method for manufacturing semiconductor chip
Technical field
It is used to manufacture semiconductor chip the present invention relates to a kind of semiconductor chip with semiconductor components and devices and one kind Method.
Background technology
In order to detect special parameter and in order to perform stress test on chip, should be connect one by one before manufacturing process terminates Logical simultaneously these semiconductor components and devices of electric measurement.Semiconductor components and devices is loaded into when performing stress test more than specific number According to it is possible thereby to find the fabrication error and defect in semiconductor components and devices.Connect for other poles internally with the component The component connect, it is impossible to improve the voltage for stress test greatly enough.For example in integrated circuit, intelligence or specific work( It is particularly the case in rate semiconductor.In the case of pseudo- Schottky diode, gate connection by chip metallization regularly Electrically connected with source connection.Thus grid oxic horizon can not possibly be detected by stress test.In the cut-off electricity of semiconductor components and devices Pressure can obtain similar difficulty when being limited by single chip integrated clamp circuit.Thus, for example for ignition device for motor vehicle The Zener diode that the maximum breakdown voltage of transistor can be integrated on chip is limited in 300V value.However, to examine The transistor of survey has 600V breakdown voltage.Therefore, because clamper, the voltage range for detection is limited in 300V, Make it impossible to carry out complete component detection.
It is well known, however, that feasible program, for stress mornitoring still can be performed when component includes different metal plane. Here, at least stress test can be performed before last layer of metallized plane is applied.This way has in component can It is feasible during the front of welding.In pseudo- Schottky diode, such as aluminum metallization layers on the upside of the chip on form electrically separated Source connection and gate connection.The grid oxic horizon in wafer layer can be tested on the time point.Grid and source electrode it Between turn on and manufactured in following processing step so that the last layer of metal of wafer technique is carried out after stress test The PROCESS FOR TREATMENT of layer.
Have the disadvantage herein, by the slice processing sequence that is carried out after stress test, there may be component wear.
The content of the invention
Semiconductor chip includes the semiconductor components and devices with the first principal spread direction and the second principal spread direction, wherein, First principal spread direction and the second principal spread direction form main extension plane, wherein, main extension plane is perpendicular to semiconductor chip Stacking direction arrangement.The first metallic region, at least one second metallic region and Jie are directly arranged on semiconductor components and devices Electric region.First metallic region and the second metallic region are can weld welding in other words.First metallic region and at least One the second metallic region is electrically separated by dielectric regions.At least one second metallic region is along the first principal spread direction and the first gold medal Belong to region at a distance of the first spacing.First weldering with fourth thickness degree is arranged under unwelded state in the first metallic region Material.4th thickness degree at least corresponds to three times of the first spacing.3rd metallic region is arranged on the first solder.3rd metal area Domain is welding and along the first principal spread direction and the spacing of component border the 3rd.3rd spacing is equivalent to unwelded At least five times of 4th thickness degree of the first solder in state.First metallic region, the second metallic region, the 3rd metallic region There is the sealed connection of material with the first solder.
It is the second metallic region for playing test panel and the main metal layer for playing semiconductor components and devices in this advantage The first metallic region between be electric insulation, and produce extend down to test panel along principal spread direction from main metal layer On closing the weld layer without shrinkage cavity.
In another configuration scheme, at least one foregoing second metallic region is surrounded by dielectric regions completely.
It is that test panel is outside main metal layer in other words master, the thus consistently main metallization of configuration in this advantage Layer master, the master such as source contact in other words.
In another configuration scheme, the first metallic region is surrounded by dielectric regions completely.
In another configuration scheme, border second of second metallic region along principal spread direction and semiconductor components and devices Spacing.
Herein advantageously, test panel can be arranged very close to the border land of semiconductor components and devices, thus substantially make member The testability of device becomes easy.
In another configuration scheme, the first metallic region has first layer thickness, and the second metallic region has the second thickness Degree, dielectric regions have third layer thickness.Here, first layer thickness and second layer thickness are more than third layer thickness.
It is in this advantage, welding material can more easily scatter, to form the sealed connection of material.
In another configuration scheme, semiconductor components and devices includes pseudo- Schottky diode.
Herein it is an advantage to be able to test semiconductor components and devices in a straightforward manner, particularly pseudo- Schottky diode Gate oxide.
Included according to the method for being used to manufacture the semiconductor chip with semiconductor components and devices of the present invention：In semiconductor element Structuring dielectric regions on device；First metallic region and the second metallic region are applied on semiconductor components and devices so that the One metallic region and the second metallic region are electrically separated from each other；First solder is applied in the first metallic region, passes through temperature step Rapid material is connected cohesively together the first metallic region, the second metallic region, the 3rd metallic region and the first solder.
It is just to perform stress test after complete wafer technique terminates so that after wafer technique terminates in this advantage Still the electrical connection of unlimited joint passes through Welder when by semiconductor die package to respective housings or corresponding assembly Skill step is carried out.
In another configuration scheme, semiconductor components and devices is by being temporarily switched on the first metallic region and/or the second metal area Domain is tested.
Other advantages are drawn from the following description to embodiment or by dependent claims.
Brief description of the drawings
The present invention is illustrated below according to preferred embodiment and accompanying drawing.
Accompanying drawing is shown：
Top views of the Fig. 1 according to semiconductor chip of the invention before a welding process；
The sectional view of hatching A-As ' of the Fig. 2 along Fig. 1 semiconductor chip according to the present invention before a welding process；
The sectional view of hatching A-As ' of the Fig. 3 along Fig. 1 semiconductor chip according to the present invention after the welding process；With And
Fig. 4 is used for the method for manufacturing the semiconductor chip according to the present invention.
Embodiment
Fig. 1 shows the top view of the semiconductor chip 100 according to the present invention.Semiconductor chip 100 has semiconductor element device Part 101.Arrangement plays the first metallic region of the main metal layer effect of semiconductor components and devices on semiconductor components and devices 101 102.First metallic region 102, which has, vacates portion, and at least one second metallic region 103 is arranged in this and vacated in portion.First gold medal The category metallic region 103 of region 102 and second arranges there is the first spacing 105 between them at each interval.Here, between first Not only extend away from 105 along the first principal spread direction x but also extend along the second principal spread direction y.Arranged in the first metallic region 102 Solder 107.The 3rd metallic region 108 is arranged on solder 107.3rd metallic region 108 is along the first principal spread direction x and partly Conductor component 101 is at a distance of the 3rd spacing 109.Here, the first metallic region 102 and the second metal 103 are welding.3rd Metallic region 108 especially has the solderable surface of plane.The material of 3rd metallic region 108 includes such as copper or nickel plating Copper.Solder 107 can be small welding plate or soldering paste.
In one embodiment, semiconductor components and devices 100 has multiple secondth areas 103.
Fig. 2 shows the sectional view of semiconductor chip 201.Here, in Fig. 2 with Fig. 1 meaning identicals feature have with Fig. 1 Reference marker identical after bit digital.In addition show, component 201 has the back face metalization layer 210 of whole surface construction.The back side Metal layer 210 is connected by weld layer 211 with the 4th metallic region 212 as lower metal interface.
Fig. 3 shows the sectional view according to semiconductor chip 301 of the invention after the welding process.With Fig. 2 meanings in Fig. 3 Identical feature has and bit digital after the reference marker identical in Fig. 2.
In one embodiment, the 3rd metallic region 108,208,308 overlap the first metallic region 102,202,302 and Second metallic region 103,203,303.Here, width of the solder 307 in its bottom point is less than the width on its summit, that is, Say, the trapezoidal configuration of solder 307.
In one embodiment, the first metallic region 102,202,302 and the second metallic region 103,203,303 have The thin sequence layer being made up of nickel and silver.3rd metallic region 108,208 and 308 is one of the housing of encapsulation of semiconductor chip Point.Solder 107,207 and 307 includes the slicken solder with positive volume discontinuities (Volumenvorsprung), wherein, solder 107th, 207,307 it is arranged only under unwelded state in the first metallic region 102,202,302.In addition, solder 107,207 and 307 have high wettability.
Semiconductor chip 100,200,300 can have forced diode, especially efficiency diode or puppet Xiao Te Based diode is used as component 101,201 and 301.These diodes are especially suitable in the generator of motor vehicle.MOS gate poles two Pole pipe may also serve as semiconductor components and devices 101 and 201.Further, it is possible to use power MOSFETS with clamp voltage and IGBTs。
Fig. 4 shows the method 400 for manufacturing the semiconductor chip with semiconductor components and devices.This method starts from step 410, its mode is：The structuring dielectric regions on semiconductor components and devices.In subsequent step 420 by the first metallic region and Second metallic region is applied on semiconductor components and devices so that the first metallic region and the second metallic region are electrically separated from each other. First solder is applied in the first metallic region in subsequent step 430.In subsequent step 450, by temperature step First metallic region, the second metallic region, same welding 3rd metallic region and the first solder material are connected cohesively together. Dielectric layer does not have solder wettability, but can by the 3rd metallic region to the lateral spacing having between semiconductor chip yet Realize the sealed connection of material.In other words, the 3rd metallic region has lateral in the first principal spread direction and the second principal spread direction Spacing, i.e. the 3rd metallic region protrude from semiconductor core.If there is solder positive volume to dash forward when being transitioned into liquid from solid-state Become, then liquid solder expands from the first metallic region through the 3rd metallic region to the second metallic region.It means that solder is logical Crossing the lateral spacing of the 3rd metallic region, laterally projecting portion outwards extends in other words, and in cooling with the first metallic region, the Two metallic regions and the 3rd metallic region realize the sealed connection of material.
Therefore, the first metallic region and the second metallic region are electrically connected to each other.
It is preferred that test semiconductor components and devices in step 425, wherein, step 425 in time step 420 with 430 it Between perform.Tested by being temporarily switched on the first and second metallic regions.
Alternatively, test can also be performed in step 440 in time between step 430 and 450.
In one embodiment, the 3rd metallic region is configured to the copper covered with several microns thick nickel phosphide layer of chemical deposition Joint or copper shell.Here, solder is PbSn4.By the nitrogen that hydrogen content is 5% to 10% for example at about 350 degrees Celsius Hydrogen gaseous mixture carries out temperature step.The atmosphere comprising formic acid can also alternatively be used.

Claims (8)

1. semiconductor chip (100), including the semiconductor element with the first principal spread direction (x) He the second principal spread direction (y) Device (101), wherein, first principal spread direction (x) and the main extension plane of second principal spread direction (y) formation, its In, the main extension plane is arranged perpendicular to the stacking direction (z) of the semiconductor chip (100), wherein, directly described half Arranged on conductor component (101)：
Welding first metallic region (102),
At least one welding second metallic region (103), and
Dielectric regions (104), wherein,
First metallic region (102) and at least one described second metallic region (103) are by the dielectric regions (104) electricity Separation, wherein, at least one described second metallic region (103) is along first principal spread direction (x) and first metal Region (102) is at a distance of the first spacing (105), it is characterised in that arrange the first solder on first metallic region (102) (107), first solder has the 4th thickness of the three times at least corresponding to first spacing (105) under unwelded state Degree, and the 3rd metallic region (108) is arranged on first solder (107), the 3rd metallic region (108) is along described The spacing (109) of border the 3rd of first principal spread direction (x) and the semiconductor components and devices (101), the 3rd spacing phase When at least five times of the 4th thickness degree in first solder (107) under unwelded state, wherein, first metal Region (102), second metallic region (103), the 3rd metallic region (108) and first solder (107) have The sealed connection of material.
2. semiconductor chip (100) according to claim 1, it is characterised in that at least one described second metallic region (103) surrounded completely by the dielectric regions (104).
3. semiconductor chip (100) according to claim 1 or 2, it is characterised in that first metallic region (102) Surrounded completely by the dielectric regions (104).
4. semiconductor chip (100) according to any one of the preceding claims, it is characterised in that second metal area Border second spacing (106) of the domain (103) along the principal spread direction (x) and the semiconductor components and devices (101).
5. semiconductor chip (100) according to any one of the preceding claims, it is characterised in that first metal area Domain (102) has first layer thickness, and second metallic region (103) has second layer thickness, dielectric regions (104) tool There is third layer thickness, wherein, the first layer thickness and the second layer thickness are more than the third layer thickness.
6. semiconductor chip (100) according to any one of the preceding claims, it is characterised in that the semiconductor element device Part (101) includes pseudo- Schottky diode.
7. the method for manufacturing the semiconductor chip (100) for including semiconductor components and devices (101), with following steps：
Structuring (410) dielectric regions (104) on the semiconductor components and devices (101)；
First metallic region (102) and the second metallic region (103) are applied into (420) and arrive the semiconductor components and devices (101) On so that first metallic region (102) and second metallic region (103) are electrically separated from each other；
First solder (107) is applied into (430) to first metallic region (102), and
(450) described first metallic region (102), second metallic region are connected cohesively together by temperature step material (103), the 3rd metallic region (108) and first solder (107).
8. method (400) according to claim 7, it is characterised in that by being temporarily switched on (425) described first metal area Domain (102) and/or second metallic region (103) test the semiconductor components and devices (101).
CN201611271992.7A 2015-11-09 2016-11-09 Semiconductor chip with solderable front side and method for manufacturing semiconductor chip Active CN107026140B (en)

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DE102015221971.2A DE102015221971A1 (en) 2015-11-09 2015-11-09 Solderable semiconductor chip and method of manufacturing a semiconductor chip

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1430791A (en) * 2000-04-04 2003-07-16 国际整流器公司 Chip scale surface mounted device and its process of manufacture
US20090079006A1 (en) * 2007-09-25 2009-03-26 Kabushiki Kaisha Toshiba Semiconductor apparatus
US20150008575A1 (en) * 2013-07-03 2015-01-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1430791A (en) * 2000-04-04 2003-07-16 国际整流器公司 Chip scale surface mounted device and its process of manufacture
US20090079006A1 (en) * 2007-09-25 2009-03-26 Kabushiki Kaisha Toshiba Semiconductor apparatus
US20150008575A1 (en) * 2013-07-03 2015-01-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof

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