CN107026118A - 半导体器件中的局部互连件的制造方法及半导体器件 - Google Patents

半导体器件中的局部互连件的制造方法及半导体器件 Download PDF

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Publication number
CN107026118A
CN107026118A CN201611099323.6A CN201611099323A CN107026118A CN 107026118 A CN107026118 A CN 107026118A CN 201611099323 A CN201611099323 A CN 201611099323A CN 107026118 A CN107026118 A CN 107026118A
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source
gate electrode
electrode
grid
insulating barrier
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CN107026118B (zh
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赖瑞尧
陈盈燕
叶震亚
杨世海
陈燕铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体器件，包括设置在衬底上的第一栅电极、第一源极/漏极区以及将第一栅电极与第一源极/漏极区连接的局部互连件。局部互连件设置在衬底与第一金属布线层之间，其中，电源供电线设置在第一金属布线层中。局部互连件在平面图中具有钥匙孔形状，并且具有头部、颈部和通过颈部连接至头部的主体部分。头部设置在第一栅电极上方，并且主体部分设置在第一源极/漏极区上方。本发明还提供了半导体器件中的局部互连件的制造方法。

Description

半导体器件中的局部互连件的制造方法及半导体器件
技术领域
本发明的实施例涉及一种用于制造半导体器件的方法，更具体地，涉及用于连接栅电极与源极/漏极区的局部互连件的结构及制造方法。
背景技术
随着具有复杂布局结构的半导体器件的尺寸的减小，已经开发了将源极/漏极区连接至另一源极/漏极区或栅电极的局部互连件。布局互连件是设置在第一金属布线层下面的导电层，并且连接具有相对较短距离的元件。例如，在静态随机存取存储器(SRAM)中，局部互连件可以用于将一个反相器的输出节点(源极/漏极)连接至另一反相器的输入节点(栅极)。需要提供用于具有改进的工艺变化电阻(process variation resistance)的局部互连件的结构和制造工艺。
发明内容
根据本发明的一方面，提供了一种半导体器件，包括：第一栅电极，设置在衬底上；第一源极/漏极区；以及局部互连件，将所述第一栅电极与所述第一源极/漏极区连接，其中：所述局部互连件设置在所述衬底与第一金属布线层之间，其中，电源供电线设置在所述第一金属布线层中，从上往下看时，所述局部互连件具有钥匙孔形状，并且所述局部互连件具有头部、颈部和通过所述颈部连接至所述头部的主体部分，和所述头部设置在所述第一栅电极上方，并且所述主体部分设置在所述第一源极/漏极区上方。
根据本发明的另一方面，提供了一种静态随机存取存储器(SRAM)，包括：第一场效应晶体管(FET)，具有第一栅极、第一源极和第一漏极，所述第一栅极耦合至字线，所述第一漏极耦合至第一位线；第二FET，具有第二栅极、第二源极和第二漏极，所述第二漏极耦合至第一电源供电线；第三FET，具有第三栅极、第三源极和第三漏极，所述第三漏极耦合至第二电源供电线；第四FET，具有第四栅极、第四源极和第四漏极，所述第四栅极耦合至所述字线，并且所述第四漏极耦合至第二位线；第五FET，具有第五栅极、第五源极和第五漏极，所述第五漏极耦合至所述第一电源供电线；第六FET，具有第六栅极、第六源极和第六漏极，所述第六漏极耦合至所述第二电源供电线，其中：所述第二栅极和所述第三栅极共用第一栅电极层，并且所述第五栅极和所述第六栅极共用第二栅电极层，所述第一源极、所述第二源极、所述第三源极和所述第二栅电极层通过第一局部互连件电连接，所述第四源极、所述第五源极、所述第六源极和所述第一栅电极层通过第二局部互连件电连接，所述第一局部互连件和所述第二局部互连件设置在衬底与第一金属布线层之间，其中，所述第一位线和所述第二位线以及所述第二电源供电线设置在所述第一金属布线层中，从上往下看，将所述第二栅电极层与所述第三FET的第三源极连接的所述第一局部互连件的一部分具有钥匙孔形状，并且所述第一局部互连件的一部分具有头部、颈部和通过所述颈部连接至所述头部的主体部分，以及所述头部设置在所述第二栅电极层上方，并且所述主体部分设置在所述第三FET的第三源极上方。
根据本发明的又一方面，提供了一种制造半导体器件的方法，所述方法包括：在衬底上方形成第一栅极结构和第二栅极结构，所述第一栅极结构包括第一栅电极、设置在所述第一栅电极上方的第一覆盖绝缘层、以及设置在所述第一栅电极和所述第一覆盖绝缘层的侧面上的第一侧壁间隔件，所述第二栅极结构包括第二栅电极、设置在所述第二栅电极上方的第二覆盖绝缘层、以及设置在所述第二栅电极和所述第二覆盖绝缘层的侧面上的第二侧壁间隔件；在介于所述第一侧壁间隔件与所述第二侧壁间隔件之间的区域中形成第一源极/漏极区；在所述第一源极/漏极区上方并且在所述第一侧壁间隔件与所述第二侧壁间隔件之间形成第一绝缘层；在形成所述第一绝缘层之后，去除所述第一覆盖绝缘层的一部分，从而形成第一间隔；在所述第一栅极结构和所述第二栅极结构上方并且在所述第一间隔中形成第二绝缘层；去除所述第二绝缘层的一部分和所述第一绝缘层的位于所述第一源极/漏极区上面的部分，并且此外，去除所述第一侧壁间隔件的一部分，从而形成第二间隔，其中通过所述第二间隔暴露所述第一栅电极的上表面的一部分和所述第一源极/漏极区；以及利用导电材料填充所述第二间隔，从而将所述第一栅电极与所述第一源极/漏极区连接。附图说明
当结合附图进行阅读时，从以下详细描述可更好地理解本发明。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A至图1C和图2A至图8C示出了根据本发明的一个实施例的示出半导体器件的顺序制造工艺的示例性示图。
图1D示出了FinFET结构的示例性透视图。
图9示出了根据本发明的一个实施例的半导体器件的示例性截面图。
图10和图11示出根据本发明的一个实施例的SRAM的示例性电路图和布局结构。
图12A是图11中示出的区域A的示例性平面图，并且图12B是根据本发明的一个实施例的图12A的线X3-X3的示例性截面图。
具体实施方式
应当理解，以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面将描述元件和布置的特定实例以简化本发明。当然这些仅是实例并不旨在限定。例如，元件的尺寸不限于所公开的范围或值，但可能依赖于工艺条件和/或器件的期望性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成附加的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简化和清楚，可以以不同的尺寸任意地绘制各个部件。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图所示的一个元件或部件与另一(一些)元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。另外，术语“由...制成”可以意为“包括”或者“由...组成”。
图1A至图1C示出了根据本发明的一个实施例的半导体器件的顺序制造工艺的一个阶段。图1A示出了平面(顶视)图，图1B示出了沿着图1A的线X1-X1的截面图，以及图1C示出了沿着图1A的线X2-X2的截面图。
图1A至图1C示出了形成金属栅极之后的半导体器件的结构。在图1A至图1C中，金属栅极10形成在衬底(未示出)上方，并且覆盖绝缘层20设置在金属栅极10上方。在一些实施例中，金属栅极10的厚度在15nm至50nm的范围内，并且覆盖绝缘层20的厚度在从大约15nm至大约30nm的范围内。侧壁间隔件30提供在金属栅极10和覆盖绝缘层20的侧壁上。在一些实施例中，侧壁间隔件30的位于侧壁间隔件的底部处的膜厚度在大约5nm至大约20nm的范围内。金属栅极10、覆盖绝缘层20和侧壁间隔件30的组合可以一起被称为栅极结构。此外，源极/漏极区50形成为邻近栅极结构，并且介于栅极结构之间的间隔填充有第一层间介电(ILD)层40。
金属栅极10包括一个或多个金属材料层，诸如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlC、TiAlN、TaN、NiSi、CoSi、其他导电材料。栅极介电层(未示出)包括一层或多层金属氧化物，诸如高k金属氧化物。用于高k电介质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物和/或它们的混合物。
在一些实施例中，一个或多个功函数调整层(未示出)夹置在栅极介电层(未示出)与金属栅极10之间。功函数调整层由导电材料制成，诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层或者这些材料中的两种或多种的多层。对于n沟道FET，TaN、TiAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi中的一种或多种用作功函调整层，而对于p沟道FET，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co中的一种或多种用作功函调整层。
覆盖绝缘层20包括一层或多层绝缘材料，诸如包括SiN、SiCN和SiOCN的氮化硅基材料。在该实施例中，SiN用作覆盖绝缘层20。侧壁间隔件30由与覆盖绝缘层20不同的材料制成，并且包括一层或多层绝缘材料，诸如包括SiN、SiON、SiCN和SiOCN的氮化硅基材料。在该实施例中，SiON、SiCN或SiOCN用作侧壁间隔件30。第一ILD层40包括一层或多层绝缘材料，诸如诸如二氧化硅(SiO2)和SiON的氧化硅基材料。在该实施例中，SiO2用作第一ILD层40。
在该实施例中，采用由栅极替换工艺制造的鳍式场效应晶体管(FinFET)。
图1D示出了FinFET结构的示例性透视图。
首先，在衬底300上方制造鳍结构310。鳍结构包括底部区域和作为沟道区315的上部区域。例如，衬底是杂质浓度在大约1×1015cm-3至大约1×1018cm-3的范围内的p型硅衬底。在其他的实施例中，衬底是具有在杂质浓度大约1×1015cm-3至大约1×1018cm-3的范围内的n型硅衬底。可选地，衬底可以包括诸如锗的其他元素半导体和化合物半导体或它们的组合，其中，化合物半导体包括：诸如SiC和SiGe的IV-IV族化合物半导体；诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的III-V族化合物半导体。在一个实施例中，衬底是SOI(绝缘体上硅)衬底的硅层。
形成鳍结构310之后，在鳍结构310上方形成隔离绝缘层320。隔离绝缘层320包括通过LPCVD(低压化学汽相沉积)、等离子体CVD或可流动CVD形成的一层或多层绝缘材料，诸如氧化硅、氮氧化硅或氮化硅。隔离绝缘层可以由以下材料的一层或多层形成：旋涂玻璃(SOG)、SiO、SiON、SiOCN和/或掺氟的硅酸盐玻璃(FSG)。
在鳍结构上方形成隔离绝缘层320之后，执行平坦化操作，以去除隔离绝缘层320的一部分。平坦化操作可以包括化学机械抛光(CMP)和/或回蚀刻工艺。然后，还去除(凹进)隔离绝缘层320，从而暴露鳍结构的上部区域。
伪栅极结构形成在暴露的鳍结构上方。伪栅极结构包括由多晶硅制成的伪栅电极层和伪栅极介电层。包括一个或多个绝缘材料层的侧壁间隔件350还形成在伪栅电极层的侧壁上。在形成伪栅极结构之后，使未被伪栅极结构覆盖的鳍结构310凹进至隔离绝缘层320的上表面之下。然后，通过使用外延生长方法在凹进的鳍结构上方形成源极/漏极区360。源极/漏极区可以包括对沟道区域315施加应力的应变材料。
然后，层间介电层(ILD)370形成在伪栅极结构和源极/漏极区上方。在平坦化操作之后，去除伪栅极结构，从而制造栅极间隔。然后，在栅极间隔中，形成包括栅电极和栅极介电层(诸如高k介电层)的金属栅极结构330。此外，覆盖绝缘层340形成在金属栅极结构330上方，从而获得图1D中示出的FinFET结构。在图1D中，切割金属栅极结构330、覆盖隔离层340、侧壁330和ILD层370的一部分以示出下面的结构。
图1D中的金属栅极结构330、覆盖隔离层340、侧壁330、源极/漏极360和ILD 370分别对应于图1A至图1C的金属栅极10、覆盖绝缘层20、侧壁间隔件30、源极/漏极区50和第一层间介电层(ILD)40。
图2A和图2B示出了根据本发明的一个实施例的半导体器件的顺序制造工艺的多个阶段中的一个阶段。图2A示出了平面(顶视)图，并且图2B示出了沿着图2A的线X1-X1所获得的截面图。
光刻胶层60与位于其下的底部抗反射涂(BARC)层65形成在图1A至图1C的结构上方。如图2B所示，通过使用光刻操作，在光刻胶层60和BARC层65中形成孔图案70。如图2A所示，调整孔70(其要连接至栅极10A)的位置，从而在孔70中暴露覆盖绝缘层20A和一个侧壁间隔件30A的邻近源极/漏极区50的部分。应该注意，图2A中省略了光刻胶层60和BARC层65，并且仅示出了孔70的位置。
图3A和图3B示出了根据本发明的一个实施例的半导体器件的顺序制造工艺的多个阶段中的一个阶段。图3A示出了平面(顶视)图，并且图3B示出了沿着图3A的线X1-X1所获取的截面图。
如图3B所示，通过使用光刻胶层60作为蚀刻掩模，去除覆盖绝缘层20A的上述部分和一个侧壁间隔件30A的上述部分，以制造间隔75，并且然后去除光刻胶层60和BARC层65。
图4A和图4B示出了根据本发明的一个实施例的半导体器件的顺序制造工艺的多个阶段中的一个阶段。图4A示出了平面(顶视)图，并且图4B示出了沿着图4A的线X1-X1所获取的截面图。
如图4B所示，在蚀刻之后，第二ILD层100形成在图3A和图3B的蚀刻的结构上方，并且硬掩模层110、BARC层120和光刻胶层125顺序地形成在第二ILD层100上方。
第二ILD层100包括一层或多层绝缘材料，诸如氧化硅基材料，诸如二氧化硅(SiO2)、SiON或低k介电材料。例如，硬掩模层100由TaN、TiN、Ti或相对于氧化硅具有高蚀刻选择性的其他合适的材料。在一些实施例中，第二ILD层100和硬掩模层110的厚度在大约15nm至大约50nm的范围内。应该注意，图4A中省略了第二ILD层100、硬掩模层110、BARC层120和光刻胶层125，并且示出了金属栅极10的暴露部分75。
图5A和图5B示出了根据本发明的一个实施例的半导体器件的顺序制造工艺的多个阶段中的一个阶段。图5A示出了平面(顶视)图，并且图5B示出了沿着图5A的线X1-X1所获得的截面图。
如图5A和图5B所示，通过使用光刻操作，图案化光刻胶层125和BARC层120，并且通过使用光刻胶层作为蚀刻掩模来图案化硬掩模层110，从而形成第一开口127和第二开口128。随后去除光刻胶层125和BARC层120。应该注意，图5A中省略了第二ILD层100、硬掩模层110和光刻胶层125。
如图5A所示，形成第一开口127，从而使第一开口127的边缘(图5A中的左边缘)设置为与金属栅极的暴露部分75交叉并且位于源极/漏极区50上方。在平面图中，左边缘可以放置为完全覆盖暴露部分75。第一开口127的右边缘未放置在源极/漏极区50上方和源极/漏极区50上面的第一ILD层40上方，并且可以放置在邻近的金属栅极(或覆盖隔离层)或侧壁间隔件上方。在图5A中，形成第二开口128以与两个源极/漏极区和两个栅极结构重叠。
图6A和图6B示出了根据本发明的一个实施例的半导体器件的顺序制造工艺的多个阶段中的一个阶段。图6A示出了平面(顶视)图，并且图6B示出了沿着图6A的线X1-X1所获取的截面图。
如图6B所示，通过使用图案化的硬掩模层110作为蚀刻掩模，去除第二ILD层100和第一ILD层40，从而暴露金属栅极10A的上部和源极/漏极区50的上部。
由于覆盖绝缘层20(和20A)由SiN制成，所以可以通过高选择性执行ILD氧化物蚀刻，并且可以以基本自对准的方式来形成开口140。
如图6B所示，在用于第一ILD层和第二ILD层的氧化物蚀刻过程中，未蚀刻由SiN制成的侧壁间隔件30A，并且保留侧壁间隔件的上部35。
然而，由于侧壁间隔件30A的宽度(厚度)小于大约5nm并且侧壁间隔件30A由SiON、SiCN或SiOCN制成，所以在蚀刻和/或过蚀刻期间去除侧壁间隔件的上部35，而基本不蚀刻覆盖绝缘层20。换句话说，即使侧壁间隔件的材料具有比覆盖绝缘层更低的蚀刻比率，用于ILD的包括离子轰击以导致各向异性蚀刻行为的蚀刻工艺也可以大量消减(chop)或去掉(break)厚度小于5nm的侧壁。
图7A至图7C示出了根据本发明的一个实施例的半导体器件的顺序制造工艺的多个阶段中的一个阶段。图7A示出了平面(顶视)图，图7B示出了沿着图7A的线X1-X1所获得的截面图，以及图7C示出了沿着图7A的线X2-X2所获得的截面图。
图7A至图7C示出了ILD氧化物蚀刻之后所得到的结构。沿着线X1-X1形成开口140，并且沿着线X2-X2形成开口142和144。
图8A至图8C示出了根据本发明的一个实施例的半导体器件的顺序制造工艺的多个阶段中的一个阶段。图8A示出了平面(顶视)图，图8B示出了沿着图8A的线X1-X1所获得的截面图，以及图8C示出了沿着图8A的线X2-X2所获得的截面图。
在形成开口140、142和144之后，导电材料填充在开口中。一个或多个金属材料层(诸如钨、钛、钴和镍、或其硅化物、或其他合适的材料)形成在图7A至图7C的结构上方，并且执行诸如CMP方法的平坦化操作，从而获得图8A至图8C的结构。间隔140被金属层填充，从而形成连接金属栅极10A与源极/漏极区50的局部互连件150。开口142和144也被金属层填充，从而分别形成源极/漏极接触件152和154。这些源极/漏极接触件152和154分别接触源极/漏极区52和54。应该注意，覆盖绝缘层20的上表面、侧壁间隔件30的上表面(顶部)以及局部互连件150和源极/漏极接触件152和154的上表面基本彼此共面，即，位于同一平面上。
如图8A所示，局部互连件150在平面(顶视)图中具有“钥匙孔”形状。“头”部在平面图中具有基本为圆形的形状，并且在一些实施例中，“头”部的直径D在大约10nm至大约30nm的范围内，并且在一些实施例中，“颈”部(连接部分)的宽度Wn在大约5nm至大约10nm的范围内。钥匙孔形状的“主体”部分设置在源极/漏极区50上方。在其他实施例中，“头”部在平面图中具有基本为椭圆的形状，并且椭圆形状的长轴的直径D在大约10nm至大约30nm的范围内。头部设置在金属栅极10(10A)上方，并且颈部设置在侧壁间隔件30(30A)上方。头部与覆盖绝缘层20(20A)接触。
图9示出了根据本发明的一个实施例的半导体器件的示例性截面图。
在形成用于局部互连件150和源极/漏极接触件152和154的金属层之后，在金属层上方形成蚀刻停止层(ESL)160和第三ILD层170。然后，执行图案化操作以形成贯通孔(viahole)。贯通孔填充有一种或多种导电材料，从而形成通孔塞200，并且第一金属布线210形成在通孔塞200上方。可以通过双镶嵌方法形成第一金属布线210和通孔塞200。
在一些实施例中，前述的局部互连件结构应用于SRAM单元。图10和图11示出根据本发明的一个实施例的SRAM的示例性电路图和布局结构。
SRAM单位单元包括具有数据存储(输出)节点D1和互补数据存储(输出)节点D2的两个交叉耦合的反相器。第一反相器的输出耦合至第二反相器的输入，并且第二反相器的输出耦合至第一反相器的输入。SRAM还包括耦合至第一反相器的输出和第二反相器的输入的第一传输门FET器件PG1以及耦合至第二反相器的输出和第一反相器的输入的第二传输门FET器件PG2。第一和第二传输门FET器件的栅极耦合至字线WL，第一传输门FET器件PG1的源极/漏极耦合至第一位线BL，并且第二传输门FET器件PG2的源极/漏极耦合至第二位线BLB，该第二位线BLB是第一位线BL的互补位线。在本发明中，可以交换使用FET器件的源极和漏极。
第一反相器包括第一第一导电类型的FET器件PU1和第一第二导电类型的FET器件PD1。第二反相器包括第二第一导电类型的FET器件PU2第二第二导电类型的FET器件PD2。第一传输门器件PG1和第二传输门器件PG2是第二导电类型的器件。在第一实施例中，第一导电类型是P型并且第二导电类型是N型。当然，可能在另一实施例中，第一导电类型是N型，并且第二导电类型是P型，并且在这种情况下，根据本领域的公知常识来适当地更改SRAM中的剩余的元件。
SRAM还包括第一P型阱PW1、第二P型阱PW2以及N型阱NW。如图10所示，第一传输门器件PG1(N型)和第一N型FET器件PD1设置在第一P型阱PW1内，第二传输门FET器件PG2(N型)和第二N型FET器件PD2设置在第二P型阱PW2内，以及第一P型FET器件PU1和第二P型FET器件PU2设置在N型阱NW内。
图11是根据本发明的第一实施例的SRAM单位单元的示例性布局。在图11中，仅示出了多个下层元件中的一些。
SRAM单位单元可以通过单元边界CELB来限定，并且包括第一至第四鳍结构F1、F2、F3和F4，其中每一个都在Y(列)方向上延伸并且布置在X(行)方向上。四个鳍结构F1、F3、F4和F2以这种顺序布置在X方向上。单元边界CELB具有在X方向上延伸的底边、在X方向上延伸并且与底边相对的顶边、在Y方向上延伸的左边以及在Y方向上延伸并且与左边相对的右边。
SRAM单位单元包括六个晶体管。第一传输门器件PG1是通过第一栅电极GA1和第一鳍结构F1形成的FinFET(PG1)。第一N型FET器件PD1是通过第二栅电极GA2和第一鳍结构F1形成的FinFET。第一P型FET器件PU1是通过第二栅电极GA2和第三鳍结构F3形成的FinFET。第二传输门FET器件PG2是通过第三栅电极GA3和第二鳍结构F2形成的FinFET。第二N型FET器件PD2是通过第四栅电极GA4和第二鳍结构F2形成的FinFET。第二P型FET器件PU2是通过第四栅电极GA4和第四鳍结构F4形成的FinFET。
SRAM单元还包括将FinFET PG1、PD1和PU1的源极与第四栅电极GA4连接的第一局部互连件LC1以及将FinFET PG2、PD2和PU2与第二栅电极GA2连接的第二局部互连件LC2。如图11所示，SRAM单元还包括形成在FinFET的漏极上的源极/漏极接触件SD1、SD2、SD3和SD4。此外，位线BL、互补位线BLB和电源(如，Vdd)供电线VDD设置在局部互连件和源极/漏极接触件上方的第一金属布线层中。
图8A至图9中示出的局部互连结构150可以应用在第一局部互连件LC1中以将第四栅极GA4与FinFET PU1的源极连接，以及应用在第二局部互连件LC2中以将第二栅电极GA2与FinFET PU2的源极连接。
如图11所示，第一局部互连件LC1不仅连接在FinFET PU1的源极与第四栅电极GA4之间，而且连接在FinFET PU1的源极与FinFET PG1和PD1的源极之间。
图12A是图11中示出的区域A的示例性平面图，并且图12B是根据本发明的一个实施例的图12A的线X3-X3的示例性截面图。
如图12A所示，与图8A类似，第一局部互连件LC1的一部分将第四栅极GA4连接至FinFET PU1的源极并且在平面图中具有钥匙孔形状，并且具有头部、颈部以及通过颈部连接至头部的主体部分。头部设置在第四栅极GA4上方，颈部设置在第四栅极GA4的侧壁间隔件上方，并且主体部分设置在FinFET PU1的源极上方。
本文描述的各个实施例或实例提供优于现有技术的若干优点。例如，在本发明中，由于以自对准方式形成局部互连件150，所以可以避免由工艺变化(如，光刻操作中的对准误差)所导致的短路。
应该理解，本文中不必对所有优点进行讨论，没有特定优势是所有实施例或实例都必需的，并且其他实施例或实例可提供不同优点。
根据本发明的一方面，半导体器件包括设置在衬底上的第一栅电极、第一源极/漏极区以及将第一栅电极与第一源极/漏极区连接的局部互连件。局部互连件设置在衬底与第一金属布线层之间，其中，电源供电线设置在第一金属布线层中。局部互连件在平面图中具有钥匙孔形状，并且具有头部、颈部和通过颈部连接至头部的主体部分。头部设置在第一栅电极上方，并且主体部分设置在第一源极/漏极区上方。
在一个实施例中，半导体器件还包括设置在所述第一栅电极的侧面上的第一侧壁间隔件，其中，所述颈部设置在所述第一侧壁间隔件上方。
在一个实施例中，半导体器件还包括设置在所述第一栅电极上方的第一覆盖绝缘层，其中，所述头部与所述第一覆盖绝缘层接触。
在一个实施例中，所述第一覆盖绝缘层包括SiN、SiCN、SiON或SiOCN中的至少一种。
在一个实施例中，所述第一侧壁间隔件由与所述第一覆盖绝缘层不同的材料制成，并且所述第一侧壁间隔件包括SiN、SiCN、SiON或SiOCN中的至少一种。
在一个实施例中，半导体器件还包括：第二栅电极，设置为与所述第一栅电极间隔开；第二覆盖绝缘层，设置在所述第二栅电极上方；第二侧壁间隔件，设置在所述第二栅电极的侧面上，其中，所述第一源极/漏极区与所述第一侧壁间隔件和所述第二侧壁间隔件接触。
在一个实施例中，所述局部互连件由W和Co中的至少一种制成。
在一个实施例中，所述第一覆盖绝缘层的上表面、所述第一侧壁间隔件的上表面和所述局部互连件的上表面彼此齐平。
根据本发明的另一方面，静态随机存取存储器(SRAM)包括第一至第六场效应晶体管(FET)。第一FET具有第一栅极、第一源极和第一漏极。第一栅极耦合至字线，并且第一漏极耦合至第一位线。第二FET具有第二栅极、第二源极和第二漏极。第二漏极耦合至第一电源供电线。第三FET具有第三栅极、第三源极和第三漏极。第三漏极耦合至第二电源供电线。第四FET具有第四栅极、第四源极和第四漏极。第四栅极耦合至字线，并且第四漏极耦合至第二位线。第五FET具有第五栅极、第五源极和第五漏极。第五漏极耦合至第一电源供电线。第六FET具有第六栅极、第六源极和第六漏极。第六漏极耦合至第二电源供电线。第二栅极和第三栅极共用第一栅电极层，并且第五栅极和第六栅极共用第二栅电极层。第一源极、第二源极、第三源极和第二栅电极层通过第一局部互连件进行电连接。第四源极、第五源极、第六源极和第一栅电极层通过第二局部互连件进行电连接。第一和第二局部互连件设置在衬底与第一金属线层之间，其中，第一和第二位线以及第二电源供电线设置在第一金属布线层中。第一局部互连件的一部分将第二栅电极层连接至第三FET的源极，并且在平面图中具有钥匙孔形状，并且具有头部、颈部和通过颈部连接至头部的主体部分。头部设置在第一栅电极层上方，并且主体部分设置在第三FET的源极上方。
在一个实施例中，静态随机存取存储器还包括设置在所述第一栅电极层的侧面上的第一侧壁间隔件，其中，所述颈部设置在所述第一侧壁间隔件上方。
在一个实施例中，静态随机存取存储器还包括设置在所述第一栅电极层上方的第一覆盖绝缘层，其中，所述头部与所述第一覆盖绝缘层接触。
在一个实施例中，所述第一覆盖绝缘层包括SiN、SiCN、SiON或SiOCN中的至少一种。
在一个实施例中，所述第一侧壁间隔件由与所述第一覆盖绝缘层不同的材料制成，并且所述第一侧壁间隔件包括SiN、SiCN、SiON或SiOCN中的至少一种。
在一个实施例中，所述第一局部互连件和所述第一局部互连件由W和Co中的至少一种制成。
在一个实施例中，所述第一覆盖绝缘层的上表面、所述第一侧壁间隔件的上表面和所述第一局部互连件的上表面彼此齐平。
根据本发明的又一方面，在制造半导体器件的方法中，在衬底上方形成第一栅极结构和第二栅极结构。第一栅极结构包括第一栅电极、设置在第一栅电极上方的第一覆盖绝缘层以及设置在第一栅电极和第一覆盖绝缘层的侧面上的第一侧壁间隔件。第二栅极结构包括第二栅电极、设置在第二栅电极上方的第二覆盖绝缘层以及设置在第二栅电极和第二覆盖绝缘层的侧面上的第二侧壁间隔件。第一源极/漏极区形成在介于第一侧壁间隔件与第二侧壁间隔件之间的区域中。第一绝缘层形成在第一源极/漏极区上方并且介于第一侧壁间隔件与第二侧壁间隔件之间。在形成第一绝缘层之后，去除第一覆盖绝缘层的一部分，从而形成第一间隔。第二绝缘层形成在第一和第二栅极结构上方并且位于第一间隔中。去除第二绝缘层的一部分和第一绝缘层的位于第一源极/漏极区上面的部分，并且此外，去除第一侧壁间隔件的一部分，从而形成第二间隔，其中通过第二间隔暴露第一栅电极的上表面的一部分和第一源极/漏极区。利用导电材料填充第二间隔，从而将第一栅电极与第一源极/漏极区连接。
在一个实施例中，所述第一绝缘层和所述第二绝缘层由氧化硅制成；以及所述第一覆盖绝缘层和所述第二覆盖绝缘层包括SiN、SiCN、SiON或SiOCN中的至少一种。
在一个实施例中，所述第一侧壁间隔件和所述第二侧壁间隔件由与所述第一覆盖绝缘层和所述第二覆盖绝缘层不同的材料制成，并且所述第一侧壁间隔件和所述第二侧壁间隔件包括SiN、SiCN、SiON或SiOCN中的至少一种。
在一个实施例中，所述导电材料由W和Co中的至少一种制成。
在一个实施例中，所述利用导电材料填充所述第二间隔包括：形成所述导电材料的毯式层；以及执行平坦化操作，从而使得所述第一覆盖绝缘层的上表面、所述第一侧壁间隔件的上表面和所述填充的导电材料的上表面彼此齐平。
上面论述了若干实施例的部件，以便本领域技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
第一栅电极，设置在衬底上；
第一源极/漏极区；以及
局部互连件，将所述第一栅电极与所述第一源极/漏极区连接，其中：
所述局部互连件设置在所述衬底与第一金属布线层之间，其中，电源供电线设置在所述第一金属布线层中，
从上往下看时，所述局部互连件具有钥匙孔形状，并且所述局部互连件具有头部、颈部和通过所述颈部连接至所述头部的主体部分，和
所述头部设置在所述第一栅电极上方，并且所述主体部分设置在所述第一源极/漏极区上方。
2.根据权利要求1所述的半导体器件，还包括设置在所述第一栅电极的侧面上的第一侧壁间隔件，
其中，所述颈部设置在所述第一侧壁间隔件上方。
3.根据权利要求1所述的半导体器件，还包括设置在所述第一栅电极上方的第一覆盖绝缘层，
其中，所述头部与所述第一覆盖绝缘层接触。
4.根据权利要求3所述的半导体器件，其中，所述第一覆盖绝缘层包括SiN、SiCN、SiON或SiOCN中的至少一种。
5.根据权利要求4所述的半导体器件，其中：
所述第一侧壁间隔件由与所述第一覆盖绝缘层不同的材料制成，并且所述第一侧壁间隔件包括SiN、SiCN、SiON或SiOCN中的至少一种。
6.根据权利要求3所述的半导体器件，还包括：
第二栅电极，设置为与所述第一栅电极间隔开；
第二覆盖绝缘层，设置在所述第二栅电极上方；
第二侧壁间隔件，设置在所述第二栅电极的侧面上，
其中，所述第一源极/漏极区与所述第一侧壁间隔件和所述第二侧壁间隔件接触。
7.根据权利要求1所述的半导体器件，其中，所述局部互连件由W和Co中的至少一种制成。
8.根据权利要求1所述的半导体器件，其中，所述第一覆盖绝缘层的上表面、所述第一侧壁间隔件的上表面和所述局部互连件的上表面彼此齐平。
9.一种静态随机存取存储器(SRAM)，包括：
第一场效应晶体管(FET)，具有第一栅极、第一源极和第一漏极，所述第一栅极耦合至字线，所述第一漏极耦合至第一位线；
第二FET，具有第二栅极、第二源极和第二漏极，所述第二漏极耦合至第一电源供电线；
第三FET，具有第三栅极、第三源极和第三漏极，所述第三漏极耦合至第二电源供电线；
第四FET，具有第四栅极、第四源极和第四漏极，所述第四栅极耦合至所述字线，并且所述第四漏极耦合至第二位线；
第五FET，具有第五栅极、第五源极和第五漏极，所述第五漏极耦合至所述第一电源供电线；
第六FET，具有第六栅极、第六源极和第六漏极，所述第六漏极耦合至所述第二电源供电线，其中：
所述第二栅极和所述第三栅极共用第一栅电极层，并且所述第五栅极和所述第六栅极共用第二栅电极层，
所述第一源极、所述第二源极、所述第三源极和所述第二栅电极层通过第一局部互连件电连接，
所述第四源极、所述第五源极、所述第六源极和所述第一栅电极层通过第二局部互连件电连接，
所述第一局部互连件和所述第二局部互连件设置在衬底与第一金属布线层之间，其中，所述第一位线和所述第二位线以及所述第二电源供电线设置在所述第一金属布线层中，
从上往下看，将所述第二栅电极层与所述第三FET的第三源极连接的所述第一局部互连件的一部分具有钥匙孔形状，并且所述第一局部互连件的一部分具有头部、颈部和通过所述颈部连接至所述头部的主体部分，以及
所述头部设置在所述第二栅电极层上方，并且所述主体部分设置在所述第三FET的第三源极上方。
10.一种制造半导体器件的方法，所述方法包括：
在衬底上方形成第一栅极结构和第二栅极结构，所述第一栅极结构包括第一栅电极、设置在所述第一栅电极上方的第一覆盖绝缘层、以及设置在所述第一栅电极和所述第一覆盖绝缘层的侧面上的第一侧壁间隔件，所述第二栅极结构包括第二栅电极、设置在所述第二栅电极上方的第二覆盖绝缘层、以及设置在所述第二栅电极和所述第二覆盖绝缘层的侧面上的第二侧壁间隔件；
在介于所述第一侧壁间隔件与所述第二侧壁间隔件之间的区域中形成第一源极/漏极区；
在所述第一源极/漏极区上方并且在所述第一侧壁间隔件与所述第二侧壁间隔件之间形成第一绝缘层；
在形成所述第一绝缘层之后，去除所述第一覆盖绝缘层的一部分，从而形成第一间隔；
在所述第一栅极结构和所述第二栅极结构上方并且在所述第一间隔中形成第二绝缘层；
去除所述第二绝缘层的一部分和所述第一绝缘层的位于所述第一源极/漏极区上面的部分，并且此外，去除所述第一侧壁间隔件的一部分，从而形成第二间隔，其中通过所述第二间隔暴露所述第一栅电极的上表面的一部分和所述第一源极/漏极区；以及
利用导电材料填充所述第二间隔，从而将所述第一栅电极与所述第一源极/漏极区连接。
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