CN107025132B - Interrupt configuration method and device - Google Patents
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- CN107025132B CN107025132B CN201610072882.1A CN201610072882A CN107025132B CN 107025132 B CN107025132 B CN 107025132B CN 201610072882 A CN201610072882 A CN 201610072882A CN 107025132 B CN107025132 B CN 107025132B
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G06F9/48—Program initiating; Program switching, e.g. by interrupt
Abstract
The invention provides an interrupt configuration method and an interrupt configuration device, wherein the method comprises the following steps: acquiring an interrupt configuration program in a Basic Input Output System (BIOS), wherein the interrupt configuration program comprises mapping relations between different interrupt sources and different interrupt numbers; initializing an interrupt source in the computer system according to the interrupt configuration program, and distributing an interrupt number for the interrupt source in the computer system. According to the interrupt configuration method and device provided by the invention, the interrupt configuration program originally arranged in the operating system is arranged in the BIOS, so that the interrupt configuration program without universality is not arranged in the operating system, and only the programs and functions adapted to all computer systems are included, so that any computer system can use the operating system, and the compatibility of the operating system is improved.
Description
Technical Field
The present invention relates to computer technologies, and in particular, to a method and an apparatus for configuring an interrupt.
Background
The interrupt refers to that in a computer system, after an external device sends an interrupt request to a Central Processing Unit (CPU), the CPU temporarily interrupts the execution of a current program and then executes an interrupt handler process corresponding to the external device. Because the CPU can perform other work before the CPU does not receive the interrupt request, the work efficiency of the CPU can be improved by adopting the interrupt mode.
In the prior art, when the peripheral sends an interrupt request to the CPU, the interrupt request carries its own interrupt number, and when the interrupt number is initially configured in the computer system, the CPU writes the interrupt number into the peripheral through an interrupt configuration program preset in the operating system.
However, since the interrupt numbers corresponding to the peripherals are related to the connection mode between the peripherals and the motherboard of the computer system, that is, when the connection mode between the same peripheral and the motherboard of the computer system is different, the corresponding interrupt numbers are also different, that is, the interrupt configuration programs preset in the operating system are different, the operating system cannot adapt to peripherals having different connection modes with the motherboard of the computer, resulting in poor compatibility of the operating system.
Disclosure of Invention
The invention provides an interrupt configuration method and device, which are used for solving the problem of poor operating system compatibility caused by the fact that an operating system cannot be adapted to peripherals with different connection modes with a mainboard of a computer when the operating system is used for carrying out interrupt configuration on an interrupt source of a computer system in the prior art.
A first aspect of the present invention provides an interrupt configuration method, including:
acquiring an interrupt configuration program in a Basic Input Output System (BIOS), wherein the interrupt configuration program comprises mapping relations between different interrupt sources and different interrupt numbers;
initializing an interrupt source in the computer system according to the interrupt configuration program, and distributing an interrupt number for the interrupt source in the computer system.
As described above, interrupt sources in the computer system include a first interrupt source, a second interrupt source connected to an interrupt controller internal to a CPU, a third interrupt source connected to a bridge chip, the bridge chip connected to the interrupt controller through an interrupt vector register internal to the CPU; mapping relations between different interrupt sources and different interrupt numbers in the interrupt configuration program include a first mapping relation between the first interrupt source and a first interrupt number segment, a second mapping relation between the second interrupt source and a second interrupt number segment, and a third mapping relation between the third interrupt source and a third interrupt number segment;
the initializing an interrupt source in a computer system according to the interrupt configuration program and allocating an interrupt number to the interrupt source in the computer system specifically includes:
writing an interrupt number corresponding to the first interrupt source into the first interrupt source according to the first mapping relation;
writing the interrupt number corresponding to the second interrupt source into the second interrupt source according to the second mapping relation;
and writing the interrupt number corresponding to the third interrupt source into the third interrupt source according to the third mapping relation.
As described above, the first break number segments are 48-63, the second break number segments are 16-47, and the third break number segments are 0-15.
As described above, before initializing an interrupt source in a computer system according to the interrupt configuration program, the method further comprises:
and scanning pins of the interrupt controller and the bridge chip, and determining the connection relationship between the interrupt controller and the second interrupt source and the connection relationship between the bridge chip and the third interrupt source.
As described above, the method further comprises:
enabling an interrupt bit of a pin of the interrupt vector register connected to the bridge.
A second aspect of the present invention provides an interrupt configuration apparatus, including:
the system comprises an acquisition module, a processing module and a control module, wherein the acquisition module is used for acquiring an interrupt configuration program in a Basic Input Output System (BIOS), and the interrupt configuration program comprises mapping relations between different interrupt sources and different interrupt numbers;
and the distribution module is used for initializing the interrupt source in the computer system according to the interrupt configuration program acquired by the acquisition module and distributing an interrupt number to the interrupt source in the computer system.
As described above, interrupt sources in the computer system include a first interrupt source, a second interrupt source connected to an interrupt controller internal to a CPU, a third interrupt source connected to a bridge chip, the bridge chip connected to the interrupt controller through an interrupt vector register internal to the CPU; mapping relations between different interrupt sources and different interrupt numbers in the interrupt configuration program include a first mapping relation between the first interrupt source and a first interrupt number segment, a second mapping relation between the second interrupt source and a second interrupt number segment, and a third mapping relation between the third interrupt source and a third interrupt number segment;
the allocation module is specifically configured to write an interrupt number corresponding to the first interrupt source into the first interrupt source according to the first mapping relationship; writing the interrupt number corresponding to the second interrupt source into the second interrupt source according to the second mapping relation; and writing the interrupt number corresponding to the third interrupt source into the third interrupt source according to the third mapping relation.
As described above, the first break number segments are 48-63, the second break number segments are 16-47, and the third break number segments are 0-15.
As described above, the apparatus further includes:
a determining module, configured to scan pins of the interrupt controller and the bridge chip before the allocating module initializes the interrupt sources in the computer system according to the interrupt configuration program, and determine a connection relationship between the interrupt controller and the second interrupt source and a connection relationship between the bridge chip and the third interrupt source.
As described above, the apparatus further includes:
and the processing module is used for enabling the interrupt bit of the pin connected with the bridge chip in the interrupt vector register.
The interrupt configuration method and the interrupt configuration device provided by the invention have the advantages that the interrupt configuration program originally arranged in the operating system is arranged in the BIOS, so that the computer system can distribute the interrupt number to the interrupt source in the computer system through the interrupt configuration program in the BIOS, and the interrupt configuration is not required to be carried out through the operating system, namely the operating system can not comprise the interrupt configuration program without universality and only comprises the programs and functions adapted to all computer systems, so that any computer system can use the operating system, and the compatibility of the operating system is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flowchart of a first embodiment of an interrupt configuration method according to the present invention;
FIG. 2 is a schematic diagram of a computer system according to the present invention;
FIG. 3 is a schematic structural diagram of a first interrupt configuration apparatus according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a second interrupt configuration apparatus according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides an interrupt configuration method and device, aiming at solving the problem of poor operating system compatibility caused by the fact that an operating system cannot be adapted to peripherals with different connection modes with a mainboard of a computer when the operating system is used for carrying out interrupt configuration on an interrupt source of a computer system in the prior art.
To facilitate an understanding of the present invention, a brief description of a computer system is provided below. The hardware of the computer system may include: the system comprises a CPU, a bridge chip and a plurality of interrupt sources, wherein the bridge chip is connected with an interrupt controller integrated in the CPU through an interrupt vector register in the CPU, and the CPU, the interrupt controller and the bridge chip are respectively connected with different interrupt sources. The interrupt source may be an interrupt source located outside the CPU, such as a peripheral device, or an interrupt source located inside the CPU, such as a timer.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 1 is a flowchart of a first embodiment of an interrupt configuration method provided by the present invention, where an execution main body of the present embodiment may be a computer System having a Microprocessor Without internal interlocking pipeline stages (MIPS), and the present embodiment relates to a specific process of allocating an interrupt number to an interrupt source in the computer System by the computer System according to an interrupt configuration program preset in a Basic Input Output System (BIOS).
Before the embodiment is implemented, the following preparation work is required: according to a hardware schematic diagram of a computer system, determining the electrical connection relation among a CPU, an interrupt controller, a bridge chip and different interrupt sources in the computer system, further determining the mapping relation between each interrupt source and an interrupt number according to the connection relation, and writing the mapping relation between each interrupt source and the interrupt number into an interrupt configuration program in a BIOS of the computer system.
As shown in fig. 1, the method may include:
s101, acquiring an interrupt configuration program in the BIOS, wherein the interrupt configuration program comprises mapping relations between different interrupt sources and different interrupt numbers.
Specifically, when the computer system receives an interrupt configuration request input by a user, or the computer system receives an interrupt configuration request sent by another device, or the computer system actively initiates interrupt configuration, the computer system may read an interrupt configuration program in the BIOS to perform interrupt configuration on an interrupt source in the computer system, where the interrupt configuration program includes a mapping relationship between an interrupt source adapted to the computer system and an interrupt number.
S102, initializing an interrupt source in the computer system according to the interrupt configuration program, and distributing an interrupt number for the interrupt source in the computer system.
Specifically, the computer system may write an interrupt number corresponding to each interrupt source in the computer system into an interrupt line register of each interrupt source according to the mapping relationship, so that in the running process of the computer system, the interrupt source may send an interrupt request to a CPU of the computer system by using the interrupt number in the interrupt line register, so that the CPU may determine which interrupt source sends the interrupt request according to the interrupt number, and call a correct interrupt handler to process the interrupt request of the interrupt source.
Further, the computer system may further configure an interrupt route of the computer system according to the interrupt configuration program, that is, a route between the interrupt controller and the state register of the CPU core, a route between the interrupt controller and the interrupt vector register, and a route between the interrupt vector register and the bridge chip, so that the interrupt source connected to the bridge chip and the interrupt source connected to the interrupt controller may send an interrupt request to the CPU through the interrupt route, where the computer system configures the interrupt route of the computer system according to the interrupt configuration program, which may specifically refer to the prior art, and this embodiment is not described herein again.
In the prior art, an interrupt configuration program is preset in an operating system, where the interrupt configuration program includes an interrupt number mapping relationship, and the interrupt number mapping relationship covers a corresponding relationship between an interrupt source and an interrupt number adapted to the computer system. When the computer system needs to perform interrupt configuration, the computer system reads an interrupt configuration program in the operating system so as to write an interrupt number corresponding to each interrupt source for each interrupt source according to the interrupt number mapping relation in the interrupt configuration program. However, when the connection mode between the same interrupt source and the computer motherboard (i.e., the CPU, the interrupt controller, or the bridge) is changed, the interrupt number corresponding to the interrupt source is also changed, and therefore, when the same interrupt source corresponds to different interrupt numbers, the mapping relationship between the interrupt numbers included in the interrupt configuration program is different, which causes the different interrupt configuration programs preset in the operating system, that is, the interrupt configuration program preset in the operating system does not have generality, that is, the operating system does not have commonality, so that any two computer systems having different connection modes with the same interrupt source cannot use the same operating system to perform interrupt configuration for the interrupt source, which results in poor compatibility of the operating system.
In this embodiment, the interrupt configuration program is not preset in the operating system, but preset in the BIOS of the computer system, so that, for any two computer systems having different connection modes with the same interrupt source, only the interrupt configuration program adapted to the computer system needs to be set in the BIOS of each computer system, that is, the BIOS adapted to the computer system is configured for each computer system, thus, for any two computer systems having different connection modes with the same interrupt source, only the chip adapted to the BIOS of the computer system needs to be simply replaced for the two computer systems, and the interrupt configuration program adapted to the computer system does not need to be set in the operating system The other work of the computer system uses different BIOS to execute the interrupt configuration, that is, the operating system can be adapted to any computer system with different connection modes with the same interrupt source, thereby improving the compatibility of the operating system.
The interrupt configuration method provided by the invention enables the computer system to distribute the interrupt number for the interrupt source in the computer system through the interrupt configuration program in the BIOS by setting the interrupt configuration program originally arranged in the operating system in the BIOS, and does not need to perform interrupt configuration through the operating system, namely the operating system can not include the interrupt configuration program without universality and only includes the programs and functions adapted to all the computer systems, so that any computer system can use the operating system, and the compatibility of the operating system is improved.
Fig. 2 is a schematic structural diagram of a computer system provided by the present invention, and as shown in fig. 2, the interrupt sources in the computer system may include a first interrupt source, a second interrupt source connected to an interrupt controller inside a CPU, and a third interrupt source connected to a bridge chip, where the bridge chip is connected to the interrupt controller through an interrupt vector register inside the CPU; the mapping relationship between different interrupt sources and different interrupt numbers in the interrupt configuration program includes a first mapping relationship between a first interrupt source and a first interrupt number segment, a second mapping relationship between a second interrupt source and a second interrupt number segment, and a third mapping relationship between a third interrupt source and a third interrupt number segment;
initializing an interrupt source in the computer system according to the interrupt configuration program, and assigning an interrupt number to the interrupt source in the computer system, specifically including:
writing an interrupt number corresponding to the first interrupt source into the first interrupt source according to the first mapping relation;
writing an interrupt number corresponding to the second interrupt source into the second interrupt source according to the second mapping relation;
and writing the interrupt number corresponding to the third interrupt source into the third interrupt source according to the third mapping relation.
Specifically, in this embodiment, according to connection relationships between different interrupt sources and different devices in the computer system, the interrupt sources in the computer system are divided into a first interrupt source (e.g., a timer inside the CPU, etc.), a second interrupt source (e.g., a memory controller, a low pin count bus interface, a peripheral device, etc.), and a third interrupt source (e.g., a peripheral device), where the second interrupt source is connected to an interrupt controller inside the CPU, and the third interrupt source is connected to a bridge chip, where a first interrupt number segment corresponding to the first interrupt source, a second interrupt number segment corresponding to the second interrupt source, and a third interrupt number segment corresponding to the third interrupt source may respectively correspond to one or more different interrupt numbers, and values of the first interrupt number segment, the second interrupt number segment, and the third interrupt number segment may be specifically determined according to needs of a user during specific implementation.
In an implementation manner of this embodiment, the first interrupt number segments are 48 to 63, the second interrupt number segments are 16 to 47, and the third interrupt number segments are 0 to 15, then a first mapping relationship between the first interrupt source and the first interrupt number segment may be, for example, as shown in table 1, a second mapping relationship between the second interrupt source and the second interrupt number segment may be, for example, as shown in table 2, and a third mapping relationship between the third interrupt source and the third interrupt number segment may be, for example, as shown in table 3.
TABLE 1
TABLE 2
TABLE 3
After the computer system obtains the mapping relationship between the interrupt sources and the interrupt numbers shown in the above tables 1, 2, and 3 according to the interrupt configuration program, the corresponding interrupt number can be written into each interrupt source according to the mapping relationship. It should be noted that, the first mapping relationship between the first interrupt source and the first interrupt number segment shown in table 1, the second mapping relationship between the second interrupt source and the second interrupt number segment shown in table 2, and the third mapping relationship between the third interrupt source and the third interrupt number segment shown in table 3 only represent the interrupt number corresponding to each interrupt source of the interrupt source and the connection relationship among the CPU, the interrupt controller, and the bridge, and those skilled in the art can understand that the interrupt sources included in the computer system are not limited to the interrupt sources shown in tables 1, 2, and 3, and the connection relationship among the interrupt sources, the CPU, the interrupt controller, and the bridge is not limited to the connection relationship among tables 1, 2, and 3, and therefore, the interrupt numbers corresponding to the interrupt sources are not limited to the correspondence relationships shown in tables 1, 2, and 3, and may specifically be determined according to the connection relationship among each interrupt source, the CPU, the interrupt sources, the bridge, and the corresponding to the interrupt sources, The connection mode of the interrupt controller and the bridge is to fine-tune the interrupt number corresponding to the interrupt source in table 1, table 2 and table 3.
Optionally, in another implementation manner of the present invention, before the step S102, the method may further include: and scanning pins of the interrupt controller and the bridge chip, and determining the connection relationship between the interrupt controller and the second interrupt source and the connection relationship between the bridge chip and the third interrupt source. In this way, before the computer system assigns an interrupt number to the interrupt source of the computer system, it may be determined whether the interrupt controller is actually electrically connected to each second interrupt source in the second mapping relationship and whether the bridge chip is actually electrically connected to each third interrupt source in the third mapping relationship by scanning the pins of the interrupt controller and the pins of the bridge chip. When determining that the connection relationship exists between the interrupt controller and a certain second interrupt source in the second mapping relationship, the computer system writes the corresponding interrupt number into the second interrupt source according to the second mapping relationship, and when determining that the connection relationship exists between the bridge chip and a certain third interrupt source in the third mapping relationship, the computer system writes the corresponding interrupt number into the third interrupt source according to the third mapping relationship; when the fact that the connection relation between the interrupt controller and a certain second interrupt source in the second mapping relation does not exist is determined, the computer system does not need to write the interrupt number into the second interrupt source any more, and when the fact that the connection relation between the bridge chip and a certain third interrupt source in the third mapping relation does not exist, the computer system does not need to write the interrupt number into the third interrupt source any more, and the efficiency of the computer system in executing interrupt configuration is improved.
Optionally, after the step S102, the method may further include: enabling the interrupt bit of the pin connected with the bridge chip in the interrupt vector register, so that when the bridge chip sends an interrupt request of a third interrupt source to the interrupt controller through the route with the interrupt vector register, the interrupt controller can correctly receive the interrupt request and forwards the interrupt request to the CPU for processing, thereby improving the success rate of sending the interrupt request by the third interrupt source.
The interrupt configuration method provided by the invention enables the computer system to distribute the interrupt number for the interrupt source in the computer system through the interrupt configuration program in the BIOS by setting the interrupt configuration program originally arranged in the operating system in the BIOS, and does not need to perform interrupt configuration through the operating system, namely the operating system can not include the interrupt configuration program without universality and only includes the programs and functions adapted to all the computer systems, so that any computer system can use the operating system, and the compatibility of the operating system is improved.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Fig. 3 is a schematic structural diagram of a first embodiment of an interrupt configuration device provided in the present invention, and as shown in fig. 3, the interrupt configuration device may include: an acquisition module 11 and a distribution module 12; wherein the content of the first and second substances,
an obtaining module 11, configured to obtain an interrupt configuration program in a BIOS, where the interrupt configuration program may include mapping relationships between different interrupt sources and different interrupt numbers;
the allocating module 12 may be configured to initialize an interrupt source in the computer system according to the interrupt configuration program acquired by the acquiring module 11, and allocate an interrupt number to the interrupt source in the computer system.
The interrupt configuration device provided by the present invention can implement the above method embodiments, and the implementation principle and technical effect are similar, which are not described herein again.
Further, on the basis of the above embodiment, the interrupt sources in the computer system may include a first interrupt source, a second interrupt source connected to an interrupt controller inside the CPU, and a third interrupt source connected to a bridge chip, where the bridge chip is connected to the interrupt controller through an interrupt vector register inside the CPU; the mapping relationship between the different interrupt sources and the different interrupt numbers in the interrupt configuration program may include a first mapping relationship between the first interrupt source and the first interrupt number segment, a second mapping relationship between the second interrupt source and the second interrupt number segment, and a third mapping relationship between the third interrupt source and the third interrupt number segment;
the allocating module 12 may be specifically configured to write an interrupt number corresponding to the first interrupt source into the first interrupt source according to the first mapping relationship; writing an interrupt number corresponding to the second interrupt source into the second interrupt source according to the second mapping relation; and writing the interrupt number corresponding to the third interrupt source into the third interrupt source according to the third mapping relation.
In one implementation of the present invention, the first break number segment may be 48 to 63, the second break number segment may be 16 to 47, and the third break number segment may be 0 to 15.
The interrupt configuration device provided by the present invention can implement the above method embodiments, and the implementation principle and technical effect are similar, which are not described herein again.
Fig. 4 is a schematic structural diagram of a second embodiment of the interrupt configuration apparatus provided in the present invention, and as shown in fig. 4, the interrupt configuration apparatus may further include: the determining module 13 may be configured to scan pins of the interrupt controller and the bridge chip, and determine a connection relationship between the interrupt controller and the second interrupt source and a connection relationship between the bridge chip and the third interrupt source before the allocating module 12 initializes the interrupt sources in the computer system according to the interrupt configuration program.
With continued reference to fig. 4, optionally, the interrupt configuration apparatus may further include: the processing module 14 may be configured to enable an interrupt bit of a pin of the interrupt vector register coupled to the bridge.
The interrupt configuration device provided by the present invention can implement the above method embodiments, and the implementation principle and technical effect are similar, which are not described herein again.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. An interrupt configuration method, applied to a microprocessor MIPS without internal interlocking pipeline stages, includes:
acquiring an interrupt configuration program in a Basic Input Output System (BIOS), wherein the interrupt configuration program comprises mapping relations between different interrupt sources and different interrupt numbers;
initializing an interrupt source in a computer system according to the interrupt configuration program, and distributing an interrupt number for the interrupt source in the computer system;
the interrupt sources in the computer system comprise a first interrupt source, a second interrupt source connected with an interrupt controller inside a CPU, and a third interrupt source connected with a bridge chip, wherein the bridge chip is connected with the interrupt controller through an interrupt vector register inside the CPU; mapping relations between different interrupt sources and different interrupt numbers in the interrupt configuration program include a first mapping relation between the first interrupt source and a first interrupt number segment, a second mapping relation between the second interrupt source and a second interrupt number segment, and a third mapping relation between the third interrupt source and a third interrupt number segment;
the initializing an interrupt source in a computer system according to the interrupt configuration program and allocating an interrupt number to the interrupt source in the computer system specifically includes:
writing an interrupt number corresponding to the first interrupt source into the first interrupt source according to the first mapping relation;
writing the interrupt number corresponding to the second interrupt source into the second interrupt source according to the second mapping relation;
and writing the interrupt number corresponding to the third interrupt source into the third interrupt source according to the third mapping relation.
2. The method of claim 1, wherein the first break number segments are 48-63, the second break number segments are 16-47, and the third break number segments are 0-15.
3. The method of claim 1 or 2, wherein prior to initializing an interrupt source in a computer system according to the interrupt configuration program, the method further comprises:
and scanning pins of the interrupt controller and the bridge chip, and determining the connection relationship between the interrupt controller and the second interrupt source and the connection relationship between the bridge chip and the third interrupt source.
4. The method according to claim 1 or 2, characterized in that the method further comprises:
enabling an interrupt bit of a pin of the interrupt vector register connected to the bridge.
5. An interrupt configuration device applied to MIPS (mobile industry processor) is characterized by comprising the following components:
the system comprises an acquisition module, a processing module and a control module, wherein the acquisition module is used for acquiring an interrupt configuration program in a Basic Input Output System (BIOS), and the interrupt configuration program comprises mapping relations between different interrupt sources and different interrupt numbers;
the distribution module is used for initializing the interrupt source in the computer system according to the interrupt configuration program acquired by the acquisition module and distributing an interrupt number to the interrupt source in the computer system;
the interrupt sources in the computer system comprise a first interrupt source, a second interrupt source connected with an interrupt controller inside a CPU, and a third interrupt source connected with a bridge chip, wherein the bridge chip is connected with the interrupt controller through an interrupt vector register inside the CPU; mapping relations between different interrupt sources and different interrupt numbers in the interrupt configuration program include a first mapping relation between the first interrupt source and a first interrupt number segment, a second mapping relation between the second interrupt source and a second interrupt number segment, and a third mapping relation between the third interrupt source and a third interrupt number segment;
the allocation module is specifically configured to write an interrupt number corresponding to the first interrupt source into the first interrupt source according to the first mapping relationship; writing the interrupt number corresponding to the second interrupt source into the second interrupt source according to the second mapping relation; and writing the interrupt number corresponding to the third interrupt source into the third interrupt source according to the third mapping relation.
6. The apparatus of claim 5, wherein the first break number segments are 48-63, the second break number segments are 16-47, and the third break number segments are 0-15.
7. The apparatus of claim 5 or 6, further comprising:
a determining module, configured to scan pins of the interrupt controller and the bridge chip before the allocating module initializes the interrupt sources in the computer system according to the interrupt configuration program, and determine a connection relationship between the interrupt controller and the second interrupt source and a connection relationship between the bridge chip and the third interrupt source.
8. The apparatus of claim 5 or 6, further comprising:
and the processing module is used for enabling the interrupt bit of the pin connected with the bridge chip in the interrupt vector register.
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