WO2018040494A1 - Method and device for extending processor instruction set - Google Patents

Abstract

A method and device for extending a processor instruction set, relating to the technical field of communications. The method and device can improve the processing speed of a processor without modifying a processor core. The method comprises: a monitoring module identifies instructions by means of an on-chip bus and stores an extended instruction among the instructions to a local memory (102); after a processor core loads the extended instruction from the memory by means of the on-chip bus, the processor core decodes the extended instruction to generate an undefined instruction abnormality (103); after the processor core finishes executing the current instruction, the processor core executes an abnormality processing procedure (104), and suspends execution of an instruction following the extended instruction; the monitoring module triggers an execution module corresponding to the extended instruction to execute the extended instruction (105); the monitoring module controls the processor core to exit from the abnormality processing procedure (108), so that the processor core continues executing the instruction following the extended instruction (109). The method and the device are applicable to the execution process of an extended instruction.

Description

Method and device for expanding processor instruction set

The present application claims priority to Chinese Patent Application No. 201610777425.2, the entire disclosure of which is incorporated herein by reference. In this application.

Technical field

The present invention relates to the field of communications technologies, and in particular, to a method and apparatus for extending a processor instruction set.

Background technique

With the development of communication technology, in order to improve the processing capability of the communication system, it is often necessary to use a hardware acceleration module to process complex services, such as floating point operations, encryption and decryption, compression and decompression operations. At present, the following methods can be used to implement the processing of complex services:

A coprocessor is used to execute a dedicated instruction such as a floating point instruction, that is, the processor needs to send a dedicated instruction to the coprocessor for execution. The advantage of this type of processing is that it is simple to program and can directly use coprocessor instructions. The disadvantage is that the processor must support this special instruction. However, not all processor cores support this function, for example, the manufacturer uses third-party processing. The kernel can't support the coprocessor's operation by designing its own processor.

Alternatively, the hardware acceleration module is used as a peripheral of the processor, and the processor sends the data to the acceleration module through PCIe (English: Peripheral Component Interconnect express, Chinese: PCI fast channel) interface, and the acceleration module processes the processing result. The device is stored in memory, and when the processor needs to access the processing result, the processing result is read from the memory. This processing method is more flexible in the implementation process because the acceleration module is decoupled from the processor, but there is frequent data interaction between the processor and the acceleration module, which reduces the processing performance of the service.

Therefore, there is still a need for an implementation method that combines the advantages of the above two technologies to improve the processing power of the service and simplify the programming.

Summary of the invention

The present invention provides a method and apparatus for extending a processor instruction set, which can improve the processing speed of the processor without modifying the processor core.

In order to achieve the above object, the present invention adopts the following technical solutions:

In one aspect, the invention provides a method of extending a processor instruction set. The method is for a chip comprising a processor core, a monitoring module and at least one execution module for executing an extended instruction, the monitoring module and at least one execution module for executing the extended instruction being implemented by programmable logic. The method for extending the processor instruction set includes: the monitoring module identifies an instruction by an on-chip bus, the instruction is an instruction that the processor core loads from the memory through the on-chip bus; the monitoring module saves the extended instruction in the instruction to the local memory; The on-chip bus is loaded from memory into the extended instruction Thereafter, the processor core decodes the extended instruction to generate an undefined instruction exception, which is an extended instruction that has been stored in the local memory; after the processor core executes the current instruction, the processor core executes an exception handler, the exception The processing program is a program triggered by an undefined instruction exception; when the processor core executes the exception processing program, the processor core suspends executing the instruction after the extended instruction, and the execution module corresponding to the extended instruction is triggered by the monitoring module to execute the extended instruction; the monitoring module controls The processor core exits the exception handler so that the processor core continues to execute instructions following the extended instruction. It can be seen that although the processor core cannot execute the extended instruction, since each extended instruction has its corresponding execution module to execute the extended instruction, even if the processor core does not have the ability to execute the extended instruction, The execution module can still be successfully executed by the execution module, and after executing the extended instruction, the processor core is triggered to continue executing the instruction after the extended instruction. In this way, it is equivalent to expanding the instruction set of the processor core, thus improving the processing power of the processor, thereby improving the processing speed of the processor.

In a possible design, it is considered that each execution module can execute at least one extended instruction, and each extended instruction corresponds to one instruction address. Therefore, in order to ensure accurate determination of the extended instruction, the processor core triggers the extension instruction corresponding by the monitoring module. The process of executing the extended instruction by the execution module may be specifically implemented as: the processor core sends the content of the program counter when the processor core generates an undefined instruction exception, and the content of the program counter is the next instruction of the extended instruction. The instruction address determines the instruction address of the extended instruction according to the instruction address of the next instruction; the monitoring module notifies the execution module corresponding to the extended instruction to execute the extended instruction corresponding to the instruction address. It can be seen that the present invention can accurately calculate the instruction address of the extended instruction according to the instruction address of the next instruction recorded in the obtained program counter, thereby ensuring that the monitoring module can timely notify the execution module that can be used to execute the extended instruction. Execute the extension instruction.

In a possible design, before the monitoring module notifies the execution module corresponding to the extended instruction to execute the extended instruction corresponding to the instruction address, the monitoring module includes: determining, by the monitoring module, the execution module corresponding to the extended instruction according to the extended instruction that has been stored to the local memory. It can be seen that the present invention can find a unique execution module for executing the extended instruction by first determining the manner of executing the module according to the extended instruction, which can ensure that the execution is performed after the monitoring module notifies the execution module to execute the extended instruction. The module can successfully execute the extended instruction.

In a possible design, the monitoring module saves the extended instruction in the instruction to the local memory, and the monitoring module may: the monitoring module saves the extended instruction in the instruction to the local memory according to a preset format, where the preset format includes the extended instruction. The instruction address, the content of the extended instruction, and the execution module corresponding to the extended instruction. It can be seen that the monitoring module of the present invention can store the extended instructions recognized from the on-chip bus according to the preset format, and can facilitate the management of the stored extended instructions. In addition, when it is necessary to determine a corresponding execution module for the extended instruction, the stored content may be directly called from the local memory to quickly lock the execution module corresponding to the extended instruction, and the execution module triggers the execution module to execute the extended instruction.

In a possible design, after the processor core executes the extended instruction by the execution module corresponding to the expansion instruction triggered by the monitoring module, the processor core temporarily stays in the exception handling program. It can be seen that when the processor core temporarily stays in the exception handler, it can be ensured that the processor core is It is currently possible to not continue executing instructions after the extended instruction.

In a possible design, the processor core temporarily stays in the exception handler, which can be implemented as follows: the processor core accesses a preset reserved memory address, and the reserved memory address does not correspond to any physical memory unit; when the monitoring module After sending a retry response to the processor core, the processor core accesses the reserved memory address again. It can be seen that when the processor core accesses the preset reserved memory address, since the monitoring module returns a retry response to the processor core, the processor core repeatedly accesses the preset reserved memory address, thereby ensuring the processor. The kernel can temporarily stay in the exception handler. This means that the processor core can temporarily not execute the next instruction after the extended instruction.

In a possible design, the monitoring module controls the processor core to exit the exception handler, which may be specifically implemented: after the monitoring module sends a normal completion response to the processor core, the processor core exits the exception handler. That is, the present invention can ensure that the processor core can exit the exception handler when necessary.

In a possible design, after the processor core decodes the extended instruction to generate an undefined instruction exception, the monitoring module generates a hardware signal for controlling whether the processor core stays in the exception handler; the monitoring module The processor core sends hardware signals. The processor core temporarily stays in the exception handler, which can be implemented as: When the hardware signal is low, the processor core temporarily stays in the exception handler. It can be seen that after the monitoring module generates a low-level hardware signal according to the content in the program counter and sends it to the processor core, it can ensure that the processor core can temporarily stay in the exception handling program. This means that the processor core can temporarily not execute the next instruction after the extended instruction.

In a possible design, the monitoring module controls the processor core to exit the exception handler, which can be implemented as: when the hardware signal is high, the processor core exits the exception handler. This means that the monitoring module can effectively control the working state of the processor core by generating different levels of hardware signals.

In a possible design, the processor core continues to execute the instruction after the extended instruction, which may be implemented as: the processor core restores the data of the general-purpose register, the program counter, and the status register that were backed up before executing the exception handler, and then according to the program. The next instruction address stored in the counter fetches the instruction from the next instruction address; the processor core executes the instruction corresponding to the next instruction address. It can be seen that after the execution module completes the execution process of the extended instruction, the processing core thereof can recover the breakpoint by the above method, and directly execute the instruction after the extended instruction.

In one possible design, the chip further includes a memory controller for reading instructions and data from the memory, and the monitoring module can be disposed in the memory controller or separated from the memory controller.

In another aspect, the invention provides an apparatus for extending a processor instruction set. The device can implement the functions performed by the monitoring module, the execution module and the processing module, that is, the processor core, in the example of the above method, and the functions can be implemented by hardware or by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above functions.

In a possible design, the structure of the device includes a processor and a communication interface, and the processing The device is configured to support the apparatus to perform the corresponding functions of the above methods. The communication interface is used to support communication between the device and other devices. The apparatus can also include a memory for coupling with the processor that retains the program instructions and data necessary for the apparatus.

The present invention provides a method and apparatus for extending a processor instruction set, as compared with a prior art using a coprocessor to execute a dedicated instruction such as a floating point instruction, or a hardware acceleration module as a peripheral of a processor. The processor sends the data to the acceleration module for processing through an interface such as PCIe. The present invention provides a chip internal structure, and ensures that the monitoring module can allocate the extended instruction to the extended instruction without modifying the processor core. Executing on the execution module, and in the process of executing the extended instruction by the execution module, causing the processor core to suspend execution of the instruction after the extended instruction to ensure the execution order of the instruction. Although the processor core cannot execute the extended instruction, since the execution module can execute the extended instruction, even if the processor core does not have the ability to execute the extended instruction, the execution module can be used to successfully complete the execution of the extended instruction. And after executing the extended instruction, triggering the processor core to continue executing the instruction after the extended instruction. In this way, it is equivalent to expanding the instruction set of the processor core, thus improving the processor's business processing capability and improving the processing speed of the processor.

DRAWINGS

1 is a schematic diagram of an internal structure of a chip according to an embodiment of the present invention;

FIG. 2 and FIG. 3 are schematic diagrams showing another internal structure of a chip according to an embodiment of the present invention; FIG.

4 is a schematic structural diagram of an embedded system according to an embodiment of the present invention;

FIG. 5 is an interaction diagram of a method for extending a processor instruction set according to an embodiment of the present invention;

FIG. 6 to FIG. 14 are schematic diagrams of another method for extending a processor instruction set according to an embodiment of the present invention; FIG.

FIG. 15 is a schematic structural diagram of an apparatus for extending an instruction set of a processor according to an embodiment of the present disclosure;

FIG. 16 is a schematic structural diagram of another apparatus for extending a processor instruction set according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

The embodiment of the present invention can be used in a chip. The chip can be internally provided with a processor core, a monitoring module and at least one execution module for executing the extended instruction, such as the accelerator 1 and the accelerator 2 as shown in FIG. 1 . The monitoring module and the at least one execution module for executing the extended instruction may be implemented by programmable logic (such as FPGA, CPLD, etc.). It should be noted that the chip may further include a memory controller. The memory controller is configured to read the instructions and the data from the memory, and the monitoring module may be disposed in the memory controller, or may be disposed in the chip together with the memory controller, which is not limited herein.

Taking the architecture shown in FIG. 1 as an example, an on-chip bus is disposed inside the chip, and the on-chip bus The function is similar to the AHB bus (English: Advanced High Performance Bus) in ARM (English: Advanced RISC Machine) architecture, which can be used to connect various internal chips. The function module; the chip also includes a processor core, such as an ARM core, having functions of fetching instructions, instruction decoding, instruction execution, etc.; the chip further includes at least one accelerator for realizing acceleration functions of various services, such as adding, Decryption, compression, decompression and other functions; the chip also includes a memory controller, the memory controller, external SDRAM (English: Synchronous Dynamic Random Access Memory, Chinese: synchronous dynamic random access memory), used to read commands from the SDRAM, Data, or write data to SDRAM. In the embodiment of the present invention, the memory shown in FIG. 1 can be regarded as the above SDRAM. The SDRAM interface may specifically include DDR (English: Double Data Rate, Chinese: Double Rate) 2, DDR3 or DDR4. It should be noted that an execution module such as an accelerator and a memory controller can be implemented by an FPGA (Field Programmable Gate Array, Chinese: Field Programmable Gate Array). In the actual application process, the modified logic configuration code can be loaded into the FPGA, so that the functions that the execution module and/or the memory controller can implement can be changed, which can be used to correct the design flaws, or New functions are added to the execution module and/or memory controller. It should be noted that the monitoring module can be set in the memory controller at this time.

Considering the existence of various on-chip bus standards, in addition to the above AHB bus, there are also CoreConnect, Wishbone or other custom buses, which can connect the various functional modules inside the chip to realize the between the modules. data transmission. In practical applications, multiple buses can be placed inside the chip to form a hierarchical structure. In the embodiment of the present invention, as shown in FIG. 2, the two buses can be connected by providing a bridge module between the two buses. For example, in the ARM architecture, in addition to the AHB bus, it can also include an APB bus (English: Advanced Peripheral Bus, Chinese: Advanced Peripheral Bus). Among them, the APB bus can be used to connect low-speed modules, and the AHB bus can be used to connect high-speed modules such as accelerators. It should be noted that the high-speed module and the low-speed module are separately connected, which can effectively avoid bus blocking and improve the throughput of the bus.

In the architecture shown in Figure 1 and Figure 2, in addition to the function of reading and writing memory, the memory controller needs to have a monitoring function, that is, it can monitor the instructions transmitted on the on-chip bus and save the extended instructions to the local In the instruction memory, it is also necessary to control the corresponding accelerator startup and receive the information of the completion of the acceleration operation. In the embodiment of the present invention, these functions can also be implemented by an independent monitoring module, that is, implemented by an FPGA, and can be dynamically modified to support new extended instructions, and the original memory controller can be used. Hard logic implementations are implemented without the use of an FPGA, which can help improve the performance of the memory interface. Taking the architecture shown in FIG. 1 as an example, the memory controller shown in FIG. 3 can be divided into a memory controller and a monitoring module according to the functions.

It should be noted that the above-mentioned chips as shown in FIG. 1 to FIG. 3 can be applied to an embedded system. For example, as shown in FIG. 4, in the embedded system, in addition to the chip, a memory, a BIOS (Chinese: Basic Input Output System, English: basic input/output system), a network interface chip, and a serial interface may be included. Chips, etc. Among them, the chip can be regarded as a processor, which is respectively connected with a memory, a BIOS, a network interface chip and a serial interface chip.

An embodiment of the present invention provides a method for extending a processor instruction set. As shown in FIG. 5, the method flow is performed by each module in a chip. The method process includes:

101. The processor core loads instructions from memory through an on-chip bus.

During the running of the system, the machine language programs are stored in the memory, and the processor core needs to continuously read the program codes from the memory, decode and execute them, thereby completing the functions corresponding to the instructions. Taking the ARM7 core's three-level instruction pipeline as an example, when the first instruction is being executed, the second instruction is being decoded, and the third instruction is being read from the memory. At this time, the content of the program counter is the third. The instruction address of the instruction.

In the embodiment of the present invention, when the processor core reads the program code from the memory, the code passes through the on-chip bus. At this time, the monitoring module and the accelerator implemented by the FPGA can recognize the instructions. In order to facilitate the identification of the module by the monitoring module and the execution module, in the embodiment of the invention, the AHB bus defines the HPROT[3:0] signal. Among them, HPROT[0]=0 means that the current bus operation is fetching, HPROT[0]=1 means that the current bus operation is fetching data. Moreover, this signal can be connected to all devices on the on-chip bus, which means that other devices can use the level of the HPROT[3:0] signal to distinguish whether the instruction is currently being transmitted on the on-chip bus, and only When the instruction transmitted on the on-chip bus is an instruction, step 102 is performed.

102. The monitoring module identifies the instruction through the on-chip bus, and saves the extended instruction in the instruction to the local memory.

When the monitoring module recognizes that there is an extended instruction in the instruction transmitted through the on-chip bus, the extended instruction can be directly saved to the local memory. It should be noted that the execution module may also save the extension instruction locally and temporarily not execute the extension instruction. That is, when HPROT[0]=0, and the instruction transmitted through the on-chip bus is an extended instruction, the monitoring module stores the extended instruction in the local instruction memory, that is, in the local memory. At the same time, the execution module that recognizes the extension instruction will also save this instruction locally. At this time, the execution module does not execute the extended instruction, but waits for the monitoring module to issue information that triggers the execution module to execute the extended instruction.

103. After the processor core loads the extended instruction, the processor core decodes the extended instruction to generate an undefined instruction exception.

The extended instruction is an extended instruction that has been stored in the local memory.

When the processor core decodes the extended instruction, since the processor core cannot recognize the extended instruction, the processor core generates an "undefined instruction" exception, that is, an undefined instruction exception is generated, and jumps to " The handler corresponding to the "undefined instruction" is executed. It should be noted that after the undefined instruction exception is generated, it will not be executed immediately, but will not be processed until the currently executing instruction is executed. The specific processing manner will be mentioned later, and will not be described here.

104. After the processor core executes the current instruction, the processor core executes an exception handler.

Among them, the exception handler is a program triggered by an undefined instruction exception.

At the beginning of the execution of the exception handler, the processor core saves the current breakpoint, which is the contents of the general purpose registers, program counters, and status registers of the backup processor core. For the ARM7 core, the value of the backup program counter is equal to the content of the current program counter minus 4, that is, the instruction address of the next instruction of the extended instruction, and the instruction address is used as the return address of the exception handler; Change the content of the program counter, that is, the start address of the handler that sets the undefined instruction exception, for example: set to 0x0000_0004; the processor core loads the code from the memory address specified by the program counter, and this code is the exception handler.

It should be noted that when the processor core executes the exception handler, the processor core suspends the execution of the instruction after the extended instruction, and notifies the monitoring module to ensure that the monitoring module can trigger the execution module corresponding to the extended instruction to execute the extended instruction. In the embodiment of the present invention, after the execution module completes the execution operation of the extended instruction, the completion information may be sent to the monitoring module through the on-chip bus, or the monitoring module may be notified by performing a handshake signal between the module and the monitoring module.

105. The monitoring module triggers an execution module corresponding to the extended instruction to execute the extended instruction.

106. The execution module executes the extended instruction.

107. The execution module sends a message to the monitoring module that the execution module executes the extended instruction.

108. The monitoring module controls the processor core to exit the exception handler.

After the corresponding execution module executes the extended instruction, the monitoring module can control the processor core to exit the exception processing program, and execute step 109. The specific implementation manner will be described later, and will not be further described herein.

109. The processor core continues to execute instructions after the extended instruction.

In the present invention, a chip internal structure is proposed. Under the premise of not modifying the processor core, it is ensured that the monitoring module can allocate the extended instruction to the execution module corresponding to the extended instruction, and the execution module performs the expansion. During the instruction, the processor core is suspended to execute the instruction after the extended instruction to ensure the order of execution of the instruction. Although the processor core cannot execute the extended instruction, since the execution module can execute the extended instruction, even if the processor core does not have the ability to execute the extended instruction, the execution module can be used to successfully complete the execution of the extended instruction. And after executing the extended instruction, triggering the processor core to continue executing the instruction after the extended instruction. In this way, it is equivalent to expanding the instruction set of the processor core, thus improving the processor's business processing capability and improving the processing speed of the processor.

In an implementation manner of the embodiment of the present invention, each execution module can execute at least one extended instruction, each extended instruction corresponds to one instruction address, and the monitoring module can be based on the processor core. The content of the program counter when the undefined instruction exception is generated is used to determine the instruction address of the next instruction of the extended instruction, and then the instruction address of the extended instruction is derived, and the execution module corresponding to the extended instruction is notified to execute the extended instruction. Therefore, on the basis of the implementation shown in FIG. 5, an implementation as shown in FIG. 6 can also be implemented. After the step 104 is performed, the step 110 is performed. The step 105 is performed by the execution module that is triggered by the monitoring module to trigger the extension instruction, and may be specifically implemented as step 1051 and step 1052:

110. The processor core sends the monitoring module a content in the program counter when the processor core generates an undefined instruction exception.

The content in the program counter is the instruction address of the next instruction of the extended instruction.

Before the processor core enters the exception handler, the processor core needs to back up the contents of the program counter when an undefined instruction exception is generated, and then perform exception handling in the processor core. In the program, the processor core needs to send the content that has been backed up to the monitoring module.

1051. The monitoring module determines an instruction address of the extended instruction according to an instruction address of the next instruction.

1052. The monitoring module notifies the execution module corresponding to the extended instruction to execute the extended instruction corresponding to the instruction address.

In a program instruction, there may be a jump instruction or a conditional instruction. For a jump instruction, the program does not execute in order when executing the instruction, but skips the following several instructions to continue execution; for a conditional instruction, the program needs to determine whether it satisfies before executing an instruction. If the condition is not met, the instruction will not be executed. Therefore, the previously saved extended instruction does not need to be executed. It is very possible to skip the extended instruction to execute the following instruction. For example, as shown in Table 1, a program segment includes five instructions in sequence, and the first three lines have entered the instruction pipeline. The first instruction is a jump instruction, which requires a jump to the third instruction. In this way, the extended instruction 1 Although it has been previously saved to the local memory of the monitoring module and the corresponding execution module, it is not executed, and the actual instruction that needs to be executed is the extended instruction 2. Therefore, in order to prevent the execution module from executing the wrong extended instruction, the monitoring module needs to inform the execution module corresponding to the extended instruction of the information of the extended instruction that should be currently executed.

Table I

Instruction number	Instruction type
First instruction	Jump instruction
Second instruction	Extended instruction 1
Third instruction	Ordinary instruction 1
Fourth instruction	Extended instruction 2

When the processor core executes the extended instruction 2, that is, during the decoding of the extended instruction 2, an undefined instruction exception is generated, and the processor core enters the exception handler. At this point, the processor core needs to obtain the saved breakpoint address, that is, the instruction address of the next instruction of the extended instruction, and send the instruction address of the next instruction to the monitoring module, or subtract the 4 and send it to the monitoring module. . Considering that the length of each instruction is 4 bytes, the monitoring module can determine the address of the extended instruction 2 itself according to the instruction address sent by the processor core.

The embodiment of the present invention provides a method for extending a processor instruction set. When a processor core executes an exception handler, the processor core suspends execution of an instruction after the extended instruction, and sends the undefined instruction to the monitoring module when the processor core generates an undefined instruction. The instruction address of the next instruction in the program counter at the time of the exception, and then the monitoring module determines the instruction address of the extended instruction according to the instruction address of the next instruction, and notifies the execution module corresponding to the extended instruction to execute the extended instruction corresponding to the instruction address. The invention can accurately calculate the instruction address of the extended instruction according to the instruction address of the next instruction recorded in the acquired program counter, thereby ensuring that the monitoring module can timely notify the execution module that can execute the extended instruction to execute the extended instruction. .

Considering that a plurality of execution modules may be disposed in the chip, and each execution module corresponds to at least one extended instruction that can be executed. Therefore, in order to ensure that the execution module triggered by the monitoring module can be used to execute the extended instruction, in the embodiment of the present invention In an implementation manner, before the monitoring module executes the extended instruction, the monitoring module needs to determine which execution module is to be notified. Therefore, on the basis of the implementation shown in FIG. 6, an implementation as shown in FIG. 7 can also be implemented. If the execution module corresponding to the extended instruction is executed by the monitoring module in step 1052, the execution module corresponding to the instruction address is executed, and step 111 is performed:

111. The monitoring module determines an execution module corresponding to the extended instruction according to the extended instruction that has been stored to the local storage.

The local memory of the monitoring module stores a correspondence between the extended instruction and the execution module. Therefore, the monitoring module can determine the execution module corresponding to each extended instruction according to the content of the stored extended instruction.

The method for extending the processor instruction set provided by the embodiment of the present invention, before the monitoring module notifies the execution module to execute the extended instruction, the monitoring module needs to determine the execution module corresponding to the extended instruction according to the extended instruction. The present invention can find a unique execution module for executing the extended instruction by first determining the manner of executing the module according to the extended instruction, which can ensure that the execution module can be successfully executed after the monitoring module notifies the execution module to execute the extended instruction. The extension instruction.

In an implementation manner of the embodiment of the present invention, the monitoring module may store the extended instruction in the instruction to the local storage according to a preset format, so as to be subsequently stored according to the storage. The content to accurately determine the execution module corresponding to the extended instruction. Therefore, on the basis of the implementation shown in FIG. 5, it can also be implemented as the implementation shown in FIG. The step 102: The monitoring module identifies the instruction by the on-chip bus, and saves the extended instruction in the instruction to the local memory, which may be specifically implemented as step 1021:

1021. The monitoring module identifies the instruction by using an on-chip bus, and saves the extended instruction in the instruction to the local memory according to a preset format.

The preset format includes an instruction address of the extended instruction, a content of the extended instruction, and an execution module corresponding to the extended instruction.

The format in which the extended instruction is saved to the local memory of the monitoring module is as shown in Table 2, in which the instruction address and content of each extended instruction are stored, and the execution module corresponding to each extended instruction is stored. When the monitoring module receives the instruction address sent by the processor core, it can find out which instruction is currently executing the extended instruction according to the instruction address and the contents shown in Table 2, and which execution is performed by the extended instruction. The module then sends the above content to the corresponding execution module.

Table II

Instruction address of the extended instruction	Extended instruction content	Execution module corresponding to the extended instruction
Instruction address 1	Extended instruction 1	Accelerator 1
Instruction address 2	Extended instruction 2	Accelerator 1
Instruction address 3	Extended instruction 3	Accelerator 2
Instruction address 4	Extended instruction 4	Accelerator 2

After the accelerator receives the information, the data is read from the specified source data address according to the content of the extended instruction, and the corresponding acceleration operation is performed, and then saved to the specified target address.

The method for extending the processor instruction set provided by the embodiment of the present invention, after the monitoring module recognizes the extended instruction by the on-chip bus, the monitoring module stores the identified extended instruction, and the storage format is as follows: the instruction address, the content, and the corresponding Execution module. The monitoring module of the invention can pass By storing the extended instructions identified from the on-chip bus in a preset format, it is convenient to manage the stored extended instructions. In addition, when it is necessary to determine a corresponding execution module for the extended instruction, the stored content may be directly called from the local memory to quickly lock the execution module corresponding to the extended instruction, and the execution module triggers the execution module to execute the extended instruction.

In an implementation manner of the embodiment of the present invention, the processor core may temporarily stay in the exception handling program, and thus, in an implementation manner as shown in FIG. 6, in order to ensure that the processor core can suspend execution of the instruction after the extended instruction. In addition, it can also be implemented as an implementation as shown in FIG. After performing the step 1052, the monitoring module notifies the execution module corresponding to the extended instruction to execute the extended instruction corresponding to the instruction address, and may perform step 112:

112. The processor core temporarily stays in the exception handler.

Considering that after the processor core enters the exception handler, it cannot temporarily exit, otherwise the processor core will continue to execute the instruction after the extended instruction that generates the undefined instruction exception. If the subsequent instruction depends on the execution result of the execution module corresponding to the extended instruction that generated the undefined instruction exception, the data will be in error. Therefore, the processor core must wait until the execution module completes the execution of the extended instruction before exiting the exception handler. Therefore, after the processor core starts executing the exception handler, the exception handler can be exited only after the execution module completes the execution of the extension instruction. Otherwise, the processor core will stay in the exception handler. For example, the processor core cannot exit the exception handler until the accelerator completes the acceleration operation, that is, the processor core needs to temporarily stay in the exception handler.

A method for extending a processor instruction set according to an embodiment of the present invention can ensure that a processor core suspends execution of an instruction after an extended instruction by temporarily causing a processor core to stay in an exception handler. In the present invention, when the processor core temporarily stays in the exception handler, it is possible to ensure that the processor core is currently unable to continue executing the instruction after the extension instruction.

In order to ensure that the processor core can temporarily stay in the exception handler, in one implementation of the embodiment of the present invention, the processor core can temporarily stay in the exception handler by repeatedly accessing the preset reserved memory address. Therefore, on the basis of the implementation shown in FIG. 9, an implementation as shown in FIG. 10 can also be implemented. The processor core of step 112 temporarily stays in the exception handling program, and can be specifically implemented as step 1121 to step 1123:

1121. The processor core accesses a preset reserved memory address.

The reserved memory address does not correspond to any physical memory unit.

1122. The monitoring module sends a retry response to the processor core.

1123. The processor core accesses the reserved memory address again.

When the processor core accesses the preset reserved memory address, since the reserved memory address does not correspond to any one of the physical memory units, the monitoring module monitors that the processor core accesses the reserved memory address and can pass the HRESP of the AHB bus [1:0]. The signal and the HREADY signal respond to the processor core, ie retry the response. When HRESP[1:0]=10 and HREADY=0, it indicates RETRY response. At this time, the processor core will repeatedly try again until it succeeds. It should be noted that when HRESP[1:0]=10 and HREADY=0, the processor core repeatedly executes the instruction to access the reserved memory address, and does not continue to execute the instruction after the extended instruction.

A method for extending a processor instruction set according to an embodiment of the present invention can ensure that a processing core can temporarily stay in an exception handling program by causing a processor to repeatedly access a preset reserved memory address. In the present invention, when the processor core accesses the preset reserved memory address, since the monitoring module returns a retry response to the processor core, the processor core repeatedly accesses the preset reserved memory address, thereby ensuring the processor. The kernel can temporarily stay in the exception handler. This means that the processor core can temporarily not execute the next instruction after the extended instruction.

In an implementation manner of the embodiment of the present invention, after the processor core receives the normal completion response sent by the monitoring module, the processing is performed in order to ensure that the processor core can exit the exception processing program and then continue to execute the instruction after the extended instruction. The kernel exits the exception handler. Therefore, on the basis of the implementation shown in FIG. 10, an implementation as shown in FIG. 11 can also be implemented. The step 108 of the monitoring module controls the processor core to exit the exception handling process, which may be specifically implemented as step 1081 and step 1082:

1081. The monitoring module sends a normal completion response to the processor core.

It should be noted that the normal completion response is a response of the processor core to complete the access process normally after accessing the reserved memory address.

1082. The processor core exits the exception handler.

After the monitoring module knows that the execution module has executed the extended instruction, if the processor core initiates the retry operation again, it will return a signal of HRESP[1:0]=00 and HREADY=1 to the processor core. Among them, HRESP[1:0]=00 represents the OKAY response, so the processor core completes the execution of the current instruction, exits the exception handler, and continues to execute the instruction after the extended instruction.

The method for extending the processor instruction set provided by the embodiment of the present invention may enable the processor core to exit the exception handling program after receiving the normal completion response sent by the monitoring module. The present invention ensures that the processor core can exit the exception handler if necessary.

In an implementation manner of the embodiment of the present invention, in addition to ensuring that the processor core temporarily stays in the exception handling program by repeatedly accessing the preset reserved memory address by the processor core, the monitoring module may also send a hardware signal to the processor core. And when the hardware signal is low, the processor core temporarily stays in the exception handler. Therefore, on the basis of the implementation shown in FIG. 9, an implementation as shown in FIG. 12 can also be realized. After the step 103 is performed, the step 114 and the step 115 are performed. The processor core temporarily stays in the exception handling program, and may be specifically implemented as step 1124:

114. The monitoring module generates a hardware signal.

Among them, the hardware signal is used to control whether the processor core stays in the exception handler.

115. The monitoring module sends a hardware signal to the processor core.

1124. When the hardware signal is low, the processor core temporarily stays in the exception handler.

A method for extending a processor instruction set according to an embodiment of the present invention, after the processor core generates an undefined instruction exception, the processor core sends the content of the backup program counter to the monitoring module, and then the monitoring module receives the received The contents of the program counter generate hardware signals and send them to the processor core. When the hardware signal received by the processor core is low, the processor core is suspended, which is equivalent to the processor core temporarily staying in the exception handler. In the present invention, After the monitoring module generates a low-level hardware signal according to the contents of the program counter and sends it to the processor core, it can ensure that the processor core can temporarily stay in the exception handler. This means that the processor core can temporarily not execute the next instruction after the extended instruction.

Considering that after the execution module completes the execution process of the extended instruction, the processor core needs to continue to execute the instruction after the extended instruction. In an implementation manner of the embodiment of the present invention, the hardware signal sent to the processor core according to the monitoring module may be high. At the level, the processor core continues to execute instructions following the extended instruction. Therefore, on the basis of the implementation shown in FIG. 12, an implementation as shown in FIG. 13 can also be realized. The step 108 of the monitoring module controls the processor core to exit the exception handling process, which may be specifically implemented as step 1083:

1083. When the hardware signal is high, the processor core exits the exception handler.

The embodiment of the present invention provides a method for extending a processor instruction set. When a hardware signal sent by a monitoring module to a processor core is a high level, the processor core continues to execute an instruction after the extended instruction. In the present invention, the monitoring module can effectively control the operating state of the processor core by generating hardware signals of different levels.

In order to ensure that the processor core can successfully execute the next instruction after the extended instruction, in one implementation of the embodiment of the present invention, the processor core needs to continue executing the next instruction following the extended instruction after restoring the breakpoint. Therefore, on the basis of the implementation shown in FIG. 11 or 13, the content shown in FIG. 11 can be taken as an implementation as shown in FIG. The step 109 after the processor core continues to execute the instruction after the extended instruction may be specifically implemented as step 1091 to step 1093:

1091. The processor core restores data of a general-purpose register, a program counter, and a status register that were backed up before executing the exception handler.

After the processor core exits the exception handler, it needs to restore the breakpoint before continuing to execute the next instruction after the extended instruction. Therefore, the processor core needs to use the general-purpose register, program counter, and status register of the previously backed-up processor core. Restore to the corresponding register.

1102: The processor core fetches an instruction from the next instruction address according to the next instruction address stored in the program counter.

The processor core fetches instructions from the corresponding instruction address according to the new value of the program counter. At this time, the processor core has exited the exception handler.

1093. The processor core executes an instruction corresponding to the next instruction address.

The processor core continues to execute instructions following the extended instruction that produced the undefined instruction exception.

The embodiment of the present invention provides a method for extending a processor instruction set. The processor core recovers data of a general-purpose register, a program counter, and a status register stored before executing an exception processing program, and according to a next instruction address stored in the program counter. , fetch the instruction from the next instruction address, and then execute the instruction corresponding to the next instruction address. Compared with the prior art, the coprocessor is used to execute a dedicated instruction such as a floating point instruction, or the hardware acceleration module is used as a peripheral of the processor, and the processor sends the data to the acceleration module through the PCIe interface, etc. The invention can achieve the effect of extending the instruction set of the processor core without modifying the processor core, thereby improving the processing speed of the processor.

The solution provided by the embodiment of the present invention is mainly introduced from the perspective of interaction between modules in the chip. It can be understood that each module, such as a monitoring module, an execution module, a processing module, etc., in order to implement the above functions, includes hardware structures and/or software modules corresponding to the execution of the respective functions. Those skilled in the art will readily appreciate that the present invention can be implemented in a combination of hardware or hardware and computer software in combination with the elements and algorithm steps of the various examples described in the embodiments disclosed herein. Whether a function is implemented in hardware or computer software to drive hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods for implementing the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.

The embodiment of the present invention may perform the division of the function module on the device that expands the processor instruction set according to the foregoing method example. For example, each function module may be divided according to each function, or two or more functions may be integrated into one processing module. in. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of the module in the embodiment of the present invention is schematic, and is only a logical function division, and the actual implementation may have another division manner.

FIG. 15 is a schematic diagram showing a possible structure of an apparatus for expanding an instruction set of the processor in the foregoing embodiment. The device 20 includes: a processing module 21 and a monitoring module. 22. Execution module 23. The processing module 21 is configured to execute the instruction, or pause the execution of the instruction after the extended instruction after the departure field processing program, and resume the breakpoint at an appropriate timing, and continue to execute the instruction after the extended instruction, for example, in FIG. 5 Processes 101, 103 and 104, 109, process 112 in FIG. 9, processes 1121 and 1123 in FIG. 10, process 1082 in FIG. 11, process 1124 in FIG. 12, process 1083 in FIG. 13, and FIG. The process module 1091 to 1093; the monitoring module 22 is configured to identify an extended instruction that passes through the on-chip bus, and save it in the local memory, and then trigger the corresponding execution module to execute the extended instruction, and the subsequent control processing module exits the exception handling program, for example: Processes 102, 105, 108 in FIG. 5, processes 1051 and 1052 in FIG. 6, process 111 in FIG. 7, process 1122 in FIG. 10, process 1081 in FIG. 11, processes 114 and 115 in FIG. The execution module 23 is configured to execute the extended instruction and feed back to the monitoring module after completing the execution process, such as the processes 106 and 107 in FIGS. 5 to 14. The apparatus 20 can also include a storage module 24 for storing associated program code and data. All the related content of the steps involved in the foregoing method embodiments may be referred to the functional descriptions of the corresponding functional modules, and details are not described herein again.

The processing module 21 may be a processor or a controller, for example, a central processing unit (English: Central Processing Unit, CPU for short), a general-purpose processor, and a digital signal processor (English: Digital Signal Processor, referred to as DSP). , Application-Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or random combination. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure. The processor may also be a combination of computing functions, for example comprising one or more microprocessor combinations. A combination of DSP and microprocessor, and so on. The storage module 24 can be a memory.

When the processing module 21 and the execution module 23 are processors, and the storage module 24 is a memory, and the data is transmitted through the communication interface between the modules, the apparatus for expanding the processor instruction set according to the embodiment of the present invention may be as shown in FIG. The device 30 is shown.

Referring to FIG. 16, the apparatus 30 includes a processor 31, a communication interface 32, a memory 33, and a bus 34. The communication interface 32, the processor 31, and the memory 33 are connected to each other through a bus 34. The bus 34 may be a Peripheral Component Interconnect (PCI) bus or an extended industry standard structure (English: Extended Industry) Standard Architecture, referred to as EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 16, but it does not mean that there is only one bus or one type of bus.

The steps of a method or algorithm described in connection with the present disclosure may be implemented in a hardware, or may be implemented by a processor executing software instructions. The software instructions may be composed of corresponding software modules, and the software modules may be stored in a random access memory (English: Random Access Memory, RAM for short), flash memory, read only memory (English: Read Only Memory, referred to as: ROM), Erase programmable read-only memory (English: Erasable Programmable ROM, referred to as: EPROM), electrically erasable programmable read-only memory (English: Electrically EPROM, referred to as: EEPROM), registers, hard disk, mobile hard disk, read-only optical disk (referred to as : CD-ROM) or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor to enable the processor to read information from, and write information to, the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC. Additionally, the ASIC can be located in a core network interface device. Of course, the processor and the storage medium may also exist as discrete components in the core network interface device.

Those skilled in the art will appreciate that in one or more examples described above, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored in a computer readable medium or transmitted as one or more instructions or code on a computer readable medium. Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage medium may be any available media that can be accessed by a general purpose or special purpose computer.

The specific embodiments of the present invention have been described in detail with reference to the preferred embodiments of the present invention. The scope of the protection, any modifications, equivalent substitutions, improvements, etc., which are made on the basis of the technical solutions of the present invention, are included in the scope of the present invention.

Claims (22)

1. A method for extending a processor instruction set, the method being for a chip, the chip comprising a processor core, a monitoring module, and at least one execution module for executing an extended instruction, the monitoring module and The at least one execution module for executing the extended instruction is implemented by programmable logic, the method comprising:

   The monitoring module identifies an instruction by an on-chip bus, the instruction being an instruction that the processor core loads from a memory through the on-chip bus;

   The monitoring module saves the extended instruction in the instruction to a local memory;

   After the processor core loads from the memory to the extended instruction via the on-chip bus, the processor core decodes the extended instruction to generate an undefined instruction exception, the extended instruction being stored to the local memory The extended instruction in

   After the processor core executes the current instruction, the processor core executes an exception handler, and the exception handler is a program triggered by the undefined instruction exception;

   When the processor core executes the exception processing program, the processor core suspends execution of the instruction after the extended instruction, and triggers, by the monitoring module, an execution module corresponding to the extended instruction to execute the extended instruction;

   The monitoring module controls the processor core to exit the exception handler to facilitate execution of the instructions following the extended instruction by the processor core.
2. The method according to claim 1, wherein each execution module is capable of executing at least one extended instruction, each extended instruction corresponding to an instruction address, and the processor core triggers, by the monitoring module, the extended instruction The execution module executes the extended instruction, including:

   The processor core sends, to the monitoring module, content in a program counter when the processor core generates the undefined instruction abnormality, and the content in the program counter is an instruction address of a next instruction of the extended instruction ;

   The monitoring module determines an instruction address of the extended instruction according to an instruction address of the next instruction;

   The monitoring module notifies the execution module corresponding to the extended instruction to execute an extended instruction corresponding to the instruction address.
3. The method according to claim 2, wherein before the monitoring module notifies the execution module corresponding to the extension instruction to execute the extension instruction corresponding to the instruction address, the method includes:

   The monitoring module determines an execution module corresponding to the extended instruction according to the extended instruction that has been stored to the local storage.
4. The method according to any one of claims 1 to 3, wherein the monitoring module saves the extended instruction in the instruction to the local memory, including:

   The monitoring module saves the extended instruction in the instruction to the local memory according to a preset format, where the preset format includes an instruction address of the extended instruction, a content of the extended instruction, and a corresponding corresponding to the extended instruction. Execution module.
5. The method according to claim 2, after the execution of the extension instruction by the execution module of the execution module by the processor module, the method includes:

   The processor core temporarily stays in the exception handler.
6. The method of claim 5, wherein the processor core temporarily stays in the exception handler, comprising:

   The processor core accesses a preset reserved memory address, where the reserved memory address does not correspond to any one of the physical memory units;

   After the monitoring module sends a retry response to the processor core, the processor core accesses the reserved memory address again.
7. The method according to claim 6, wherein the monitoring module controls the processor core to exit the exception handling program, including:

   After the monitoring module sends a normal completion response to the processor core, the processor core exits the exception handler.
8. The method of claim 5, wherein after the processor core decodes the extended instruction to generate an undefined instruction exception, the method comprises:

   The monitoring module generates a hardware signal, and the hardware signal is used to control whether the processor core stays in the exception handling program;

   The monitoring module sends the hardware signal to the processor core;

   The processor core temporarily stays in the exception handler, including:

   When the hardware signal is low, the processor core temporarily stays in the exception handler.
9. The method according to claim 8, wherein the monitoring module controls the processor core to exit the exception handling program, including:

   The processor core exits the exception handler when the hardware signal is high.
10. The method according to claim 7 or 9, wherein the processor core continues to execute the instructions after the extended instruction, including:

    The processor core recovers data of a general-purpose register, a program counter, and a status register that are backed up before execution of the exception handler;

    The processor core fetches an instruction from the next instruction address according to a next instruction address stored in the program counter;

    The processor core executes an instruction corresponding to the next instruction address.
11. The method of claim 1 wherein said chip further comprises a memory controller, said memory controller for reading instructions and data from said memory, said monitoring module being configurable in said memory control In the device, or in the same manner as the memory controller is disposed in the chip.
12. An apparatus for expanding a processor instruction set, wherein the apparatus is for a chip, the chip comprising a processing module, a monitoring module, and at least one execution module for executing an extended instruction, the monitoring module and the The at least one execution module for executing the extended instruction is implemented by programmable logic, and the apparatus includes:

    The monitoring module is configured to identify an instruction by an on-chip bus, where the instruction is an instruction that the processing module loads from a memory through the on-chip bus;

    The monitoring module is further configured to save the extended instruction in the instruction to a local memory;

    The processing module is configured to decode an extended instruction after the processing module loads the extended instruction from the memory by using the on-chip bus, to generate an undefined instruction abnormality, where the extended instruction is stored to the local The extended instruction in the memory;

    The processing module is further configured to: after the processing module executes the current instruction, execute an exception processing program, where the exception processing program is a program triggered by the undefined instruction exception;

    The processing module is further configured to suspend execution of the instruction after the extended instruction when the processing module executes the exception processing program, and trigger an execution module corresponding to the extended instruction to perform the expansion by using the monitoring module instruction;

    The monitoring module is configured to control the processing module to exit the exception handling program, so that the processing module continues to execute the instruction after the extended instruction.
13. The apparatus according to claim 12, wherein each execution module is capable of executing at least one extended instruction, each extended instruction corresponding to an instruction address, and the processing module is specifically configured to send to the monitoring module The processing module generates content in the program counter when the undefined instruction is abnormal, and the content in the program counter is an instruction address of a next instruction of the extended instruction;

    The monitoring module is specifically configured to determine an instruction address of the extended instruction according to an instruction address of the next instruction;

    The monitoring module is further configured to notify the execution module corresponding to the extended instruction to execute an extended instruction corresponding to the instruction address.
14. The apparatus according to claim 13, wherein the monitoring module is further configured to determine an execution module corresponding to the extended instruction according to the extended instruction that has been stored to the local storage.
15. The device according to any one of claims 12 to 14, wherein the monitoring module is configured to save the extended instruction in the instruction to the local memory according to a preset format, the preset The format includes an instruction address of the extended instruction, a content of the extended instruction, and an execution module corresponding to the extended instruction.
16. The apparatus according to claim 13, wherein said processing module is further configured to temporarily stay in said exception handling program.
17. The device according to claim 16, wherein the processing module is configured to access a preset reserved memory address, where the reserved memory address does not correspond to any one of the physical memory units;

    After the monitoring module sends a retry response to the processing module, the reserved memory address is accessed again.
18. The device according to claim 17, wherein the processing module is further configured to exit the exception handling program after the monitoring module sends a normal completion response to the processing module.
19. The apparatus according to claim 16, wherein the monitoring module is further configured to generate a hardware signal, where the hardware signal is used to control whether the processing module stays in the exception processing program;

    The monitoring module is further configured to send the hardware signal to the processing module;

    The processing module is specifically configured to temporarily stay in the exception handling program when the hardware signal is low.
20. The device according to claim 19, wherein the processing module is further configured to exit the exception handling program when the hardware signal is high.
21. The device according to claim 18 or 20, wherein the processing module is specifically configured to recover data of a general-purpose register, a program counter, and a status register that are backed up before the execution of the exception processing program;

    Obtaining an instruction from the next instruction address according to a next instruction address stored in the program counter;

    Execute the instruction corresponding to the next instruction address.
22. The apparatus according to claim 12, wherein said chip further comprises a memory controller, said memory controller is operative to read instructions and data from said memory, said monitoring module being configurable in said memory control In the device, or in the same manner as the memory controller is disposed in the chip.

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