CN104679687A - Method and device for recognizing interruption source - Google Patents
Method and device for recognizing interruption source Download PDFInfo
- Publication number
- CN104679687A CN104679687A CN201410797967.7A CN201410797967A CN104679687A CN 104679687 A CN104679687 A CN 104679687A CN 201410797967 A CN201410797967 A CN 201410797967A CN 104679687 A CN104679687 A CN 104679687A
- Authority
- CN
- China
- Prior art keywords
- interrupt
- data field
- message
- interrupt source
- peripherals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Bus Control (AREA)
Abstract
An embodiment of the invention discloses a method for recognizing an interruption source. By the method and the device for recognizing the interruption source, the problem that an interruption source is difficult to recognize in the prior art is solved. The method comprises the following steps of writing an interruption number corresponding to an interruption source which is an optional interrupted module of peripheral equipment in data field high 16 bits of a message passing interrupt capability structure; combining the data field high 16 bits in a data passing interrupted message by using the peripheral equipment; and transmitting the message to a central processing unit (CPU) by using the peripheral equipment so that the CPU recognizes the peripheral equipment according to data field low 16 bits of the message and recognizes the interruption source according to the data field high 16 bits of the message. The embodiment of the invention also provides a device for recognizing the interruption source.
Description
Technical field
The present invention relates to the communications field, be specifically related to a kind of method and the device that identify interrupt source.
Background technology
In computer systems, which, peripherals needs central processing unit (Central Processing Unit usually, CPU) interrupt processing is performed, such as peripherals needs CPU to read data, or peripherals need CPU process peripherals be in operation occur mistake, capital sends look-at-me to CPU, CPU suspends the task of current execution after receiving look-at-me, turn and remove to perform interrupt handling routine corresponding to the peripherals that sends look-at-me, namely data are read, process mistake etc., wherein, the peripherals sending look-at-me can be called interrupt source (this defines from the angle of peripherals outside), also can by cause peripherals inner go out present condition change and the module making peripherals send look-at-me is referred to as interrupt source that (this defines from the angle of peripherals inside, granularity is less), such as the data reception module of peripherals inside detects data check mistake, or reception buffer zone is overflowed, interrupt source can be can be regarded as, therefore, identify that interrupt source is the correct interrupt handling routine performing correspondence, make the prerequisite that computer system is normally run.
At present, a kind of prior art is: peripheral component interconnect bus (Peripheral Component Inte rconnect, PCI) INTA#/INTB#/INTC#/INTD# tetra-interrupt pin (# represents Low level effective) are supported, wherein, interruptable controller is connected with in bridge sheet, when there being interruption to occur, certain pin becomes low level, then interruptable controller notice CPU performs interrupt processing, multiple PCI equipment can share certain look-at-me, CPU needs the interrupt status register inquiring about each PCI device interior when an interrupt occurs, confirm concrete interrupt source.PCI equipment one and the PCI equipment two of such as Fig. 1 share INTA# signal, if PCI equipment two interrupts, the interrupt status register that so CPU must access PCI equipment one and PCI equipment two inside successively just can be confirmed to be the interruption that PCI equipment two produces, thus performs corresponding interrupt handling routine.But the interrupt status register of accessing PCI device interior due to CPU needs through gap bridge sheet and PCI equipment, and speed is slow, because this increasing the expense of interrupt processing delay and CPU.
Another kind of prior art is: peripheral component interconnect bus express passway (Peripheral Component Interconnect express, PCIe) support that Message Transmission interrupts (Message Signaled Interrupt, MSI) or expansion Message Transmission interrupt (Message Signaled Interrupt extension, MSI-X) mode, when there being interruption to occur, exclusive interrupt number is initiatively sent to the interruptable controller be connected in bridge sheet by the PCIe equipment of such as Fig. 2 by PCIe interface, interruptable controller is transmitted to CPU again, such CPU directly can confirm the peripherals occurring to interrupt, wherein, MSI agreement supports at most 32 interrupt numbers, MSI-X supports at most 2048 interrupt numbers, the mode of relative hardware interrupt supports more interrupt source.But consider the cost of realization, what the interrupt number number that actual PCIe equipment can be supported defined more than agreement lacks, current MSI or MSI-X mode cannot accomplish that each interrupt source has oneself interrupt number, still needs CPU to inquire about concrete interrupt source.
Summary of the invention
Embodiments provide a kind of method and the device that identify interrupt source, for solving in prior art the problem identified existing for interrupt source.
First aspect present invention provides a kind of method identifying interrupt source, comprising:
When any one module of peripherals occurs to interrupt, described module is as interrupt source by high 16 for the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, and described peripherals comprises the module of multiple different levels;
Described peripherals is incorporated into the message that Message Transmission interrupts by high for described data field 16, it is low 16 that described message also comprises data field;
The described message be incorporated into is sent to central processor CPU by described peripherals, to make described CPU identify described peripherals according to low 16 of the data field of described message, identifies described interrupt source according to high 16 of the data field of described message.
In conjunction with first aspect, in the implementation that the first is possible, described method also comprises:
When the upper layer module that described interrupt source is corresponding detects described interrupt source generation interruption, described upper layer module is by high 16 for the data field of interrupt number corresponding for described upper layer module write Message Transmission interrupt capabilities structure.
In conjunction with first aspect, in the implementation that the second is possible, described module comprises as high 16 of the data field of interrupt source by interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure:
Described module is as the field of interrupt source by correspondence in high 16 of the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, high 16 of described data field has multiple field, and the field that described data field is high 16 level corresponding with the module of described peripherals becomes corresponding relation.
In conjunction with the first possible implementation of first aspect, in the implementation that the third is possible, upper layer module corresponding to described interrupt source detects described interrupt source generation interruption and comprises:
Upper layer module corresponding to described interrupt source detects described interrupt source according to the result that set occurs in the interruption status position of described interrupt source and interrupts.
In conjunction with the first possible implementation of first aspect, in the 4th kind of possible implementation, high 16 of the data field of interrupt number corresponding for described upper layer module write Message Transmission interrupt capabilities structure comprises by described upper layer module:
Described upper layer module is by field corresponding in high 16 of the data field of interrupt number corresponding for described upper layer module write Message Transmission interrupt capabilities structure.
Second aspect present invention provides a kind of method identifying interrupt source, comprising:
CPU receives the message high for data field 16 being incorporated into Message Transmission interruption that peripherals sends, and it is low 16 that described message also comprises data field;
Described CPU judges whether high 16 of the data field of described message is 0, and if not, described CPU identifies described peripherals according to low 16 of the data field of described message, identifies described interrupt source according to high 16 of the data field of described message.
In conjunction with second aspect, in the implementation that the first is possible, according to high 16 of the data field of described message, described CPU identifies that interrupt source comprises:
Described CPU, according to the interrupt number of interrupt number corresponding to described interrupt source or upper layer module corresponding to described interrupt source, identifies described interrupt source.
Third aspect present invention provides a kind of device identifying interrupt source, comprising:
First writing unit, for when any one module of peripherals occurs to interrupt, by high 16 for the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, described peripherals comprises the module of multiple different levels;
Be incorporated into unit, for after described first writing unit is by high 16 of the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, high for described data field 16 are incorporated into the message that Message Transmission interrupts, it is low 16 that described message also comprises data field;
Transmitting element, for being incorporated into after unit to be incorporated into the message that Message Transmission interrupts by high for described data field 16 described, the described message be incorporated into is sent to CPU, to make described CPU identify described peripherals according to low 16 of the data field of described message, identify described interrupt source according to high 16 of the data field of described message.
In conjunction with the third aspect, in the implementation that the first is possible, also comprise:
Whether detecting unit, for after described first writing unit is by high 16 of the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, detects described interrupt source and interrupt;
Second writing unit, during for detecting described interrupt source generation interruption when described detecting unit, by high 16 for the data field of interrupt number corresponding for upper layer module corresponding for described interrupt source write Message Transmission interrupt capabilities structure.
In conjunction with the third aspect, in the implementation that the second is possible,
Described first writing unit, specifically for the field by correspondence in high 16 of the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, high 16 of described data field has multiple field, and the field that described data field is high 16 level corresponding with the module of described peripherals becomes corresponding relation.
In conjunction with the first possible implementation of the third aspect, in the implementation that the third is possible,
Described detecting unit, the result specifically for there is set according to the interruption status position of described interrupt source detects described interrupt source and interrupts.
In conjunction with the first possible implementation of the third aspect, in the 4th kind of possible implementation,
Described second writing unit, specifically for the field by correspondence in high 16 of the data field of interrupt number corresponding for described upper layer module write Message Transmission interrupt capabilities structure.
Fourth aspect present invention provides a kind of device identifying interrupt source, comprising:
Receiving element, for receiving the message high for data field 16 being incorporated into Message Transmission interruption that peripherals sends, it is low 16 that described message also comprises data field;
Judging unit, for receive at described receiving element that peripherals sends by data field high 16 be incorporated into the message that Message Transmission interrupts after, judge whether high 16 of the data field of described message is 0;
Recognition unit, for judge when described judging unit the data field of described message high 16 be not 0 time, according to the data field of described message low 16 identify described peripherals, according to the data field of described message high 16 identify described interrupt sources.
In conjunction with fourth aspect, in the implementation that the first is possible,
Described recognition unit, specifically for the interrupt number according to interrupt number corresponding to described interrupt source or upper layer module corresponding to described interrupt source, identifies described interrupt source.
Can find out, in the technical scheme of some embodiments of the invention, when any one module of peripherals occurs to interrupt, described module as interrupt source by high 16 for the data field of interrupt number corresponding for interrupt source write Message Transmission interrupt capabilities structure, described peripherals is incorporated into the message that Message Transmission interrupts by high for described data field 16, the described message be incorporated into is sent to central processor CPU by described peripherals, described peripherals is identified according to low 16 of the data field of described message to make described CPU, described interrupt source is identified according to high 16 of the data field of described message, apply above technical scheme, each interrupt source has corresponding interrupt number, make CPU completely without the need to inquiring about all interrupt status registers, directly identify interrupt source according to high 16 of the data field of message, reduce the expense of interruption delay and CPU.
Term " first ", " second ", " the 3rd " " 4th " etc. in instructions of the present invention and claims and above-mentioned accompanying drawing are for distinguishing different objects, instead of for describing particular order.In addition, term " comprises " and " having " and their any distortion, and intention is to cover not exclusive comprising.Such as contain the process of series of steps or unit, method, system, product or equipment and be not defined in the step or unit listed, but also comprise the step or unit do not listed alternatively, or also comprise alternatively for other intrinsic step of these processes, method, product or equipment or unit.
First introduce the method for the identification interrupt source that the embodiment of the present invention provides below, the application system of the embodiment of the present invention comprises: peripherals, bridge sheet, CPU, internal memory, wherein, interruptable controller is had in bridge sheet, some interruptable controllers can be integrated in CPU, and the executive agent of the identification interrupt source that the embodiment of the present invention provides is peripherals, this peripherals can be in computer system except CPU and main memory other any device, such as video card, network interface card etc.Wherein, this peripherals comprises the module of multiple different levels, such as ground floor secondary module, second layer secondary module, third layer secondary modules etc., second layer secondary module represents subordinate's module that each ground floor secondary module is corresponding, and third layer secondary module represents subordinate's module that each second layer secondary module is corresponding.Each level has corresponding interrupt status register, each interrupt status register is corresponding with these layer modules all with same upper layer module, for as described in Figure 3, all ground floor secondary modules share a first level interrupt status register, the all second layer secondary modules being subordinated to same ground floor secondary module share a second level interrupt status register, there are 5 the second level interrupt status registers (because ground floor secondary module has 5) in figure 3, the all third layer secondary modules being subordinated to each second layer secondary module share a third layer time interrupt status register, there is 8 third layer time interrupt status register (because the second layer secondary module being subordinated to same ground floor secondary module has 8) in figure 3.The message format that the Message Transmission that the embodiment of the present invention uses peripherals interrupts is expanded, more information can be carried, particularly embody the message of interrupt source hierarchical structure, be convenient to CPU Direct Recognition interrupt source, avoid the time delay that all interrupt status registers inquiring about peripherals bring.
Refer to Fig. 4, in the embodiment of the present invention, identify that an embodiment of the method for interrupt source comprises:
401, when any one module of peripherals occurs to interrupt, this module as interrupt source by high 16 for the data field of interrupt number corresponding for interrupt source write Message Transmission interrupt capabilities structure;
In embodiments of the present invention, peripherals comprises the module of multiple different levels, such as ground floor secondary module, second layer secondary module, third layer secondary module etc., when any one third layer secondary module occurs to interrupt as interrupt source, has corresponding interrupt number.
It should be noted that, it can be MSI that Message Transmission interrupts, and can be also MSI-X, be not specifically limited herein.
It should be noted that, the configuration space of peripherals be provided with specially Message Transmission interrupt ability structure be PCIe equipment configuration space in one group of register, form a data structure, this ability structure comprises multiple field, this field includes message addresses Message Address, message high address Message Upper Address and message data Message Data field, wherein Message Address and Message Upper Address field are all the destination addresses that peripherals sends that Message Transmission interrupts message, Message Transmission interrupts support two kinds of address widths, one is 32, another is 64, the many high 32 bit address Message Upper Address of the latter, Message Data is 32 bit data, define only low 16 in prior art, high 16 default be 0, and unlike the prior art, define not only low 16 in the embodiment of the present invention, also define high 16.
Such as: when any one third layer secondary module occurs to interrupt, the second layer secondary module that this third layer secondary module is corresponding and ground floor secondary module are respectively by high 16 for the data field of the interrupt number of correspondence write Message Transmission interrupt capabilities structure, wherein the span of high 16 of data field is 64K, three fields are divided into for high 16 of data field, such as 4-4-8 (first level the-the second level-third layer time), be equivalent to ground floor secondary module and have at most 16, the second layer secondary module of each ground floor secondary module subordinate has at most 16, the third layer secondary module of each second layer secondary module subordinate has at most 256.For the modules of the first level, each module has unique interrupt number, such as, when ground floor secondary module one produces and interrupts, ground floor secondary module one value 0001, ground floor secondary module two value 0010, ground floor secondary module three value 0011, after analogize, second layer secondary module, the obtaining value method of third layer secondary module corresponding field is similar.This hierarchical structure can not certainly be adopted, but only third layer secondary module unified interrupt number and be kept at the high 16 of Message Data field, but the hierarchy information of intermodule can be lost like this, be unfavorable for the optimization of interrupt processing.Such as in some cases, have no progeny when cpu identifies during the module of certain level produces, do not need the interruption identifying that subordinate's module produces, can directly make corresponding interrupt processing, need not continue to identify subordinate's module, thus improve interrupt processing efficiency.
402, peripherals is incorporated into the message that Message Transmission interrupts by high for data field 16;
In embodiments of the present invention, it is low 16 that this message also comprises data field, wherein data field low 16 for identifying peripherals, data field high 16 for identifying interrupt source.
Be understandable that, when certain third layer secondary module in peripherals occurs to interrupt, third layer secondary module, the second layer secondary module of third layer secondary module subordinate, the interrupt number of correspondence is write the corresponding field (hardware implementing) of above-mentioned high 16 by the ground floor secondary module of second layer secondary module subordinate respectively, in conjunction with low 16 bit data configured during software initialization and message addresses, be combined into the message that Message Transmission interrupts.
403, the message be incorporated into is sent to central processor CPU by peripherals, to make CPU identify peripherals according to low 16 of the data field of message, identifies interrupt source according to high 16 of the data field of message.
In embodiments of the present invention, if interruptable controller is not integrated in CPU, then the message be incorporated into is sent to the interruptable controller in bridge sheet by peripherals, then by bridge sheet by the message repeating that receives to CPU, perform interrupt handling routine to make CPU.
In the technical scheme of some embodiments of the invention, when any one module of peripherals occurs to interrupt, described module as interrupt source by high 16 for the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, described peripherals is incorporated into the message that Message Transmission interrupts by high for described data field 16, the described message be incorporated into is sent to central processor CPU by described peripherals, described peripherals is identified according to low 16 of the data field of described message to make described CPU, described interrupt source is identified according to high 16 of the data field of described message, apply above technical scheme, each interrupt source has corresponding interrupt number, make CPU completely without the need to inquiring about all interrupt status registers, directly identify interrupt source according to high 16 of the data field of message, reduce the expense of interruption delay and CPU.
Refer to Fig. 5, in the embodiment of the present invention, identify that another embodiment of the method for interrupt source comprises:
501, when any one module of peripherals occurs to interrupt, this module as interrupt source by high 16 for the data field of interrupt number corresponding for interrupt source write Message Transmission interrupt capabilities structure;
Optionally, described module is as the field of interrupt source by correspondence in high 16 of the data field of interrupt number corresponding for interrupt source write Message Transmission interrupt capabilities structure, high 16 of described data field has multiple field, and the field that described data field is high 16 level corresponding with the module of described peripherals becomes corresponding relation.
In embodiments of the present invention, peripherals comprises the module of multiple different levels, such as ground floor secondary module, second layer secondary module, third layer secondary module etc., any one third layer secondary module all likely occur interrupt and as interrupt source, wherein, any one interrupt source has corresponding interrupt number, and high 16 of data field has multiple field, and the field that described data field is high 16 level corresponding with the module of described peripherals becomes corresponding relation.
It should be noted that, it can be MSI that Message Transmission interrupts, and can be also MSI-X, be not specifically limited herein.
It should be noted that, the ability structure of Message Transmission interruption is provided with specially at the configuration space of peripherals, this ability structure comprises multiple field, this field includes Message Address, Message Upper Address and Message Data field, wherein Message Address and Message Upper Address field are all the destination addresses that peripherals sends that Message Transmission interrupts message, Message Transmission interrupts support two kinds of address widths, one is 32, another is 64, the many high 32 bit address Message Upper Address of the latter, Message Data is 32 bit data, define only low 16 in prior art, high 16 default be 0, and unlike the prior art, define not only low 16 in the embodiment of the present invention, also define high 16.
502, when the upper layer module that interrupt source is corresponding detects interrupt source generation interruption, upper layer module is by high 16 for the data field of interrupt number corresponding for upper layer module write Message Transmission interrupt capabilities structure;
Optionally, the upper layer module that described interrupt source is corresponding detects described interrupt source according to the result of the interruption status position generation set of described interrupt source and interrupts.
Optionally, described upper layer module is by field corresponding in high 16 of the data field of interrupt number corresponding for described upper layer module write Message Transmission interrupt capabilities structure.
In certain embodiments, when certain layer module produces interruption, there is set in the interruption status position of the correspondence in the interrupt status register belonging to it, such as when certain lower layer module occurs to interrupt, the interruption status position corresponding to upper layer module of it and it all can set, when third layer secondary module one occurs to interrupt, there is set in the interruption status position corresponding to third layer secondary module one in third layer time interrupt status register, because third layer secondary module one is subordinated to second layer secondary module one, also there is set in the interruption status position therefore corresponding to second layer secondary module one in the second level interrupt status register.In like manner, because second layer secondary module one is subordinated to ground floor secondary module one, also there is set in the interruption status position therefore corresponding to ground floor secondary module one in the first level interrupt status register.
503, peripherals is incorporated into the message that Message Transmission interrupts by high for data field 16;
In embodiments of the present invention, it is low 16 that message also comprises data field, wherein data field low 16 for identifying peripherals, data field high 16 for identifying interrupt source.
Be understandable that, when certain third layer secondary module in peripherals occurs to interrupt, third layer secondary module, the second layer secondary module of third layer secondary module subordinate, the interrupt number of correspondence is write above-mentioned data field high 16 (hardware implementing) by the ground floor secondary module of second layer secondary module subordinate respectively, in conjunction with the data field configured during software initialization low 16 and message addresses, be combined into the message that Message Transmission interrupts.
504, the message be incorporated into is sent to CPU by peripherals, to make CPU identify peripherals according to low 16 of the data field of message, identifies interrupt source according to high 16 of the data field of message.
In embodiments of the present invention, if interruptable controller is not integrated in CPU, then the message be incorporated into is sent to interruptable controller by peripherals, then by interruptable controller by the message repeating that enters to CPU, perform interrupt processing to make CPU.
In the technical scheme of some embodiments of the invention, when any one module of peripherals occurs to interrupt, described module is as the field of interrupt source by correspondence in high 16 of the data field of interrupt number corresponding for interrupt source write Message Transmission interrupt capabilities structure, when the upper layer module that described interrupt source is corresponding detects described interrupt source generation interruption, described upper layer module is by field corresponding in high 16 of the data field of interrupt number corresponding for upper layer module write Message Transmission interrupt capabilities structure, described peripherals is incorporated into the message that Message Transmission interrupts by high for described data field 16, the described message be incorporated into is sent to central processor CPU by described peripherals, described peripherals is identified according to low 16 of the data field of described message to make described CPU, described interrupt source is identified according to high 16 of the data field of described message, apply above technical scheme, high 16 of data field has multiple field, the field that described data field is high 16 level corresponding with the module of described peripherals becomes corresponding relation.Each interrupt source has corresponding interrupt number, makes CPU completely without the need to inquiring about all interrupt status registers, directly identifies interrupt source according to high 16 of the data field of message, reduces the expense of interruption delay and CPU.
On the basis of above-described embodiment, refer to Fig. 6, in the embodiment of the present invention, identify that another embodiment of the method for interrupt source comprises:
601, CPU receives the message high for data field 16 being incorporated into Message Transmission interruption that peripherals sends;
In embodiments of the present invention, it is low 16 that described message also comprises data field, wherein data field low 16 for identifying peripherals, data field high 16 for identifying interrupt source.
Be understandable that, such as when certain third layer secondary module in peripherals occurs to interrupt, third layer secondary module, the second layer secondary module of third layer secondary module subordinate, the interrupt number of correspondence is write above-mentioned data field high 16 (hardware implementing) by the ground floor secondary module of second layer secondary module subordinate respectively, in conjunction with the data field configured during software initialization low 16 and message addresses, be combined into the message that Message Transmission interrupts.
602, CPU judges whether high 16 of the data field of message is 0, if not, performs step 603;
In embodiments of the present invention, define only low 16 in prior art, high 16 default be 0, and unlike the prior art, define not only low 16 in the embodiment of the present invention, also define high 16.
It should be noted that, if high 16 of data field is 0, then adopt prior art identification interrupt source, the interrupt status register identification interrupt source that such as CPU is all according to inquiry, be not specifically limited herein.
603, CPU identifies peripherals according to low 16 of the data field of message, identifies interrupt source according to high 16 of the data field of message.
In embodiments of the present invention, CPU first identifies peripherals according to low 16 of the data field of message, after determining peripherals, identifies interrupt source further according to high 16 of the data field of message, be understandable that, interrupt source is a module of peripherals.
In the technical scheme of some embodiments of the invention, CPU receives the message high for data field 16 being incorporated into Message Transmission interruption that peripherals sends, and it is low 16 that described message also comprises data field; CPU judges whether high 16 of the data field of described message is 0, if not, described CPU identifies described peripherals according to low 16 of the data field of described message, described interrupt source is identified according to high 16 of the data field of described message, apply above technical scheme, each interrupt source has corresponding interrupt number, and CPU is completely without the need to inquiring about all interrupt status registers, directly identify interrupt source according to high 16 of the data field of message, reduce the expense of interruption delay and CPU.
Refer to Fig. 7, in the embodiment of the present invention, identify that another embodiment of the method for interrupt source comprises:
701, CPU receives the message high for data field 16 being incorporated into Message Transmission interruption that peripherals sends;
In embodiments of the present invention, it is low 16 that described message also comprises data field, wherein data field low 16 for identifying peripherals, data field high 16 for identifying interrupt source.
Be understandable that, such as when certain third layer secondary module in peripherals occurs to interrupt, third layer secondary module, the second layer secondary module of third layer secondary module subordinate, the interrupt number of correspondence is write above-mentioned data field high 16 (hardware implementing) by the ground floor secondary module of second layer secondary module subordinate respectively, in conjunction with the data field configured during software initialization low 16 and message addresses, be combined into the message that Message Transmission interrupts.
702, CPU judges whether high 16 of the data field of message is 0, if not, performs step 703;
In embodiments of the present invention, define only low 16 in prior art, high 16 default be 0, and unlike the prior art, define not only low 16 in the embodiment of the present invention, also define high 16.
It should be noted that, if high 16 of data field is 0, then adopt prior art identification interrupt source, such as, during CPU is all according to inquiry segment register identification interrupt source, is not specifically limited herein.
703, CPU identifies peripherals, the interrupt number identification interrupt source of the interrupt number corresponding according to interrupt source or upper layer module corresponding to interrupt source according to low 16 of the data field of message.
In embodiments of the present invention, CPU first identifies peripherals according to low 16 of the data field of message, again according to the interrupt number of interrupt number corresponding to interrupt source or upper layer module corresponding to interrupt source, identify interrupt source, be understandable that, interrupt source is a module of peripherals, and due to high 16 interrupt numbers including interrupt number corresponding to interrupt source or upper layer module corresponding to interrupt source of data field, then CPU is directly according to the interrupt number identification interrupt source of correspondence.
Be understandable that, when such as, in peripherals, ground floor secondary module one occurs to interrupt, the interrupt number identification interrupt source that CPU Direct Recognition interrupt source is corresponding.When such as, in peripherals, certain third layer secondary module occurs to interrupt, due to third layer secondary module, the second layer secondary module of third layer secondary module subordinate, the interrupt number of correspondence is write the corresponding field of above-mentioned high 16 by the ground floor secondary module of second layer secondary module subordinate respectively, then CPU first identifies the interrupt number that the ground floor secondary module of second layer secondary module subordinate is corresponding, identify the interrupt number that the second layer secondary module of third layer secondary module subordinate is corresponding again, finally identify the interrupt number of this third layer secondary module, identify interrupt source.
In the technical scheme of some embodiments of the invention, CPU receives the message high for data field 16 being incorporated into Message Transmission interruption that peripherals sends, and it is low 16 that described message also comprises data field; CPU judges whether high 16 of the data field of described message is 0, if not, described CPU identifies described peripherals according to low 16 of the data field of described message, the interrupt number identification interrupt source of the interrupt number corresponding according to interrupt source or upper layer module corresponding to interrupt source, apply above technical scheme, each interrupt source has corresponding interrupt number, CPU is completely without the need to inquiring about all interrupt status registers, directly according to the interrupt number identification interrupt source of interrupt number corresponding to interrupt source or upper layer module corresponding to interrupt source, reduce the expense of interruption delay and CPU.
For ease of better implementing the above-mentioned correlation technique of the embodiment of the present invention, be also provided for the relevant apparatus coordinating said method below.
Refer to Fig. 8, in the embodiment of the present invention, identify that an embodiment of the device 800 of interrupt source comprises:
First writing unit 801, for when any one module of peripherals occurs to interrupt, by high 16 for the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, described peripherals comprises the module of multiple different levels;
Be incorporated into unit 802, for after described first writing unit 801 is by high 16 of the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, high for described data field 16 are incorporated into the message that Message Transmission interrupts, it is low 16 that described message also comprises data field;
Transmitting element 803, for being incorporated into after unit 802 to be incorporated into the message that Message Transmission interrupts by high for described data field 16 described, the described message be incorporated into is sent to CPU, to make described CPU identify described peripherals according to low 16 of the data field of described message, identify described interrupt source according to high 16 of the data field of described message.
In the technical scheme of some embodiments of the invention, when any one module of peripherals occurs to interrupt, by high 16 for the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, the described message be incorporated into is sent to central processor CPU, described peripherals is identified according to low 16 of the data field of described message to make described CPU, described interrupt source is identified according to high 16 of the data field of described message, apply above technical scheme, each interrupt source has corresponding interrupt number, make CPU completely without the need to inquiring about all interrupt status registers, directly identify interrupt source according to high 16 of the data field of message, reduce the expense of interruption delay and CPU.
Refer to Fig. 9, in the embodiment of the present invention, identify that another embodiment of the device 900 of interrupt source comprises:
First writing unit 901, specifically for the field by correspondence in high 16 of the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, high 16 of described data field has multiple field, and the field that described data field is high 16 level corresponding with the module of described peripherals becomes corresponding relation;
Detecting unit 902, specifically for after described first writing unit 901 is by field corresponding in high 16 of the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, detects described interrupt source according to the result of the interruption status position generation set of described interrupt source and whether interrupt;
Second writing unit 903, during specifically for detecting described interrupt source generation interruption at described detecting unit 902, by field corresponding in high 16 of the data field of interrupt number corresponding for described upper layer module write Message Transmission interrupt capabilities structure;
Be incorporated into unit 904, for after the interrupt number of correspondence is write high 16 of the data field of Message Transmission interrupt capabilities structure by described first writing unit 901 and described second writing unit 903 respectively, high for described data field 16 are incorporated into the message that Message Transmission interrupts, it is low 16 that described message also comprises data field;
Transmitting element 905, for being incorporated into after unit 904 to be incorporated into the message that Message Transmission interrupts by high for described data field 16 described, the described message be incorporated into is sent to CPU, to make described CPU identify described peripherals according to low 16 of the data field of described message, identify described interrupt source according to high 16 of the data field of described message.
In certain embodiments, when certain layer module produces interruption, there is set in the interruption status position of the correspondence in the interrupt status register belonging to it, such as when certain lower layer module occurs to interrupt, the interruption status position corresponding to upper layer module of it and it all can set, when third layer secondary module one occurs to interrupt, there is set in the interruption status position corresponding to third layer secondary module one in third layer time interrupt status register, because third layer secondary module one is subordinated to second layer secondary module one, also there is set in the interruption status position therefore corresponding to second layer secondary module one in the second level interrupt status register.In like manner, because second layer secondary module one is subordinated to ground floor secondary module one, also there is set in the interruption status position therefore corresponding to ground floor secondary module one in the first level interrupt status register.
In the technical scheme of some embodiments of the invention, when any one module of peripherals occurs to interrupt, by field corresponding in high 16 of the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, when detecting described interrupt source and occurring to interrupt, by field corresponding in high 16 of the data field of interrupt number corresponding for upper layer module corresponding for described interrupt source write Message Transmission interrupt capabilities structure, high for described data field 16 are incorporated into the message that Message Transmission interrupts, the described message be incorporated into is sent to central processor CPU, described peripherals is identified according to low 16 of the data field of described message to make described CPU, described interrupt source is identified according to high 16 of the data field of described message, apply above technical scheme, each interrupt source has corresponding interrupt number, make CPU completely without the need to inquiring about all interrupt status registers, directly identify interrupt source according to high 16 of the data field of message, reduce the expense of interruption delay and CPU.
Refer to Figure 10, in the embodiment of the present invention, identify that another embodiment of the device 1000 of interrupt source comprises:
Receiving element 1001, for receiving the message high for data field 16 being incorporated into Message Transmission interruption that peripherals sends, it is low 16 that described message also comprises data field;
Judging unit 1002, for receive at described receiving element 1001 peripherals send by data field high 16 be incorporated into Message Transmission interrupt message after, judge whether high 16 of the data field of described message is 0;
Recognition unit 1003, for judge when described judging unit 1002 data field of described message high 16 be not 0 time, identify described peripherals according to low 16 of the data field of described message, identify described interrupt source according to high 16 of the data field of described message.
Optionally, recognition unit 1003, specifically for judge when described judging unit 1002 data field of described message high 16 be not 0 time, the interrupt number of the interrupt number corresponding according to described interrupt source or upper layer module corresponding to described interrupt source, identifies described interrupt source.
In the technical scheme of some embodiments of the invention, CPU receives the message high for data field 16 being incorporated into Message Transmission interruption that peripherals sends, and it is low 16 that described message also comprises data field; CPU judges whether high 16 of the data field of described message is 0, if not, described CPU identifies described peripherals according to low 16 of the data field of described message, described interrupt source is identified according to high 16 of the data field of described message, apply above technical scheme, each interrupt source has corresponding interrupt number, and CPU is completely without the need to inquiring about all interrupt status registers, directly identify interrupt source according to high 16 of the data field of message, reduce the expense of interruption delay and CPU.
Embodiment shown in Fig. 8 to Figure 10 from the angle of functional module to identifying that the concrete structure of interrupt source device is illustrated, below in conjunction with the embodiment of Figure 11 from hardware point of view to identifying that the concrete structure of interrupt source device is described:
Refer to Figure 11, a structural representation of the device 1100 of the identification interrupt source that Figure 11 provides for the embodiment of the present invention, wherein, at least one processor 1101 (such as CPU, Central Processing Unit), at least one network interface or other communication interface, storer 1102, at least one communication bus, at least one input media 1103, at least one output unit 1104 and uninterrupted power source UPS 1105 can be comprised for realizing the connection communication between these devices.The executable module of processor 1101 for storing in execute store 1102, such as computer program.Storer 1102 may comprise high-speed random access memory (RAM, Random Access Memory), still may comprise non-volatile storer (non-volatile memory), such as at least one magnetic disk memory.
As shown in figure 11, in some embodiments, store programmed instruction in storer 1102, programmed instruction can be performed by processor 1101, and processor 1101 specifically performs following steps:
When any one module of peripherals occurs to interrupt, by high 16 for the data field of the interrupt number of correspondence write Message Transmission interrupt capabilities structure, described peripherals comprises the module of multiple different levels;
High for described data field 16 are incorporated into the message that Message Transmission interrupts, it is low 16 that described message also comprises data field.
In certain embodiments, processor 1101 is also for performing following steps:
When the upper layer module that described interrupt source is corresponding detects described interrupt source generation interruption, by high 16 for the data field of the interrupt number of correspondence write Message Transmission interrupt capabilities structure;
It should be noted that, in the above-described embodiments, the description of each embodiment is all emphasized particularly on different fields in certain embodiment, there is no the part described in detail, can see the associated description of other embodiments.Such as, in the embodiment described in Figure 11, there is no the part described in detail, can see the associated description of the method for above-mentioned Fig. 4 to Figure 10 or device embodiment.
In sum, when any one module of peripherals occurs to interrupt, described module as interrupt source by high 16 for the data field of interrupt number corresponding for interrupt source write Message Transmission interrupt capabilities structure, described peripherals is incorporated into the message that Message Transmission interrupts by high for described data field 16, the described message be incorporated into is sent to central processor CPU by described peripherals, described peripherals is identified according to low 16 of the data field of described message to make described CPU, described interrupt source is identified according to high 16 of the data field of described message, apply above technical scheme, each interrupt source has corresponding interrupt number, make CPU completely without the need to inquiring about all interrupt status registers, directly identify interrupt source according to high 16 of the data field of message, reduce the expense of interruption delay and CPU.
Those skilled in the art can be well understood to, and for convenience and simplicity of description, the system of foregoing description, the specific works process of device and unit, with reference to the corresponding process in preceding method embodiment, can not repeat them here.
In several embodiments that the application provides, should be understood that, disclosed system, apparatus and method, can realize by another way.Such as, device embodiment described above is only schematic, such as, the division of described unit, be only a kind of logic function to divide, actual can have other dividing mode when realizing, such as multiple unit or assembly can in conjunction with or another system can be integrated into, or some features can be ignored, or do not perform.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be by some interfaces, and the indirect coupling of device or unit or communication connection can be electrical, machinery or other form.
The described unit illustrated as separating component or can may not be and physically separates, and the parts as unit display can be or may not be physical location, namely can be positioned at a place, or also can be distributed in multiple network element.Some or all of unit wherein can be selected according to the actual needs to realize the object of the present embodiment scheme.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, also can be that the independent physics of unit exists, also can two or more unit in a unit integrated.Above-mentioned integrated unit both can adopt the form of hardware to realize, and the form of SFU software functional unit also can be adopted to realize.
If described integrated unit using the form of SFU software functional unit realize and as independently production marketing or use time, can be stored in a computer read/write memory medium.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words or all or part of of this technical scheme can embody with the form of software product, this computer software product is stored in a storage medium, comprising some instructions in order to make a computer equipment (can be personal computer, server, or the network equipment etc.) perform all or part of step of method described in each embodiment of the present invention.And aforesaid storage medium comprises: USB flash disk, portable hard drive, ROM (read-only memory) (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. various can be program code stored medium.
The above, above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Accompanying drawing explanation
Fig. 1 is a structural representation of the method identifying interrupt source in prior art;
Fig. 2 is another structural representation of the method identifying interrupt source in prior art;
Fig. 3 is a structural representation of the method identifying interrupt source in the embodiment of the present invention;
Fig. 4 is an embodiment schematic diagram of the method identifying interrupt source in the embodiment of the present invention;
Fig. 5 is another embodiment schematic diagram of the method identifying interrupt source in the embodiment of the present invention;
Fig. 6 is another embodiment schematic diagram of the method identifying interrupt source in the embodiment of the present invention;
Fig. 7 is another embodiment schematic diagram of the method identifying interrupt source in the embodiment of the present invention;
Fig. 8 is an embodiment schematic diagram of the device identifying interrupt source in the embodiment of the present invention;
Fig. 9 is another embodiment schematic diagram of the device identifying interrupt source in the embodiment of the present invention;
Figure 10 is another embodiment schematic diagram of the device identifying interrupt source in the embodiment of the present invention;
Figure 11 is a structural representation of the device identifying interrupt source in the embodiment of the present invention.
Embodiment
Embodiments provide a kind of method and the device that identify interrupt source, for solving in prior art the problem identified existing for interrupt source.
Claims (14)
1. identify a method for interrupt source, it is characterized in that, comprising:
When any one module of peripherals occurs to interrupt, described module is as interrupt source by high 16 for the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, and described peripherals comprises the module of multiple different levels;
Described peripherals is incorporated into the message that Message Transmission interrupts by high for described data field 16, it is low 16 that described message also comprises data field;
The described message be incorporated into is sent to central processor CPU by described peripherals, to make described CPU identify described peripherals according to low 16 of the data field of described message, identifies described interrupt source according to high 16 of the data field of described message.
2. method according to claim 1, is characterized in that, described method also comprises:
When the upper layer module that described interrupt source is corresponding detects described interrupt source generation interruption, described upper layer module is by high 16 for the data field of interrupt number corresponding for described upper layer module write Message Transmission interrupt capabilities structure.
3. method according to claim 1, is characterized in that, described module comprises as high 16 of the data field of interrupt source by interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure:
Described module is as the field of interrupt source by correspondence in high 16 of the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, high 16 of described data field has multiple field, and the field that described data field is high 16 level corresponding with the module of described peripherals becomes corresponding relation.
4. method according to claim 2, is characterized in that, upper layer module corresponding to described interrupt source detects described interrupt source generation interruption and comprise:
Upper layer module corresponding to described interrupt source detects described interrupt source according to the result that set occurs in the interruption status position of described interrupt source and interrupts.
5. method according to claim 2, is characterized in that, high 16 of the data field of interrupt number corresponding for described upper layer module write Message Transmission interrupt capabilities structure comprises by described upper layer module:
Described upper layer module is by field corresponding in high 16 of the data field of interrupt number corresponding for described upper layer module write Message Transmission interrupt capabilities structure.
6. identify a method for interrupt source, it is characterized in that, comprising:
CPU receives the message high for data field 16 being incorporated into Message Transmission interruption that peripherals sends, and it is low 16 that described message also comprises data field;
Described CPU judges whether high 16 of the data field of described message is 0, and if not, described CPU identifies described peripherals according to low 16 of the data field of described message, identifies described interrupt source according to high 16 of the data field of described message.
7. method according to claim 6, is characterized in that, according to high 16 of the data field of described message, described CPU identifies that interrupt source comprises:
Described CPU, according to the interrupt number of interrupt number corresponding to described interrupt source or upper layer module corresponding to described interrupt source, identifies described interrupt source.
8. identify a device for interrupt source, it is characterized in that, comprising:
First writing unit, for when any one module of peripherals occurs to interrupt, by high 16 for the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, described peripherals comprises the module of multiple different levels;
Be incorporated into unit, for after described first writing unit is by high 16 of the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, high for described data field 16 are incorporated into the message that Message Transmission interrupts, it is low 16 that described message also comprises data field;
Transmitting element, for being incorporated into after unit to be incorporated into the message that Message Transmission interrupts by high for described data field 16 described, the described message be incorporated into is sent to CPU, to make described CPU identify described peripherals according to low 16 of the data field of described message, identify described interrupt source according to high 16 of the data field of described message.
9. device according to claim 8, is characterized in that, also comprises:
Whether detecting unit, for after described first writing unit is by high 16 of the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, detects described interrupt source and interrupt;
Second writing unit, during for detecting described interrupt source generation interruption when described detecting unit, by high 16 for the data field of interrupt number corresponding for upper layer module corresponding for described interrupt source write Message Transmission interrupt capabilities structure.
10. device according to claim 8, is characterized in that,
Described first writing unit, specifically for the field by correspondence in high 16 of the data field of interrupt number corresponding for described interrupt source write Message Transmission interrupt capabilities structure, high 16 of described data field has multiple field, and the field that described data field is high 16 level corresponding with the module of described peripherals becomes corresponding relation.
11. devices according to claim 9, is characterized in that,
Described detecting unit, the result specifically for there is set according to the interruption status position of described interrupt source detects described interrupt source and interrupts.
12. devices according to claim 9, is characterized in that,
Described second writing unit, specifically for the field by correspondence in high 16 of the data field of interrupt number corresponding for described upper layer module write Message Transmission interrupt capabilities structure.
13. 1 kinds of devices identifying interrupt source, is characterized in that, comprising:
Receiving element, for receiving the message high for data field 16 being incorporated into Message Transmission interruption that peripherals sends, it is low 16 that described message also comprises data field;
Judging unit, for receive at described receiving element that peripherals sends by data field high 16 be incorporated into the message that Message Transmission interrupts after, judge whether high 16 of the data field of described message is 0;
Recognition unit, for judge when described judging unit the data field of described message high 16 be not 0 time, according to the data field of described message low 16 identify described peripherals, according to the data field of described message high 16 identify described interrupt sources.
14. devices according to claim 13, is characterized in that,
Described recognition unit, specifically for the interrupt number according to interrupt number corresponding to described interrupt source or upper layer module corresponding to described interrupt source, identifies described interrupt source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410797967.7A CN104679687B (en) | 2014-12-19 | 2014-12-19 | A kind of method and device for identifying interrupt source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410797967.7A CN104679687B (en) | 2014-12-19 | 2014-12-19 | A kind of method and device for identifying interrupt source |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104679687A true CN104679687A (en) | 2015-06-03 |
| CN104679687B CN104679687B (en) | 2018-04-20 |
Family
ID=53314760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410797967.7A Active CN104679687B (en) | 2014-12-19 | 2014-12-19 | A kind of method and device for identifying interrupt source |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104679687B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107025132A (en) * | 2016-02-02 | 2017-08-08 | 龙芯中科技术有限公司 | Interrupt collocation method and device |
| WO2019128575A1 (en) * | 2017-12-28 | 2019-07-04 | 中兴通讯股份有限公司 | Interrupt processing method and interrupt processing device |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060242332A1 (en) * | 2005-04-22 | 2006-10-26 | Johnsen Bjorn D | Distributed I/O bridging functionality |
| US7328296B1 (en) * | 2006-01-03 | 2008-02-05 | Emc Corporation | Interrupt processing system |
| CN101211323A (en) * | 2006-12-28 | 2008-07-02 | 联想(北京)有限公司 | Hardware interruption processing method and processing unit |
| CN101739369A (en) * | 2008-11-13 | 2010-06-16 | 索尼株式会社 | Interrupt detection apparatus and information processing system |
| CN101872330A (en) * | 2009-11-04 | 2010-10-27 | 杭州海康威视数字技术股份有限公司 | Interrupt processing method of multi-PCIE (Peripheral Component Interface Express) equipment system |
| US20120036304A1 (en) * | 2010-08-04 | 2012-02-09 | International Business Machines Corporation | Injection of i/o messages |
| CN103019848A (en) * | 2012-12-25 | 2013-04-03 | 北京航天测控技术有限公司 | Method for realizing peripheral component interconnect (PCI) bus non-vector interrupt |
| US20130159581A1 (en) * | 2011-12-19 | 2013-06-20 | Advanced Micro Devices, Inc. | Method and apparatus for remapping interrupt types |
| CN103440188A (en) * | 2013-08-29 | 2013-12-11 | 福建星网锐捷网络有限公司 | Method and device for detecting PCIE hardware faults |
| US20140223059A1 (en) * | 2013-02-04 | 2014-08-07 | Bryan D. Marietta | Write Transaction Interpretation for Interrupt Assertion |
-
2014
- 2014-12-19 CN CN201410797967.7A patent/CN104679687B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060242332A1 (en) * | 2005-04-22 | 2006-10-26 | Johnsen Bjorn D | Distributed I/O bridging functionality |
| US7328296B1 (en) * | 2006-01-03 | 2008-02-05 | Emc Corporation | Interrupt processing system |
| CN101211323A (en) * | 2006-12-28 | 2008-07-02 | 联想(北京)有限公司 | Hardware interruption processing method and processing unit |
| CN101739369A (en) * | 2008-11-13 | 2010-06-16 | 索尼株式会社 | Interrupt detection apparatus and information processing system |
| CN101872330A (en) * | 2009-11-04 | 2010-10-27 | 杭州海康威视数字技术股份有限公司 | Interrupt processing method of multi-PCIE (Peripheral Component Interface Express) equipment system |
| US20120036304A1 (en) * | 2010-08-04 | 2012-02-09 | International Business Machines Corporation | Injection of i/o messages |
| US20130159581A1 (en) * | 2011-12-19 | 2013-06-20 | Advanced Micro Devices, Inc. | Method and apparatus for remapping interrupt types |
| CN103019848A (en) * | 2012-12-25 | 2013-04-03 | 北京航天测控技术有限公司 | Method for realizing peripheral component interconnect (PCI) bus non-vector interrupt |
| US20140223059A1 (en) * | 2013-02-04 | 2014-08-07 | Bryan D. Marietta | Write Transaction Interpretation for Interrupt Assertion |
| CN103440188A (en) * | 2013-08-29 | 2013-12-11 | 福建星网锐捷网络有限公司 | Method and device for detecting PCIE hardware faults |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107025132A (en) * | 2016-02-02 | 2017-08-08 | 龙芯中科技术有限公司 | Interrupt collocation method and device |
| CN107025132B (en) * | 2016-02-02 | 2020-03-13 | 龙芯中科技术有限公司 | Interrupt configuration method and device |
| WO2019128575A1 (en) * | 2017-12-28 | 2019-07-04 | 中兴通讯股份有限公司 | Interrupt processing method and interrupt processing device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104679687B (en) | 2018-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102866971B (en) | Device, the system and method for transmission data | |
| US20120271978A1 (en) | Resource Sharing Expansion Card | |
| US20140164666A1 (en) | Server and method for sharing peripheral component interconnect express interface | |
| US10372639B2 (en) | System and method to avoid SMBus address conflicts via a baseboard management controller | |
| CN113868173A (en) | Flat port bridge | |
| CN104636186A (en) | Virtual machine memory management method, physical host, PCIE equipment, configuration method thereof and migration management equipment | |
| CN104850502A (en) | Method, apparatus and device for accessing data | |
| US20140149617A1 (en) | I2c bus structure and device availability query method | |
| CN104571956A (en) | Data writing method and splitting device | |
| CN105404596A (en) | Data transmission method, device and system | |
| KR20210000648A (en) | Method, apparatus, electronic device and computer readable storage medium for supporting communication among chips | |
| CN104123173A (en) | Method and device for achieving communication between virtual machines | |
| CN104679687A (en) | Method and device for recognizing interruption source | |
| CN105334907A (en) | Clock synchronization method and data processing system | |
| CN111753562B (en) | Label identification method, device, electronic equipment and readable medium | |
| CN102393838A (en) | Data processing method and device, PCI-E (peripheral component interface-express) bus system, and server | |
| US20150195236A1 (en) | Techniques for implementing a secure mailbox in resource-constrained embedded systems | |
| US9952979B1 (en) | Methods and systems for direct memory access operations | |
| EP2942714B1 (en) | Monitoring method, monitoring apparatus, and electronic device | |
| CN104346234A (en) | Memory access method, equipment and system | |
| CN104834644A (en) | Self-search storage apparatus | |
| CN110532150A (en) | A kind of shelf management method, apparatus, storage medium and processor | |
| CN103488505A (en) | Patching method, device and system | |
| CN114238183A (en) | Systems, methods, and media for implementing Virtio devices | |
| CN105335228A (en) | Memory change processing method and operating systems |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200421 Address after: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee after: HUAWEI TECHNOLOGIES Co.,Ltd. Address before: 301, A building, room 3, building 301, foreshore Road, No. 310052, Binjiang District, Zhejiang, Hangzhou Patentee before: Huawei Technologies Co.,Ltd. |