CN107025063B - Memory management method, memory storage device and memory control circuit unit - Google Patents

Abstract

The invention provides a memory management method, a memory storage device and a memory control circuit unit. The method comprises the following steps: receiving first data; detecting the total number of the first type entity erasing units which do not store valid data; and if the total number is smaller than a first critical value, executing a first program. The first program includes: receiving second data from the rewritable nonvolatile memory module; temporarily storing the first data and the second data; a write rule is dynamically determined according to a storage state of the rewritable non-volatile memory module and first data and second data are stored to the rewritable non-volatile memory module according to the determined write rule. The invention can ensure that the writing speed of the rewritable nonvolatile memory module corresponding to the first data in the first program is more stable.

Description

Memory management method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to memory technologies, and in particular, to a memory management method, a memory storage device, and a memory control circuit unit.

Background

Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure and the like, the rewritable non-volatile memory module is very suitable for being built in various portable multimedia devices.

Generally, normally used physical blocks and spare (spare) physical blocks are allocated in the rewritable nonvolatile memory device. When storing data from the host system, the data is stored to the free physical block. The spare physical blocks storing data from the host system are changed to the normal physical blocks. When data in a normally used physical block is deleted by the host system, the physical block is erased and changed into an idle physical block.

In order to enable the rewritable and non-volatile memory device to operate normally, the total number of idle physical blocks in the rewritable and non-volatile memory device is usually maintained to be greater than a preset number. If the total number of the idle physical blocks is less than the predetermined number, a garbage collection (garbage collection) procedure is performed. In the garbage collection procedure, the valid data scattered in the rewritable nonvolatile memory device is collected and concentrated back to the rewritable nonvolatile memory device to release a new free physical block.

In the garbage collection procedure, if the host system continuously stores data, the rewritable nonvolatile memory device may store the data from the host system while executing the garbage collection procedure, or suspend storing the data from the host system to speed up the execution of the garbage collection procedure. However, whether the data from the host system is stored together with the execution of the garbage collection program or the storage of the data from the host system is suspended first when the garbage collection program is executed, the write speed of the rewritable nonvolatile memory device to the data from the host system is in an unpredictable state. For example, at a certain point in time, the write speed of the rewritable non-volatile memory device for data from the host system may be full speed; at the next point in time, the rewritable non-volatile memory device may stop storing data from the host system completely in order to execute the garbage collection process.

Disclosure of Invention

The invention provides a memory management method, a memory storage device and a memory control circuit unit, which can enable the writing speed of a rewritable nonvolatile memory module to be in a stable state.

An exemplary embodiment of the present invention provides a memory management method for a rewritable nonvolatile memory module, where the rewritable nonvolatile memory module includes a plurality of physical erase units, the memory management method including: receiving first data; detecting a total number of first type of physically erased cells in the physically erased cells, wherein each of the first type of physically erased cells in the physically erased cells does not store valid data; if the total number of the first kind of entity erasing units is less than a first critical value, executing a first program; and stopping the first procedure if the total number of first type entity erased units is greater than a second threshold, wherein the second threshold is greater than the first threshold, wherein the first procedure comprises: receiving second data from the rewritable nonvolatile memory module; temporarily storing the first data and the second data; and dynamically determining a write rule according to the storage state of the entity erasing unit and storing the first data and the second data to the rewritable nonvolatile memory module according to the write rule, so that the write speed of the rewritable nonvolatile memory module corresponding to the first data in the first program is not lower than a default value.

In an exemplary embodiment of the invention, the step of dynamically determining the write rule according to the storage status of the physically erased cells and storing the first data and the second data to the rewritable non-volatile memory module according to the write rule comprises: determining a first writing proportion value according to a first storage state of the entity erasing unit; storing a first part of the first data and a first part of the second data to the rewritable non-volatile memory module according to the first write proportion value, wherein the proportion of the data amount of the first part of the first data to the data amount of the first part of the second data conforms to the first write proportion value; determining a second write ratio value according to a second storage status of the physically erased unit after storing the first portion of the first data and the first portion of the second data in the rewritable non-volatile memory module, wherein the first write ratio value is different from the second write ratio value; and storing a second part of the first data and a second part of the second data to the rewritable non-volatile memory module according to the second write proportion value, wherein the proportion of the data amount of the second part of the first data to the data amount of the second part of the second data conforms to the second write proportion value.

In an exemplary embodiment of the present invention, the total number of the first type of physical units is changed from a first number to a second number in the first procedure, wherein the second number is greater than the first number, wherein the step of dynamically determining the write rule according to the storage status of the physically erased units comprises: determining a write proportion value corresponding to a proportion of the first data and the second data stored to the rewritable non-volatile memory module in the first program according to the second number, wherein the write proportion value is positively correlated with the second number.

In an exemplary embodiment of the present invention, the step of determining the write ratio value according to the second number comprises: determining the write ratio value according to the first threshold, the second number and a first reference value, wherein the first reference value corresponds to a storage condition of valid data in the physically erased cells when the first program is determined to be stopped.

In an exemplary embodiment of the present invention, the second data is data read from a first physically erased cell belonging to a second type of physically erased cells among the physically erased cells, and the step of dynamically determining the writing rule according to the storage status of the physically erased cells includes: obtaining a difference between a first reference value and a second reference value, wherein the first reference value corresponds to a storage condition of valid data in the physically erased cells when it is determined to stop the first process, and wherein the second reference value corresponds to a storage condition of valid data in the first physically erased cells; determining a second credit value based on the difference between the first reference value and the second reference value, wherein the difference between the first reference value and the second reference value is positively correlated to the second credit value; determining a first credit value according to the first reference value, the second reference value and the second credit value; and determining a write ratio value corresponding to a ratio of storing the first data and the second data to the rewritable non-volatile memory module in the first program according to the first reference value, the second reference value, the first credit value, and the second credit value, wherein the first credit value is positively correlated with the write ratio value, and wherein the second credit value is negatively correlated with the write ratio value.

In an exemplary embodiment of the invention, the first data is buffered in a first register, the second data is buffered in a second register, the dynamically determined write rule includes a write ratio value, and the step of storing the first data and the second data in the rewritable non-volatile memory module according to the write rule comprises: moving at least a part of the first data from the first buffer to a third buffer according to the writing proportion value; moving at least a part of the second data from the second buffer to the third buffer according to the writing proportion value, wherein the proportion of the data quantity of the part of the first data to the data quantity of the part of the second data conforms to the writing proportion value; and sequentially storing the data temporarily stored in the third buffer into the rewritable nonvolatile memory module.

Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for electrically connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity erasing units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module, wherein the memory control circuit unit is configured to receive first data from the host system, wherein the memory control circuit unit is further configured to detect a total number of first kind of physical erase units among the physical erase units, wherein each of the physical erase units belonging to the first kind of physical erase units does not store valid data, wherein the memory control circuit unit is further configured to instruct to execute a first program if the total number of the first kind of physical erase units is smaller than a first threshold, wherein the memory control circuit unit is further configured to instruct to stop the first program if the total number of the first kind of physical erase units is larger than a second threshold, wherein the second threshold is larger than the first threshold, wherein in the first program, the memory control circuit unit is further configured to: receiving second data from the rewritable nonvolatile memory module; temporarily storing the first data and the second data; and dynamically determining a write rule according to the storage state of the entity erasing unit and storing the first data and the second data to the rewritable nonvolatile memory module according to the write rule, so that the write speed of the rewritable nonvolatile memory module corresponding to the first data in the first program is not lower than a default value.

In an exemplary embodiment of the invention, the operation of the memory control circuit unit dynamically determining the write rule according to the storage status of the physically erased cell and storing the first data and the second data to the rewritable non-volatile memory module according to the write rule comprises: determining a first writing proportion value according to a first storage state of the entity erasing unit; storing a first part of the first data and a first part of the second data to the rewritable non-volatile memory module according to the first write proportion value, wherein the proportion of the data amount of the first part of the first data to the data amount of the first part of the second data conforms to the first write proportion value; determining a second write ratio value according to a second storage state of the physically erased unit after storing the first portion of the first data and the first portion of the second data in the rewritable non-volatile memory module, wherein the first write ratio value is different from the second write ratio value; and storing a second part of the first data and a second part of the second data to the rewritable non-volatile memory module according to the second write proportion value, wherein the proportion of the data amount of the second part of the first data to the data amount of the second part of the second data conforms to the second write proportion value.

In an exemplary embodiment of the present invention, the total number of the first type of physical units is changed from a first number to a second number in the first procedure, wherein the second number is greater than the first number, wherein the operation of the memory control circuit unit dynamically determining the write rule according to the storage status of the physical erase unit comprises: determining a write proportion value corresponding to a proportion of the first data and the second data stored to the rewritable non-volatile memory module in the first program according to the second number, wherein the write proportion value is positively correlated with the second number.

In an exemplary embodiment of the invention, the operation of the memory control circuit unit determining the write ratio value according to the second number includes: determining the write ratio value according to the first threshold, the second number and a first reference value, wherein the first reference value corresponds to a storage condition of valid data in the physically erased cells when the first program is determined to be stopped.

In an exemplary embodiment of the invention, the second data is data read from a first physically erased cell belonging to a second type of the physically erased cells, and the operation of the memory control circuit unit to dynamically determine the write rule according to the storage status of the physically erased cells comprises: obtaining a difference between a first reference value and a second reference value, wherein the first reference value corresponds to a storage condition of valid data in the physically erased cells when it is determined to stop the first process, and wherein the second reference value corresponds to a storage condition of valid data in the first physically erased cells; determining a second credit value based on the difference between the first reference value and the second reference value, wherein the difference between the first reference value and the second reference value is positively correlated to the second credit value; determining a first credit value according to the first reference value, the second reference value and the second credit value; and determining a write ratio value corresponding to a ratio of storing the first data and the second data to the rewritable non-volatile memory module in the first program according to the first reference value, the second reference value, the first credit value, and the second credit value, wherein the first credit value is positively correlated with the write ratio value, and wherein the second credit value is negatively correlated with the write ratio value.

In an exemplary embodiment of the invention, the operation of the memory control circuit unit storing the first data and the second data into the rewritable non-volatile memory module according to the write rule includes: moving at least a part of the first data from the first buffer to a third buffer of the memory control circuit unit according to the writing proportion value; moving at least a part of the second data from the second buffer to the third buffer according to the writing proportion value, wherein the proportion of the data quantity of the part of the first data to the data quantity of the part of the second data conforms to the writing proportion value; and sequentially storing the data temporarily stored in the third buffer into the rewritable nonvolatile memory module.

Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical erase units, and the memory control circuit unit includes a host interface, a memory interface, a buffer memory, and a memory management circuit. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface, the memory interface and the buffer memory, wherein the memory management circuit is configured to receive first data from the host system, wherein the memory management circuit is further configured to detect a total number of first kind of physically erased cells among the physically erased cells, wherein each of the physically erased cells belonging to the first kind of physically erased cells does not store valid data, wherein the memory management circuit is further configured to instruct to execute a first program if the total number of the first kind of physically erased cells is smaller than a first threshold, wherein the memory management circuit is further configured to instruct to stop the first program if the total number of first kind of physically erased cells is larger than a second threshold, wherein the second threshold is larger than the first threshold, wherein in the first program, the memory management circuit is further configured to: receiving second data from the rewritable nonvolatile memory module; temporarily storing the first data and the second data in the buffer memory; and dynamically determining a write rule according to the storage state of the entity erasing unit and storing the first data and the second data to the rewritable nonvolatile memory module according to the write rule, so that the write speed of the rewritable nonvolatile memory module corresponding to the first data in the first program is not lower than a default value.

In an exemplary embodiment of the invention, the first program is a data integration program for collecting valid data stored in the rewritable nonvolatile memory module.

In an exemplary embodiment of the invention, the operation of the memory management circuit dynamically determining the write rule according to the storage status of the physically erased cells and storing the first data and the second data to the rewritable non-volatile memory module according to the write rule comprises: determining a first writing proportion value according to a first storage state of the entity erasing unit; storing a first part of the first data and a first part of the second data to the rewritable non-volatile memory module according to the first write proportion value, wherein the proportion of the data amount of the first part of the first data to the data amount of the first part of the second data conforms to the first write proportion value; determining a second write ratio value according to a second storage state of the physically erased unit after storing the first portion of the first data and the first portion of the second data in the rewritable non-volatile memory module, wherein the first write ratio value is different from the second write ratio value; and storing a second part of the first data and a second part of the second data to the rewritable non-volatile memory module according to the second write proportion value, wherein the proportion of the data amount of the second part of the first data to the data amount of the second part of the second data conforms to the second write proportion value.

In an exemplary embodiment of the present invention, the total number of the first type of entity units is changed from a first number to a second number in the first program, wherein the second number is greater than the first number, wherein the operation of the memory management circuit dynamically determining the write rule according to the execution status of the first program comprises: determining a write proportion value corresponding to a proportion of the first data and the second data stored to the rewritable non-volatile memory module in the first program according to the second number, wherein the write proportion value is positively correlated with the second number.

In an exemplary embodiment of the invention, the operation of the memory management circuit determining the write ratio value according to the second number comprises: determining the write ratio value according to the first threshold, the second number and a first reference value, wherein the first reference value corresponds to a storage condition of valid data in the physically erased cells when the first program is determined to be stopped.

In an exemplary embodiment of the present invention, the second data is data read from a first physically erased cell belonging to a second type of the physically erased cells, and the operation of the memory management circuit to dynamically determine the write rule according to the storage status of the physically erased cells comprises: obtaining a difference between a first reference value and a second reference value, wherein the first reference value corresponds to a storage condition of valid data in the physically erased cells when it is determined to stop the first process, and wherein the second reference value corresponds to a storage condition of valid data in the first physically erased cells; determining a second credit value based on the difference between the first reference value and the second reference value, wherein the difference between the first reference value and the second reference value is positively correlated to the second credit value; determining a first credit value according to the first reference value, the second reference value and the second credit value; and determining a write ratio value corresponding to a ratio of storing the first data and the second data to the rewritable non-volatile memory module in the first program according to the first reference value, the second reference value, the first credit value, and the second credit value, wherein the first credit value is positively correlated with the write ratio value, and wherein the second credit value is negatively correlated with the write ratio value.

In an exemplary embodiment of the invention, the operation of the memory management circuit storing the first data and the second data in the rewritable non-volatile memory module according to the write rule comprises: moving at least a part of the first data from the first buffer to a third buffer of the buffer memory according to the writing proportion value; moving at least a part of the second data from the second buffer to the third buffer according to the writing proportion value, wherein the proportion of the data quantity of the part of the first data to the data quantity of the part of the second data conforms to the writing proportion value; and sequentially storing the data temporarily stored in the third buffer into the rewritable nonvolatile memory module.

In view of the above, in an exemplary embodiment of the invention, if the total number of the first kind of physically erased cells in the rewritable non-volatile memory module is smaller than a first threshold, the first procedure is executed. After the first program is started, a write rule is dynamically determined according to the storage state of the physical erase unit, and first data received from the host system and second data received from the rewritable nonvolatile memory module are stored to the rewritable nonvolatile memory module according to the write rule. Therefore, the writing speed of the rewritable nonvolatile memory module corresponding to the first data in the first program is stable.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention;

FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another exemplary embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram illustrating memory control circuitry in accordance with an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating a management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

FIG. 7 is a diagram illustrating storing of first data and second data according to a write rule according to an exemplary embodiment of the present invention;

FIGS. 8 and 9 are graphs of write speed of a typical memory storage device during a garbage collection process;

FIGS. 10 and 11 are graphs illustrating write speeds of a memory storage device according to an exemplary embodiment of the invention;

fig. 12 is a flowchart illustrating a memory management method according to an exemplary embodiment of the invention.

Reference numerals:

10: memory storage device

11. 31: host system

110: system bus

111: processor with a memory having a plurality of memory cells

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: main board

201: portable disc

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network adapter

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

32: SD card

33: CF card

34: embedded storage device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable non-volatile memory module

502: memory management circuit

504: host interface

506: memory interface

508: error checking and correcting circuit

510: buffer memory

512: power management circuit

601: idle zone

602: storage area

610 (610), (0) to 610(a), 610(a +1) to 610 (B): physical erase unit

612(0) -612 (C): logic unit

710. 720 and 730: buffer memory

701(0) to 701(D), 702(0) to 702(E), 703(0) to 703 (F): data area

801. 901, 1001, 1101: curve line

S1201 to S1208: step (ii) of

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with a host system so that the host system can write data to and read data from the memory storage device.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another exemplary embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the ram 112, the rom 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 can store data into the memory storage device 10 or read data from the memory storage device 10 through the data transmission interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the main board 20 can be electrically connected to the memory storage device 10 through a wired or wireless manner. The memory storage device 10 may be a flash Drive 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) based memory storage device based on various wireless communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network adapter 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system is any system that can substantially cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, a tablet computer, or the like, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, an embedded storage device 34, or the like. The embedded storage device 34 includes various types of embedded Multi-media cards (eMMC) 341 and/or embedded Multi-Chip Package (eMCP) storage devices 342, which electrically connect the memory module directly to the embedded storage device on the substrate of the host system.

Fig. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.

In the exemplary embodiment, connection interface unit 402 is compliant with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed MMC (UHS-I) interface standard, the Ultra High Speed II (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-Chip Package) interface standard, the multimedia Storage Card (Multi Media Card) interface, the flash Memory interface standard, the flash Memory (flash) interface standard, the flash Memory (MC) standard, the MC interface standard, The eMCP interface standard, the CF interface standard, an Integrated Device Electronics (IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged in one chip with the memory control circuit unit 404, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11. In the following exemplary embodiments, the operation of each circuit in the memory control circuit unit 404 is described as equivalent to the operation of the memory control circuit unit 404.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This process of changing the threshold voltage is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple storage states. By applying a read voltage, a memory cell can be determined to which storage state it belongs, thereby obtaining one or more bits stored in the memory cell.

Fig. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506 and a buffer memory 510.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations when the memory storage device 10 is in operation. The operation of the memory management circuit 502 is described below, which is equivalent to the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are recorded in the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 (for example, a system area dedicated to storing system data in the memory module) by using a program code type. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the ram of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The cell management circuit is used for managing the memory cells or the group of the rewritable nonvolatile memory module 406. The memory write-in circuit is configured to issue a write-in command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory reading circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or scripts and are used to instruct the rewritable nonvolatile memory module 406 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 502 may also issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is electrically connected to the memory management circuit 502 and is used for receiving and identifying commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with the PATA standard, the IEEE 1394 standard, the PCI express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the command sequences may include a write command sequence for indicating data to be written, a read command sequence for indicating data to be read, an erase command sequence for indicating data to be erased, and corresponding command sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include script or program code. For example, the read command sequence includes read identification codes, memory addresses, and the like.

The buffer memory 510 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.

In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508 and power management circuitry 512.

The error checking and correcting circuit 508 is electrically connected to the memory management circuit 502 and is used for performing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the corresponding error correction code and/or error check code of the data is simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting procedure on the read data according to the error correction code and/or error check code. The power management circuit 512 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.

FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. It should be understood that, in the following exemplary embodiments, the operation of the physical units of the rewritable nonvolatile memory module 406 is described, and it is a logical concept to operate the physical erase units by the words "select" and "group". That is, the physical locations of the physically erased cells of the rewritable nonvolatile memory module 406 are not changed, but the physically erased cells of the rewritable nonvolatile memory module 406 are logically operated.

In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 constitute a plurality of physical programming units, and the physical programming units constitute a plurality of physical erasing units. Specifically, memory cells on the same word line constitute one or more physical program cells. If each memory cell can store more than 2 bits, the on-line physical program units of the same word can be classified into at least a lower physical program unit and an upper physical program unit. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program unit, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical program unit. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., error correction codes). In the present exemplary embodiment, the data bit region includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, 8, 16 or more or less physical fans may be included in the data bit region, and the size of each physical fan may be larger or smaller. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).

Referring to FIG. 6, in the exemplary embodiment, the memory management circuit 502 initially groups the physical erase units 610(0) -610 (B) of the rewritable nonvolatile memory module 406 into an idle (spare) area 601 and a storage area 602. For example, the erase units 610(0) - (610A) belong to the idle area 601, and the erase units 610(A +1) - (610B) belong to the storage area 602. For example, the memory management circuit 502 may associate a physically erased cell with one of the idle area 601 and the storage area 602 by using a flag or the like. During the operation of the memory storage device 10, the relationship between a physically erased cell and the idle area 601 or the storage area 602 may change dynamically. For example, when receiving write data from the host system 11, the memory management circuit 502 selects a physical erase unit from the idle area 601 to store at least a portion of the write data and associates the physical erase unit with the storage area 602. In addition, after erasing a physical erase unit belonging to the storage area 602 to erase data therein, the memory management circuit 502 associates the erased physical erase unit with the idle area 601.

In the exemplary embodiment, each of the physically erased cells belonging to the idle area 601 is an erased physically erased cell and does not store any data, and each of the physically erased cells belonging to the storage area 602 stores data. In particular, each physical erase unit belonging to the idle area 601 may not store any valid (valid) data, and each physical erase unit belonging to the storage area 602 may store valid data and/or invalid (invalid) data.

In the exemplary embodiment, memory management circuitry 502 may configure logic 612(0) -612 (C) to map the physical erase units in storage area 602. Therefore, the total capacity of the physically erased cells 610(A +1) -800 (B) is considered to be the maximum available capacity of the rewritable nonvolatile memory module 406. In the present exemplary embodiment, the host system 11 accesses the data stored in the physically erased cells belonging to the storage area 602 by a Logical Address (LA); thus, each of logic units 612(0) -612 (C) refers to a logical address. However, in another exemplary embodiment, each of the logic units 612(0) -612 (C) can also refer to a logic program unit, a logic erase unit or consist of multiple continuous or discontinuous logic addresses. In addition, each of the logic units 612(0) -612 (C) may be mapped to one or more physical erase units.

In the present exemplary embodiment, the memory management circuit 502 records the mapping relationship (also referred to as logical-physical mapping relationship) between the logical units and the physical erase units in at least one logical-physical mapping table. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access to the memory storage device 10 according to the logical-physical mapping table.

In the exemplary embodiment, valid data is current data (or latest data) belonging to one logical unit, and invalid data is not current data belonging to any logical unit. For example, if the host system 11 stores a new data item in a logical unit to overwrite an old data item originally stored in the logical unit, the new data item stored in the storage area 602 is the current data belonging to the logical unit and is marked as valid data, and the overwritten old data item may still be stored in the storage area 601 but is marked as invalid data. In one exemplary embodiment, if the data belonging to a logical unit is updated, the mapping relationship between the logical unit and the physical erase unit storing the old data belonging to the logical unit is removed, and the mapping relationship between the logical unit and the physical erase unit storing the current data belonging to the logical unit is established. Alternatively, in another exemplary embodiment, if the data belonging to a logical unit is updated, the mapping relationship between the logical unit and the physically erased unit storing the old data belonging to the logical unit can still be maintained, depending on the actual requirements.

In the present exemplary embodiment, the physically erased cells belonging to the idle region 601 may also be referred to as first type of physically erased cells or idle physically erased cells, and the physically erased cells belonging to the storage region 602 may also be referred to as second type of physically erased cells or non-idle (non-spare) physically erased cells.

In the exemplary embodiment, the memory management circuit 502 receives data from the host system 11. For example, the data from the host system 11 is also referred to as the first data and is temporarily stored in the buffer memory 510. Then, the memory management circuit 502 attempts to store the first data in a physically erased cell of the rewritable nonvolatile memory module 406. For example, the physical erase unit for storing the first data is a physical erase unit selected from the idle area 601.

In the present exemplary embodiment, the memory management circuit 502 detects the total number of the first type of physically erased cells and determines whether the total number is smaller than a first threshold. For example, the first critical value is 2. If the total number of first type of physically erased cells is less than the first threshold, memory management circuit 502 performs a first procedure. For example, the first process is a data merging process for collecting valid data stored in the storage area 602. In an exemplary embodiment, the first process is also referred to as a garbage collection process. In the exemplary embodiment, the operation of detecting the total number of the first kind of physically erased cells and determining whether the total number is smaller than the first threshold value may be performed in response to a certain physically erased cell being extracted from the idle area 601 to the storage area 602 or continuously performed in the background (background).

In a first procedure, the memory management circuit 502 selects at least one physically erased cell from the storage area 602. The memory management circuit 502 instructs the rewritable nonvolatile memory module 406 to read valid data from the selected physical erase unit and temporarily store the collected valid data in the buffer memory 510. Then, the memory management circuit 502 will collectively store the valid data temporarily stored in the buffer memory 510 back to a certain physical erase unit in the rewritable nonvolatile memory module 406. For example, the physical erase unit used to store the collected valid data is also a physical erase unit selected from the idle region 601. However, the physical erase unit for storing data from the host system 11 and the physical erase unit for storing data from the rewritable non-volatile memory module 406 are not generally the same physical erase unit. By the processing of the first procedure, the valid data originally distributed in the storage area 602 is gradually and intensively stored. The physically erased cells in which the stored valid data are all moved can be erased and associated with the idle region 601. Therefore, after the first program is started, the total number of the physically erased cells belonging to the idle area 601 gradually increases and/or the total number of the physically erased cells belonging to the storage area 602 but storing invalid data gradually decreases.

In the exemplary embodiment, the process of changing a physical erase unit from the storage area 602 to the idle area 601 is also referred to as releasing an idle physical erase unit. During the first procedure to release the idle physical erase units, even if the host system 11 continuously instructs to store data to the memory storage device 10, the number of physical erase units associated with the idle area 601 gradually exceeds the number of physical erase units extracted to the storage area 602 for storing data (e.g., data from the host system 11 or valid data collected from the rewritable nonvolatile memory module 406).

Through the processing of the first procedure, if the memory management circuit 502 determines that the total number of the first type of physically erased cells is greater than a second threshold, the memory management circuit 502 stops the first procedure. Wherein the second threshold is greater than the first threshold. For example, the second critical value is 10. In addition, the first threshold and the second threshold may be other values, and the invention is not limited thereto.

In the present exemplary embodiment, the valid data received by the memory management circuit 502 from the rewritable nonvolatile memory module 406 in the first program is also referred to as the second data. In another exemplary embodiment, the second data may also include invalid data or padding data (dummy data) collected along with the valid data. After the first program is started, the first data from the host system 11 and the second data from the rewritable nonvolatile memory module 406 are temporarily stored in the buffer memory 510. The memory management circuit 502 dynamically determines a write rule according to the storage status of the physical erase units 610(0) - (610B) and instructs the first data and the second data to be stored in the rewritable nonvolatile memory module 406 according to the write rule. In an exemplary embodiment, the storage states of the physical erase units 610(0) -610 (B) are synchronized to reflect the current execution status of the first process.

In the exemplary embodiment, the write rule is used to limit a ratio of the first data and the second data stored in the rewritable nonvolatile memory module 406 within a predetermined data size range. For example, assuming that the default data size range is equal to the total data size of the K physical programming units, the write rule may define that the first data occupies the data size of the a physical programming units and the second data occupies the data size of the b physical programming units in the process of continuously storing the data of the K physical programming units to the rewritable nonvolatile memory module 406. Wherein a and b are positive integers, and the sum of a and b is equal to K. In an exemplary embodiment, the write rule includes a write ratio value. For example, this write ratio value is equal to a/b. Furthermore, the value of a may be inversely related to the value of b.

FIG. 7 is a diagram illustrating storing of first data and second data according to a write rule according to an exemplary embodiment of the invention.

Referring to fig. 7, it is assumed that data (i.e., first data) from the host system 11 is buffered in the buffer 710 of the buffer memory 510 and data (i.e., second data) from the rewritable nonvolatile memory module 406 is buffered in the buffer 720 of the buffer memory 510. Buffer 710 includes data regions 701(0) -701 (D) and buffer 720 includes data regions 702(0) -702 (E). The capacity of each of the data regions 701(0) to 701(D) and 702(0) to 702(E) is equal to the capacity of one physical program cell. According to the determined write rules, memory management circuit 502 moves data from a data areas in buffer 710 to register 730 in buffer 510 and moves data from b data areas in buffer 720 to register 730. Buffer 730 includes data region 703(0) -703 (F). The capacity of each of the data regions 703(0) to 703(F) is also equal to the capacity of one physical programming unit. The memory management circuit 502 sequentially stores the data temporarily stored in the register 730 to the rewritable nonvolatile memory module 406.

In the present exemplary embodiment, each of the registers 710, 720 and 730 can be regarded as an Input output Queue (IO Queue) and the data inputs and outputs of each of the registers 710, 720 and 730 conform to a First In First Out (FIFO) rule. Therefore, after K (K ═ a + b) data are continuously input into the register 730, the K data are also continuously output to the rewritable nonvolatile memory module 406. In the present exemplary embodiment, a data from the register 710 is first input into the register 730; then, the b data from the buffer 720 is input into the buffer 730. In another exemplary embodiment, b data from register 720 is first input into register 730; then, the a data from the buffer 710 is input into the buffer 730. Alternatively, in another exemplary embodiment, the a data from register 710 and the b data from register 720 may be alternately input to register 730.

In addition, in another exemplary embodiment of fig. 7, the data buffered in each of the data areas of the register 710, the register 720 and the register 730 may also include request information (request message) for storing the related data. For example, each request message may include data to be stored and a logical unit (or logical entity mapping relationship) to which the data belongs.

Conventionally, data from the host system and data collected by the garbage collection program are often randomly stored in the rewritable nonvolatile memory module, which results in that the writing speed of the rewritable nonvolatile memory module to the data of the host system in the garbage collection program is suddenly fast or slow. Alternatively, in some applications, it is also possible to use all write bandwidth (bandwidth) of the rewritable nonvolatile memory module for restoring the data collected by the garbage collector in order to shorten the running time for executing the garbage collector; storage of data from the host system is resumed after the garbage collection process is completed. However, such operations often result in the write speed of the rewritable non-volatile memory module to the data of the host system during the garbage collection process jumping significantly between zero and full speed.

In the present exemplary embodiment, the data (i.e., the first data and the second data) are stored in the rewritable nonvolatile memory module 406 according to the determined writing rule, and the bandwidth for storing the first data and/or the second data in the first program, the execution efficiency of the first program, and/or the runtime of the first program can be controlled accordingly, so that the writing speed of the rewritable nonvolatile memory module 406 corresponding to the first data in the first program can be maintained in a stable (stable) state. For example, in the example embodiment of fig. 7, every K data items stored in the rewritable nonvolatile memory module 406 include at least a data items from the host system 11. The a data is used to stabilize the writing speed/bandwidth for the data from the host system 11. For example, when the execution efficiency of the first program is better, the execution efficiency of the first program can be reduced and/or the running time of the first program can be prolonged by increasing the value of a and decreasing the value of b (which is equivalent to increasing a write ratio value). By reducing the execution efficiency of the first program and/or extending the running time of the first program, the storage bandwidth of the rewritable nonvolatile memory module 406 for the data (i.e., the first data) from the host system changes more stably (e.g., rises steadily) before the first program ends, thereby reducing the probability that the writing speed of the rewritable nonvolatile memory module 406 for the first data changes dramatically at the end of the first program.

In the exemplary embodiment, the write rule used during the execution of the first program is dynamically changed more than once. For example, in an exemplary embodiment, according to the first storage status of the current physical erase units 610(0) - (610B), the memory management circuit 502 determines a first write ratio value and instructs to store the first portion of the first data and the first portion of the second data to the rewritable nonvolatile memory module 406 according to the first write ratio value. The ratio of the data quantity of the first part of the first data to the data quantity of the first part of the second data is in accordance with the first writing ratio value. After storing the first portion of the first data and the first portion of the second data in the rewritable nonvolatile memory module 406, the storage states of the physical erase units 610(0) - (610B) may change, for example, from the first storage state to the second storage state. Therefore, the memory management circuit 502 determines the second write ratio value according to the second storage status of the current physical erase units 610(0) -610 (B). Wherein the first writing proportion value is different from the second writing proportion value. The memory management circuit 502 stores a second portion of the first data and a second portion of the second data to the rewritable nonvolatile memory module 406 according to the second write ratio value. The ratio of the data volume of the second part of the first data to the data volume of the second part of the second data is in accordance with the second writing ratio value.

In an exemplary embodiment, the memory management circuit 502 continuously detects the total number of the first type of physically erased cells and dynamically adjusts the write strategy according to the detected total number. For example, assuming that the memory management circuit 502 detects the total number of the first kind of physically erased cells as a first number earlier and determines to use the first write ratio value according to the first number, the memory management circuit 502 adjusts the first write ratio value to the second write ratio value according to the second number after the total number of the first kind of physically erased cells changes (e.g., changes from the first number to a second number greater than the first number) based on the execution of the first program. Wherein the first number positively correlates to the first write ratio value and the second number positively correlates to the second write ratio value.

In an exemplary embodiment, the memory management circuit 502 determines the write ratio value to be used according to the first threshold, the second threshold, the total number of the first type of physically erased cells and a reference value (hereinafter also referred to as a first reference value). The first reference value corresponds to a storage condition of valid data in the rewritable nonvolatile memory module 406 when it is determined that the first program can be stopped. For example, in an exemplary embodiment, the first reference value is used to indicate that the plurality of physically erased cells belonging to the storage area 602 includes several physically programmed cells storing valid data on average when the total number of physically erased cells belonging to the idle area 601 is greater than the second threshold. For example, in an exemplary embodiment, the memory management circuit 502 may determine the write ratio value according to the following procedures (1) - (3):

wherein, V_mIs a first reference value; NxP is used to indicate how many physical program cells are needed to store all valid data in the rewritable nonvolatile memory module 406, wherein N is used to indicate how many physical erase cells are needed to store all valid data in the rewritable nonvolatile memory module 406, and P is used to indicate how many physical program cells each physical erase cell contains；(N+M-G_H) Indicates the total number of the physically erased cells (i.e., the physically erased cells belonging to the storage area 602) that have stored data in the rewritable nonvolatile memory module 406 when the first program is stopped, wherein M indicates the total number of the physically erased cells initially allocated in the idle area 601, and G indicates the total number of the physically erased cells initially allocated in the idle area 601_HIs a second critical value; v_GA physical programming unit for indicating that the collected data is required to be written into several second type data in order to increase the total number of the first type physical erase units by a predetermined number (e.g., 1) in the first procedure; r_SIs a write ratio value; f is the total number of the first type entity erasing units; g_LIs the first critical value.

According to equations (1) - (3), if the current first procedure releases more idle physically erased cells, R_SWill increase; if the idle physical erase unit released by the current first program is less, R_SWill be reduced. If R is_SIncreasing, the value of a in the exemplary embodiment of FIG. 7 would correspondingly increase and the value of b would correspondingly decrease; if R is_SDecreasing, the value of a in fig. 7 will correspondingly decrease and the value of b will correspondingly increase.

In an exemplary embodiment, the memory management circuit 502 obtains a difference between the first reference value and a second reference value, wherein the second reference value corresponds to a storage condition of valid data in a specific physically erased cell (hereinafter also referred to as the first physically erased cell). For example, the first physically erased cell is the physically erased cell in the storage area 601 that is currently selected to collect the valid data (i.e., at least a portion of the second data), and the second reference value can be used to represent the number of physically erased cells in the first physically erased cell that store the valid data. The memory management circuit 502 determines a second credit value according to the difference between the first reference value and the second reference value. Wherein the difference between the first reference value and the second reference value positively correlates to the second credit value. The memory management circuit 502 determines a first credit value according to the first reference value, the second reference value and the second credit value. The memory management circuit 502 determines the write ratio value according to the first reference value, the second reference value, the first credit value and the second credit value. The first credit value is positively correlated to the write ratio value, and the second credit value is negatively correlated to the write ratio value.

For example, in an exemplary embodiment, the memory management circuit 502 may determine the write ratio value according to the following procedures (4) - (8):

C_G＝V_m-V…(4)

E_G＝f_G×C_G…(5)

E_H＝min(f_H×C_H,P)…(6)

wherein V is a second reference value; c_GIs a first reference value V_mA difference from a second reference value V; e_GIs the second credit value; e_HIs a first credit value; c_HFor calculating a first credit value E_HA transition value of (d); and f_GAnd f_HIs a constant number, where 0<f _G1 or less and 0 or less f_H<1。

According to equations (4) to (8), the first credit value E_HIs used to increase the amount of data (i.e., the value a in FIG. 7) subsequently written to the first data, and the second credit value E_GIt is to reduce the amount of data to be subsequently written to the first data.

In an exemplary embodiment, the memory management circuit 502 additionally determines a third threshold. The third threshold is between the first threshold and the second threshold. After the first program is started, the memory management circuit 502 determines whether the total number of the first type of physically erased cells is less than or equal to the third threshold. If the total number of first type entity erasing units is less than or equal to the third threshold value, the memory management circuit 502 will convert the transition value C_HSet to an initial value, e.g., 0. However, the device is not suitable for use in a kitchenThereafter, the memory management circuit 502 determines whether the second reference value V of the first physical erase unit corresponding to the currently selected valid data is less than the first reference value V_m. If the second reference value V is smaller than the first reference value V_mThe memory management circuit 502 obtains the first reference value V according to equation (4)_mDifference C from a second reference value V_G. Otherwise, if the second reference value V is not less than the first reference value V_mThe memory management circuit 502 will directly use the parameter C_GThe value of (d) is set to 0. According to equation (5), the memory management circuit 502 obtains the second credit E_G。

In an exemplary embodiment, the memory management circuit 502 further determines whether the total number of the currently first type of physically erased cells is less than a first threshold. If the total number of the first kind of physically erased cells is smaller than the first threshold, the memory management circuit 502 will set the first credit E_HIs set to 0. Otherwise, if the total number of the first kind of physically erased cells is not less than the first threshold, the memory management circuit 502 will convert f according to equation (6)_H×C_HAnd the smaller of P is taken as the first credit value E_H. Then, the memory management circuit 502 calculates the write ratio R according to equation (7)_S. In addition, the memory management circuit 502 updates the parameter C according to equation (8)_G。

Fig. 8 and 9 are graphs of write speed of a general memory storage device during a garbage collection procedure. Where the horizontal axis represents time and the vertical axis represents speed or bandwidth. For example, speed or bandwidth refers to how much data is transmitted per unit time.

Referring to FIG. 8, if there is no limit to the ratio of storing data from the host system and valid data collected from the memory to the memory, then the garbage collection procedure is performed (e.g., at time T)₁To T₂) The write speed of the memory storage device to the data from the host system is suddenly fast or slow, as shown by the curve 801. In particular, the garbage collection procedure is started (e.g., at time T)₁) And ending execution of the garbage collection program (e.g., time point T)₂) Writing of a memory storage deviceThe entry speed will vary dramatically.

Referring to FIG. 9, if one or more time ranges (e.g., time T) in the garbage collection process are limited₃To T₄And T₅To T₆) The internal memory storage device completely stops writing data from the host system at some point in the garbage collection process (e.g., point in time T)₃To T₄And T₅To T₆) The writing speed of the memory storage device to the data from the host system is reduced to 0; at certain time points (e.g., time point T)₄To T₅) The memory storage device jumps back to full speed (e.g., S) for the write speed of data from the host system_H) As shown by curve 901. Thus, although the execution efficiency of the garbage collection program can be improved and/or the running time of the garbage collection program can be shortened, the writing speed of the memory storage device is also changed severely.

Fig. 10 and 11 are graphs illustrating write speeds of a memory storage device according to an exemplary embodiment of the invention. Where the horizontal axis represents time and the vertical axis represents speed or bandwidth.

Referring to FIG. 10, in the exemplary embodiment, the first program starts from a time point T₇Execution is started. In the present exemplary embodiment, the write ratio used in the first process is dynamically determined according to equations (1) to (3) or the like, and the first data and the second data are stored according to the write ratio. In the present exemplary embodiment, the writing speed of the memory storage device 10 to the data from the host system 11 may be as shown by the curve 1001. For example, during the execution of the first program, the writing speed of the memory storage device 10 to the data from the host system 11 is maintained at the speed S_LIs near and not less than speed S_L. Compared to the conventional method (e.g., fig. 8 or 9), the running time of the first program in the present example embodiment is longer, and the curve 1001 gradually rises as the running time of the first program increases. For example, when the first program is about to end, the memory storage device 10 writes data from the host system 11 at a high speedWill approach the speed S_H. Wherein the speed S_HIs the write speed (or highest write speed) of the memory storage device 10 for data from the host system 11 without executing the first program.

Referring to FIG. 11, in the exemplary embodiment, the first program starts from a time point T₈Execution is started. In the present exemplary embodiment, the write ratio value used in the first process is dynamically determined according to equations (4) to (8) or the like, and the first data and the second data are stored according to the write ratio value. In the present exemplary embodiment, the writing speed of the memory storage device 10 to the data from the host system 11 may be as shown by the curve 1101. The amplitude of oscillation of the curve 1101 is large and the rising speed is also fast with respect to the curve 1001. Further, with respect to the example embodiment of fig. 10, in the present example embodiment, the runtime (e.g., the time point T) of the first program₈To T₉) And also shorter.

According to the example embodiments of fig. 10 and 11, the memory storage device 10 has a stable write speed (e.g., a stable rise) for data from the host system 11 during the execution of the first program. In addition, the writing speed of the memory storage device 10 for the data from the host system 11 during the execution of the first program is not less than a lower speed limit (e.g., S)_L). Wherein the lower speed limit is greater than 0.

In an example embodiment, the term "keeping the writing speed of the memory storage device 10 or the rewritable nonvolatile memory module 406 stable (i.e. in a stable state) means that the writing speed of the memory storage device 10 or the rewritable nonvolatile memory module 406 for the data (e.g. the first data) from the host system 11 has a variation smaller than a predetermined variation and/or is not lower than a default value (e.g. S) within a time range_L). In an exemplary embodiment, the time range refers to an execution period of the first program. In another exemplary embodiment, the time range specifically includes a stop time point of the first program (e.g., time point T in FIG. 11)₉) A time range of. Changeable pipeIn other words, when the host system 11 continuously stores data and the first process is stopped, the variation of the writing speed of the rewritable nonvolatile memory module 406 does not exceed the predetermined variation.

Fig. 12 is a flowchart illustrating a memory management method according to an exemplary embodiment of the invention.

Referring to fig. 12, in step S1201, first data is received from the host system and temporarily stored. In step S1202, the total number of first kind of physically erased cells in the rewritable nonvolatile memory module is detected. In step S1203, it is determined whether the total number of the detected first type physical erase units is smaller than a first threshold. If the total number of the first type of physically erased cells detected is not less than the first threshold, step S1201 can be repeatedly performed. If the detected total number of the first type of physically erased cells is smaller than the first threshold, in step S1204, a first procedure is performed. In step S1205, the second data is received from the rewritable nonvolatile memory module and temporarily stored. Wherein the second data at least comprises valid data collected through the processing of the first program. In step S1206, a write rule is dynamically determined according to the storage status of the rewritable nonvolatile memory module and the first data and the second data are stored in the rewritable nonvolatile memory module according to the write rule, so that a write speed of the rewritable nonvolatile memory module corresponding to the first data in the first program is not lower than a default value. In step S1207, it is determined whether the total number of the first type of physically erased cells is greater than a second threshold. If the total number of the first type of physically erased cells is not greater than the second threshold, step S1204 may be repeatedly performed. If the total number of the first kind of physically erased cells is greater than the second threshold, in step S1208, the first procedure is stopped.

However, the steps in fig. 12 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 12 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 12 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.

In summary, in an exemplary embodiment, if the total number of the first kind of physically erased cells in the rewritable non-volatile memory module is smaller than a first threshold, the first process is performed. After the first program is started to execute, the write rule used is dynamically adjusted according to the execution status of the first program and/or the data storage state of the rewritable nonvolatile memory module, and the first data received from the host system and the second data received from the rewritable nonvolatile memory module are stored to the rewritable nonvolatile memory module according to the dynamically adjusted write rule. Therefore, the writing speed of the rewritable nonvolatile memory module in the first program is stable.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the invention.

Claims (21)

1. A memory management method is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module comprises a plurality of entity erasing units, and the memory management method comprises the following steps:

receiving first data;

detecting a total number of first type of physically erased cells in the plurality of physically erased cells, wherein each physically erased cell in the plurality of physically erased cells belonging to the first type of physically erased cells stores no valid data;

if the total number of the first kind of entity erasing units is less than a first critical value, executing a first program; and

stopping the first process if the total number of first type entity erased units is greater than a second threshold value, wherein the second threshold value is greater than the first threshold value,

wherein the first program includes:

receiving second data from the rewritable nonvolatile memory module;

temporarily storing the first data and the second data; and

during the execution of the first program, dynamically determining a write rule according to the storage status of the plurality of physical erasure units, and storing the first data and the second data to the rewritable nonvolatile memory module according to the write rule, so that the write speed of the rewritable nonvolatile memory module corresponding to the first data in the first program is not lower than a default value,

wherein dynamically determining the write rule according to the storage status of the plurality of physically erased cells and storing the first data and the second data to the rewritable non-volatile memory module according to the write rule comprises:

storing a first part of the first data and a first part of the second data to the rewritable non-volatile memory module according to a first write proportion value, wherein a proportion of a data amount of the first part of the first data to a data amount of the first part of the second data conforms to the first write proportion value; and

storing a second part of the first data and a second part of the second data to the rewritable non-volatile memory module according to a second write proportion value, wherein a ratio of a data amount of the second part of the first data to a data amount of the second part of the second data conforms to the second write proportion value,

wherein the first write ratio value is different from the second write ratio value.

2. The memory management method according to claim 1, wherein the first program is a data integration program for collecting valid data stored in the rewritable nonvolatile memory module.

3. The method of claim 1, wherein dynamically determining the write rules according to the storage status of the plurality of physically erased cells and storing the first data and the second data to the rewritable non-volatile memory module according to the write rules further comprises:

determining the first writing proportion value according to a first storage state of the plurality of entity erasing units; and

after the first part of the first data and the first part of the second data are stored in the rewritable non-volatile memory module, determining the second writing proportion value according to a second storage state of the plurality of entity erasing units.

4. The memory management method according to claim 1, wherein the total number of the first type entity units is changed from a first number to a second number in the first procedure, wherein the second number is greater than the first number,

wherein dynamically determining the write rule based on the storage status of the plurality of physically erased cells comprises:

determining a write ratio value corresponding to a ratio of storing the first data and the second data to the rewritable non-volatile memory module in the first program according to the second number,

wherein the write ratio value is positively correlated to the second number.

5. The memory management method according to claim 4, wherein determining the write fraction value according to the second number comprises:

determining the write ratio value according to the first threshold value, the second number and a first reference value,

wherein the first reference value corresponds to a storage condition of valid data in the plurality of physically erased cells when it is determined to stop the first process.

6. The method according to claim 1, wherein the second data is data read from a first physically erased cell of the plurality of physically erased cells belonging to a second category of physically erased cells, and the step of dynamically determining the write rule according to the storage status of the plurality of physically erased cells comprises:

obtaining a difference between a first reference value and a second reference value, wherein the first reference value corresponds to a storage condition of valid data in the plurality of physically erased cells when it is determined to stop the first process, and wherein the second reference value corresponds to a storage condition of valid data in the first physically erased cell;

determining a second credit value based on the difference between the first reference value and the second reference value, wherein the difference between the first reference value and the second reference value is positively correlated to the second credit value;

determining a first credit value according to the first reference value, the second reference value and the second credit value; and

determining a write ratio value corresponding to a ratio of storing the first data and the second data to the rewritable non-volatile memory module in the first program according to the first reference value, the second reference value, the first credit value, and the second credit value,

wherein the first credit value is positively correlated to the write fraction value, wherein the second credit value is negatively correlated to the write fraction value.

7. The memory management method of claim 1, wherein the first data is buffered in a first buffer, wherein the second data is buffered in a second buffer, wherein the dynamically determined write rule comprises a write ratio value, and wherein the step of storing the first data and the second data in the rewritable non-volatile memory module according to the write rule comprises:

moving at least a part of the first data from the first buffer to a third buffer according to the writing proportion value;

moving at least a part of the second data from the second buffer to the third buffer according to the writing proportion value, wherein the proportion of the data quantity of the at least a part of the first data to the data quantity of the at least a part of the second data conforms to the writing proportion value; and

and sequentially storing the data temporarily stored in the third buffer into the rewritable nonvolatile memory module.

8. A memory storage device, comprising:

the connection interface unit is used for electrically connecting to a host system;

the rewritable nonvolatile memory module comprises a plurality of entity erasing units; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is to receive first data from the host system,

wherein the memory control circuit unit is further configured to detect a total number of first type of physically erased cells of the plurality of physically erased cells, wherein each of the first type of physically erased cells of the plurality of physically erased cells stores no valid data,

wherein the memory control circuit unit is further configured to instruct execution of a first procedure if the total number of the first type of physically erased cells is less than a first threshold,

wherein the memory control circuit unit is further configured to instruct to stop the first procedure if the total number of first kind of physically erased cells is greater than a second threshold, wherein the second threshold is greater than the first threshold,

wherein in the first program, the memory control circuit unit is further configured to:

receiving second data from the rewritable nonvolatile memory module;

temporarily storing the first data and the second data; and

during the execution of the first program, dynamically determining a write rule according to the storage status of the plurality of physical erasure units and storing the first data and the second data to the rewritable non-volatile memory module according to the write rule, so that the write speed of the rewritable non-volatile memory module corresponding to the first data in the first program is not lower than a default value,

the operations of the memory control circuit unit dynamically determining the write rule according to the storage states of the plurality of physical erase units and storing the first data and the second data to the rewritable non-volatile memory module according to the write rule include:

storing a first part of the first data and a first part of the second data to the rewritable non-volatile memory module according to a first write proportion value, wherein a proportion of a data amount of the first part of the first data to a data amount of the first part of the second data conforms to the first write proportion value; and

storing a second part of the first data and a second part of the second data to the rewritable non-volatile memory module according to a second write proportion value, wherein a ratio of a data amount of the second part of the first data to a data amount of the second part of the second data conforms to the second write proportion value,

wherein the first write ratio value is different from the second write ratio value.

9. The memory storage device of claim 8, wherein the first program is a data merge program for collecting valid data stored in the rewritable non-volatile memory module.

10. The memory storage device of claim 8, wherein the operation of the memory control circuitry unit to dynamically determine the write rule according to the storage status of the plurality of physically erased cells and to store the first data and the second data to the rewritable non-volatile memory module according to the write rule further comprises:

determining the first writing proportion value according to a first storage state of the plurality of entity erasing units; and

after the first part of the first data and the first part of the second data are stored in the rewritable non-volatile memory module, determining the second writing proportion value according to a second storage state of the plurality of entity erasing units.

11. The memory storage device of claim 8, wherein the total number of the first type of physical units is changed from a first number to a second number in the first procedure, wherein the second number is greater than the first number,

wherein the operation of the memory control circuit unit dynamically determining the write rule according to the storage status of the plurality of physically erased cells comprises:

determining a write ratio value corresponding to a ratio of storing the first data and the second data to the rewritable non-volatile memory module in the first program according to the second number,

wherein the write ratio value is positively correlated to the second number.

12. The memory storage device of claim 11, wherein the operation of the memory control circuit unit determining the write fraction value according to the second number comprises:

determining the write ratio value according to the first threshold value, the second number and a first reference value,

wherein the first reference value corresponds to a storage condition of valid data in the plurality of physically erased cells when it is determined to stop the first process.

13. The memory storage device of claim 8, wherein the second data is data read from a first physically erased cell of the plurality of physically erased cells belonging to a second category of physically erased cells, and the operation of the memory control circuit unit to dynamically determine the write rule according to the storage status of the plurality of physically erased cells comprises:

obtaining a difference between a first reference value and a second reference value, wherein the first reference value corresponds to a storage condition of valid data in the plurality of physically erased cells when it is determined to stop the first process, and wherein the second reference value corresponds to a storage condition of valid data in the first physically erased cell;

determining a second credit value based on the difference between the first reference value and the second reference value, wherein the difference between the first reference value and the second reference value is positively correlated to the second credit value;

determining a first credit value according to the first reference value, the second reference value and the second credit value; and

determining a write ratio value corresponding to a ratio of storing the first data and the second data to the rewritable non-volatile memory module in the first program according to the first reference value, the second reference value, the first credit value, and the second credit value,

wherein the first credit value is positively correlated to the write fraction value, wherein the second credit value is negatively correlated to the write fraction value.

14. The memory storage device of claim 8, wherein the first data is buffered in a first register of the memory control circuit unit, wherein the second data is buffered in a second register of the memory control circuit unit, wherein the write rule dynamically determined by the memory control circuit unit comprises a write ratio value, and wherein the operation of the memory control circuit unit to store the first data and the second data in the rewritable non-volatile memory module according to the write rule comprises:

moving at least a part of the first data from the first buffer to a third buffer of the memory control circuit unit according to the writing proportion value;

moving at least a part of the second data from the second buffer to the third buffer according to the writing proportion value, wherein the proportion of the data quantity of the at least a part of the first data to the data quantity of the at least a part of the second data conforms to the writing proportion value; and

and sequentially storing the data temporarily stored in the third buffer into the rewritable nonvolatile memory module.

15. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical erase units, the memory control circuit unit comprising:

a host interface for electrically connecting to a host system;

the memory interface is used for being electrically connected to the rewritable nonvolatile memory module;

a buffer memory; and

a memory management circuit electrically connected to the host interface, the memory interface and the buffer memory,

wherein the memory management circuitry is to receive first data from the host system,

wherein the memory management circuit is further configured to detect a total number of first type of physically erased cells of the plurality of physically erased cells, wherein each of the first type of physically erased cells of the plurality of physically erased cells stores no valid data,

wherein if the total number of the first type of physically erased cells is less than a first threshold, the memory management circuit is further configured to instruct execution of a first procedure,

wherein the memory management circuit is further configured to instruct the first procedure to stop if the total number of first type physical erase units is greater than a second threshold, wherein the second threshold is greater than the first threshold,

wherein in the first process, the memory management circuit is further configured to:

receiving second data from the rewritable nonvolatile memory module;

temporarily storing the first data and the second data in the buffer memory; and

dynamically determining a write rule according to the storage states of the plurality of physical erasure units and storing the first data and the second data to the rewritable nonvolatile memory module according to the write rule, so that the write speed of the rewritable nonvolatile memory module corresponding to the first data in the first program is not lower than a default value,

the operations of the memory management circuit dynamically determining the write rule according to the storage status of the plurality of physically erased cells and storing the first data and the second data into the rewritable non-volatile memory module according to the write rule include:

storing a first part of the first data and a first part of the second data to the rewritable non-volatile memory module according to a first write proportion value, wherein a proportion of a data amount of the first part of the first data to a data amount of the first part of the second data conforms to the first write proportion value; and

storing a second part of the first data and a second part of the second data to the rewritable non-volatile memory module according to a second write proportion value, wherein a ratio of a data amount of the second part of the first data to a data amount of the second part of the second data conforms to the second write proportion value,

wherein the first write ratio value is different from the second write ratio value.

16. The memory control circuit unit of claim 15, wherein the first program is a data integration program for collecting valid data stored in the rewritable nonvolatile memory module.

17. The memory control circuit unit of claim 15, wherein the memory management circuit dynamically determines the write rule according to the storage status of the plurality of physically erased cells and stores the first data and the second data in the rewritable non-volatile memory module according to the write rule further comprises:

determining the first writing proportion value according to a first storage state of the plurality of entity erasing units; and

after the first part of the first data and the first part of the second data are stored in the rewritable non-volatile memory module, determining the second writing proportion value according to a second storage state of the plurality of entity erasing units.

18. The memory control circuit unit of claim 15, wherein said total number of said first type of physical units is changed from a first number to a second number during said first procedure, wherein said second number is greater than said first number,

wherein the operation of the memory management circuit to dynamically determine the write rule based on the storage status of the plurality of physically erased cells comprises:

determining a write ratio value corresponding to a ratio of storing the first data and the second data to the rewritable non-volatile memory module in the first program according to the second number,

wherein the write ratio value is positively correlated to the second number.

19. The memory control circuit unit of claim 18, wherein the operation of the memory management circuit determining the write fraction value according to the second number comprises:

determining the write ratio value according to the first threshold value, the second number and a first reference value,

wherein the first reference value corresponds to a storage condition of valid data in the plurality of physically erased cells when it is determined to stop the first process.

20. The memory control circuit unit of claim 15, wherein the second data is data read from a first physically erased cell of the plurality of physically erased cells belonging to a second category of physically erased cells, and the operation of the memory management circuit to dynamically determine the write rule based on the storage status of the plurality of physically erased cells comprises:

obtaining a difference between a first reference value and a second reference value, wherein the first reference value corresponds to a storage condition of valid data in the plurality of physically erased cells when it is determined to stop the first process, and wherein the second reference value corresponds to a storage condition of valid data in the first physically erased cell;

determining a second credit value based on the difference between the first reference value and the second reference value, wherein the difference between the first reference value and the second reference value is positively correlated to the second credit value;

determining a first credit value according to the first reference value, the second reference value and the second credit value; and

determining a write ratio value corresponding to a ratio of storing the first data and the second data to the rewritable non-volatile memory module in the first program according to the first reference value, the second reference value, the first credit value, and the second credit value,

wherein the first credit value is positively correlated to the write fraction value, wherein the second credit value is negatively correlated to the write fraction value.

21. The memory control circuit unit of claim 15, wherein the first data is buffered in a first register of the buffer memory, wherein the second data is buffered in a second register of the buffer memory, wherein the write rule dynamically determined by the memory management circuit comprises a write ratio value, wherein the operation of the memory management circuit to store the first data and the second data to the rewritable non-volatile memory module according to the write rule comprises:

moving at least a part of the first data from the first buffer to a third buffer in the buffer memory according to the writing proportion value;

moving at least a part of the second data from the second buffer to the third buffer according to the writing proportion value, wherein the proportion of the data quantity of the at least a part of the first data to the data quantity of the at least a part of the second data conforms to the writing proportion value; and

and sequentially storing the data temporarily stored in the third buffer into the rewritable nonvolatile memory module.

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