CN110837339B

CN110837339B - Data merging method, memory storage device and memory control circuit unit

Info

Publication number: CN110837339B
Application number: CN201810938535.1A
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2018-08-17
Filing date: 2018-08-17
Publication date: 2023-07-04
Anticipated expiration: 2038-08-17
Also published as: CN110837339A

Abstract

The invention provides a data merging method, which is used for a memory storage device. The method comprises the following steps: a data consolidation operation is performed to store valid data collected from the source node to the reclamation node. The data merging operation includes: reading first data from the first entity unit via a first read operation; performing a first-stage programming operation on the second entity unit according to the first data; reading the first data from the first entity unit again via a second read operation; and performing a second-stage programming operation on the second physical unit according to the first data read by the second reading operation. In addition, the invention also provides a memory storage device and a memory control circuit unit.

Description

Data merging method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to memory management, and more particularly, to a data merging method, a memory storage device and a memory control circuit unit.

Background

Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.

The rewritable nonvolatile memory module may be a third-order memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell) or a fourth-order memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell). In the TLC NAND type flash memory module or the QLC NAND type flash memory module, one physical unit may be programmed multiple times based on the same write data to completely store the write data. In addition, multiple programming operations for different physical units may be performed in an interleaved manner. Therefore, it is often necessary to configure a buffer memory with enough storage space in a memory storage device to store write data for different physical units at the same time.

Disclosure of Invention

The invention provides a data merging method, a memory storage device and a memory control circuit unit, which can save the use space of a buffer memory in the data merging operation.

Exemplary embodiments of the present invention provide a data consolidation method for a memory storage device including a plurality of entity units, and the data consolidation method includes: a data consolidation operation is performed to store valid data collected from the source node to the reclamation node. The source node comprises at least one first entity unit of the entity units, the recovery node comprises a second entity unit of the entity units and the data integration operation comprises: reading first data from the first entity unit via a first read operation; performing a first-stage programming operation on the second entity unit according to the first data; after performing the first-stage programming operation, reading the first data from the first physical unit again via a second read operation; and performing a second-stage programming operation on the second physical unit according to the first data read via the second read operation.

In an exemplary embodiment of the present invention, the source node further includes at least one third entity unit among the entity units, the recovery node further includes a fourth entity unit among the entity units, and the data merging operation further includes: reading second data from the third entity unit; and programming the fourth entity unit according to the second data between the first stage programming operation and the second stage programming operation.

In an exemplary embodiment of the present invention, the data merging operation further includes: temporarily storing the first data read through the first read operation in a buffer memory to provide the first data for the first stage programming operation; temporarily storing second data in the buffer memory, and the second data overwrites at least a portion of the first data read via the first read operation in the buffer memory; and saving the first data read via the second read operation in the buffer memory to provide the first data for the second stage programming operation.

In an exemplary embodiment of the invention, the data merging method further includes: recording read information in a management table, wherein the read information reflects whether the first entity unit is read by at least one of the first read operation and the second read operation; and erasing the first physical unit according to the read information.

In an exemplary embodiment of the invention, the data merging method further includes: the first data read by the first reading operation or the second reading operation is temporarily stored in a buffer memory. The second entity unit has a basic capacity, and the available capacity of the buffer memory is less than twice the basic capacity.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for performing data merging operation to store valid data collected from the source node to the reclamation node. The source node includes at least one first entity unit of the entity units, the recovery node includes a second entity unit of the entity units, and the data integration operation includes: sending a first sequence of read instructions to instruct reading first data from the first entity unit via a first read operation; transmitting a first write instruction sequence to instruct the second entity unit to execute a first stage programming operation according to the first data; after performing the first-stage programming operation, sending a second sequence of read instructions to instruct to read the first data from the first physical unit again via a second read operation; and sending a second sequence of write instructions to instruct a second-stage programming operation to be performed on the second physical unit in accordance with the first data read via the second read operation.

In an exemplary embodiment of the present invention, the data merging operation further includes: temporarily storing the first data read through the first read operation in a buffer memory to provide the first data for the first stage programming operation; temporarily storing second data in the buffer memory, and the second data overwrites the first data read via the first read operation in the buffer memory; and saving the first data read via the second read operation in the buffer memory to provide the first data for the second stage programming operation.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to record read information in a management table and erase the first physical unit according to the read information. The read information reflects whether the first physical unit is read by at least one of the first read operation and the second read operation.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to temporarily store the first data read by the first read operation or the second read operation in a buffer memory. The second entity unit has a basic capacity, and the available capacity of the buffer memory is less than twice the basic capacity.

The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is configured to perform a data merge operation to store valid data collected from the source node to the reclamation node. The source node includes at least one first entity unit of the entity units, the recovery node includes a second entity unit of the entity units, and the data integration operation includes: sending a first sequence of read instructions to instruct reading first data from the first entity unit via a first read operation; transmitting a first write instruction sequence to instruct the second entity unit to execute a first stage programming operation according to the first data; after performing the first-stage programming operation, sending a second sequence of read instructions to instruct to read the first data from the first physical unit again via a second read operation; and sending a second sequence of write instructions to instruct a second-stage programming operation to be performed on the second physical unit in accordance with the first data read via the second read operation.

In an exemplary embodiment of the present invention, the source node further includes at least one third entity unit among the entity units, the recovery node further includes a fourth entity unit among the entity units, and the data merging operation further includes: transmitting a third read instruction sequence to instruct reading of second data from the third entity unit; and sending a third sequence of write instructions between the first phase programming operation and the second phase programming operation to instruct programming the fourth entity unit according to the second data.

In an exemplary embodiment of the invention, the memory control circuit unit further includes a buffer memory. The buffer memory is connected to the memory management circuit, and the data merge operation further comprises: temporarily storing the first data read via the first read operation in the buffer memory to provide the first data for the first stage programming operation; temporarily storing second data in the buffer memory, and the second data overwrites the first data read via the first read operation in the buffer memory; and saving the first data read via the second read operation in the buffer memory to provide the first data for the second stage programming operation.

In an exemplary embodiment of the invention, the memory management circuit is further configured to record read information in a management table and erase the first physical unit according to the read information, wherein the read information reflects whether the first physical unit is read by at least one of the first read operation and the second read operation.

In an exemplary embodiment of the present invention, the second entity unit stores the first data sequentially through the first-stage programming operation and the second-stage programming operation.

In an exemplary embodiment of the present invention, the first-stage programming operation and the second-stage programming operation belong to a multi-stage programming operation, and one memory cell of the second physical unit programmed by the multi-stage programming operation stores not less than 3 bits.

In an exemplary embodiment of the invention, the memory control circuit unit further includes a buffer memory. The buffer memory is connected to the memory management circuit, and the memory management circuit is further configured to store the first data read via the first read operation or the second read operation temporarily in the buffer memory. The second entity unit has a basic capacity, and the available capacity of the buffer memory is less than twice the basic capacity.

Based on the above, in the data merging operation, the same data in the first entity unit may be read at least twice to complete the multi-stage programming operation for the second entity unit according to the data read via the different reading operations.

In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment of the invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5A is a schematic diagram of a memory cell array according to an example embodiment of the invention;

FIG. 5B is a schematic diagram of a memory cell array according to another exemplary embodiment of the present invention;

FIG. 6 is a schematic block diagram of a memory control circuit unit according to an example embodiment of the invention;

FIG. 7 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 8 is a schematic diagram of a programmable physical unit according to an example embodiment of the invention;

FIG. 9 is a schematic diagram of a programmable physical unit according to an example embodiment of the invention;

FIG. 10 is a schematic diagram of a programmable physical unit according to an example embodiment of the invention;

FIG. 11 is a diagram illustrating programming of multiple entity units in a entity management unit according to an example embodiment of the present invention;

FIG. 12 is a schematic diagram illustrating a data merge operation in accordance with an exemplary embodiment of the present invention;

FIGS. 13-17 are schematic diagrams illustrating a data merge operation according to an example embodiment of the invention;

fig. 18 is a flowchart of a data consolidation method according to an example embodiment of the invention.

Reference numerals illustrate:

10. 30: memory storage device

11. 31: host system

110: system bus

111: processor and method for controlling the same

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: motherboard

201: portable disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with keyboard body

209: screen

210: horn with horn body

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

502. 522: memory cell

504: bit line

506: word line

508: common source line

510. 520: memory cell array

512: select gate drain transistor

514: select gate source transistor

524: bit line

524 (1) to 524 (4): bytes

526 (1) to 526 (8): word line layer:

602: memory management circuit

604: host interface

606: memory interface

608: error checking and correcting circuit

610: buffer memory

612: power management circuit

701: storage area

702: replacement area

710 (0) to 710 (B), 1110 (0) to 1110 (D), 1210 (0) to 1210 (E), 1220 (0) to 1220 (F), 1310 (0) to 1310 (G), 1320 (0) to 1320 (H), 1610 (0) to 1610 (I): entity unit

712 (0) to 712 (C): logic unit

801. 802, 811-814, 821-828, 901-908, 911-926, 1001-1016, 1021-1036: status of

1110: entity management unit

1210. 1310, 1320, 1610: source node

1220: recovery node

1300. 1400, 1600: data

1301. 1401, 1501, 1601, 1701: read operation

1302. 1402, 1602: first stage programming operation

1502. 1702: second stage Programming operation

S1810: step (Start data integration operation)

S1820: step (a)

S1821: step (reading first data from the first physical unit via the first reading operation)

S1822: step (performing a first-stage programming operation on the second entity unit according to the first data)

S1823: step (reading the first data from the first physical unit again via the second reading operation)

S1824: step (performing a second-stage programming operation on the second physical unit according to the first data read by the second read operation)

S1830: step (end data merging operation)

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are all connected to a system bus 110.

In the present exemplary embodiment, host system 11 is coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 via a wired or wireless connection via the data transmission interface 114. The memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, the host system referred to is any system that can cooperate with substantially a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may be a system such as a Digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 30 may be a variety of nonvolatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33 or an embedded storage device 34. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to a substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. In the present exemplary embodiment, the connection interface unit 402 is compliant with the serial advanced attachment (Serial Advanced Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a standard compliant with parallel advanced accessory (Parallel Advanced Technology Attachment, PATA) standard, institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, high-Speed peripheral component interconnect (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, SD interface standard, ultra High Speed-I (UHS-I) interface standard, ultra High Speed-II (UHS-II) interface standard, memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, universal flash Memory (Universal Flash Storage, UFS) interface standard, eMCP interface standard, CF interface standard, integrated drive electronics (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in a single chip, or the connection interface unit 402 may be disposed off-chip with the memory control circuit unit 404.

The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and is used to store data written by the host system 11. The rewritable nonvolatile memory module 406 may be a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell) other flash memory modules, or other memory modules having the same characteristics.

The memory cells in the rewritable nonvolatile memory module 406 are arranged in an array. The memory cell arrays in the different exemplary embodiments are described below in terms of two-dimensional arrays and three-dimensional arrays, respectively. It should be noted that the following exemplary embodiments are only examples of the memory cell array, and in other exemplary embodiments, the configuration of the memory cell array may be adjusted to meet the practical requirements.

FIG. 5A is a schematic diagram of a memory cell array according to an example embodiment of the invention.

Referring to fig. 5A, a memory cell array 510 includes a plurality of memory cells 502 for storing data, a plurality of select gate drain (select gate drain, SGD) transistors 512 and a plurality of select gate source (select gate source, SGS) transistors 514, a plurality of bit lines 504, a plurality of word lines 506, and a common source line 508 connecting the memory cells 502. Memory cells 502 are arranged in an array at the intersections of bit lines 504 and word lines 506, as shown in FIG. 5A.

FIG. 5B is a schematic diagram of a memory cell array according to another exemplary embodiment of the present invention.

Referring to fig. 5B, the memory cell array 520 includes a plurality of memory cells 522 for storing data, a plurality of bytes 524 (1) to 524 (4), and a plurality of word line layers 526 (1) to 526 (8). Bytes 524 (1) -524 (4) are independent of each other (e.g., separate from each other) and are arranged along a first direction (e.g., X-axis). Each of the bytes 524 (1) -524 (4) includes a plurality of bit lines 524 that are independent of each other (e.g., separate from each other). The bit lines 524 included in each byte are arranged along a second direction (e.g., Y-axis) and extend toward a third direction (e.g., Z-axis). The word line layers 526 (1) -526 (8) are independent of each other (e.g., separate from each other) and stacked in a third direction. In the present exemplary embodiment, each of the word line layers 526 (1) -526 (8) may also be considered a plane (also referred to as a word line plane). Each memory cell 522 is configured at each intersection between each bit line 524 in bytes 524 (1) through 524 (4) and word line layers 526 (1) through 526 (8). However, in another example embodiment, one byte may include more or fewer bit lines, and one word line layer may also pass more or fewer bytes.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

FIG. 6 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to fig. 6, the memory control circuit unit 404 includes a memory management circuit 602, a host interface 604, and a memory interface 606.

The memory management circuit 602 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 602 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is operating. The operation of the memory management circuit 602 is described as follows, which is equivalent to the description of the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control instructions of the memory management circuit 602 are implemented in firmware. For example, the memory management circuit 602 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In another example embodiment, the control instructions of the memory management circuit 602 may also be stored in program code form in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area of the memory module dedicated to storing system data). In addition, the memory management circuit 602 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 602. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

Furthermore, in another example embodiment, the control instructions of the memory management circuit 602 may also be implemented in a hardware form. For example, the memory management circuit 602 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit is configured to issue an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 406 to perform the corresponding write, read, erase, etc. In an example embodiment, the memory management circuitry 602 may also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 604 is coupled to the memory management circuit 602 and is configured to receive and identify commands and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 602 through the host interface 604. In the present exemplary embodiment, host interface 604 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 604 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 606 is coupled to the memory management circuitry 602 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 606. Specifically, if the memory management circuit 602 is to access the rewritable nonvolatile memory module 406, the memory interface 606 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels, etc.). These sequences of instructions are, for example, generated by memory management circuitry 602 and transferred to rewritable non-volatile memory module 406 through memory interface 606. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

In an example embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 608, a buffer memory 610, and a power management circuit 612.

The error checking and correction circuit 608 is connected to the memory management circuit 602 and is used for performing error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 602 receives a write command from the host system 11, the error checking and correcting circuit 608 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 602 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 602 reads data from the rewritable nonvolatile memory module 406, it reads the error correction code and/or the error check code corresponding to the data, and the error check and correction circuit 608 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.

The buffer memory 610 is connected to the memory management circuit 602 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 612 is coupled to the memory management circuit 602 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 406 of fig. 4 is also referred to as a flash memory module, the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module, and/or the memory management circuit of fig. 6 is also referred to as a flash memory management circuit.

FIG. 7 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention.

Referring to FIG. 7, the memory management circuit 602 logically groups the physical units 710 (0) -710 (B) of the rewritable nonvolatile memory module 406 into a storage area 701 and a replacement area 702. The physical units 710 (0) -710 (a) in the storage area 701 are used to store data, and the physical units 710 (a+1) -710 (B) in the replacement area 702 are used to replace damaged physical units in the storage area 701. For example, if the data read from a certain physical cell contains too many errors to be corrected, the physical cell is considered as a damaged physical cell. It should be noted that if there are no physical units available in the replacement area 702, the memory management circuit 602 may declare the entire memory storage device 10 to be in a write protect (write protect) state, and no more data can be written.

The memory management circuit 602 programs memory cells based on a physical unit. That is, memory cells belonging to the same physical unit may be programmed synchronously. For example, one physical cell may include memory cells on N word lines, and N may be 4 or another integer (e.g., 2, 8, or 16, etc.). In other words, one physical cell may include or consist of memory cells on N word lines. However, in another exemplary embodiment, one physical unit may also include more or fewer memory units, which is not a limitation of the present invention. In an example embodiment, a physical unit may also be referred to as a layer (or memory layer).

Memory management circuit 602 configures logic units 712 (0) -712 (C) to map physical units 710 (0) -710 (A) in memory region 701. In the present exemplary embodiment, one logical unit refers to one logical address. However, in another exemplary embodiment, a logic unit may also refer to a logic layer or be composed of a plurality of consecutive or non-consecutive logic addresses. In addition, each of logic cells 712 (0) -712 (C) may be mapped to one or more physical cells.

The memory management circuit 602 records a mapping relationship (also referred to as a logical-physical address mapping relationship) between logical units and physical units in at least one logical-physical address mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 602 can perform a data access operation to the memory storage device 10 according to the logical-to-physical address mapping table.

In an example embodiment, the memory management circuit 602 performs a multi-stage programming operation on a physical unit to store data (also referred to as write data) to the physical unit. For example, the multi-stage programming operation may include at least a first-stage programming operation and a second-stage programming operation, and the second-stage programming operation is performed after the first-stage programming operation. In addition, between performing the first-stage programming operation and the second-stage programming operation for the physical unit, the programming operation for another physical unit may be performed.

FIG. 8 is a schematic diagram of a programmable physical unit according to an example embodiment of the invention. Taking TLC NAND type flash memory modules as an example, for a multi-phase programming operation of a certain physical cell, each memory cell belonging to the physical cell can be programmed to a state of storing 3 bits.

Referring to fig. 8, before programming a certain physical unit, the memory units of the physical unit all belong to state ERA. For example, after erasing the physical cell, the erased memory cells all belong to state ERA. The threshold voltages of the memory cells belonging to state ERA are all within a predetermined voltage range (also referred to as an erase voltage range). After performing a programming operation on the physical unit, the programmed memory unit may belong to the state 801 and the state 802. Memory cells belonging to different states may have different threshold voltages. For example, the threshold voltage of the memory cell belonging to state 802 is greater than the threshold voltage of the memory cell belonging to state 801. Then, after the next programming operation is performed on the physical cell, the programmed cell will be in states 811-814 and the threshold voltage of the cell will be changed accordingly. For example, the memory cell belonging to state 811 has the lowest threshold voltage, while the memory cell belonging to state 814 has the highest threshold voltage. Then, after the next programming operation is performed on the physical cell, the programmed cell will be in states 821-828 and the threshold voltage of the cell will be changed. For example, the memory cell belonging to state 821 has the lowest threshold voltage, while the memory cell belonging to state 828 has the highest threshold voltage. Each memory cell belonging to states 821-828 stores 3 bits.

FIG. 9 is a schematic diagram of a programmable physical unit according to an example embodiment of the invention. Taking the QLC NAND type flash memory module as an example, for a multi-stage programming operation of a certain physical cell, each memory cell belonging to the physical cell can be programmed to a state of storing 4 bits.

Referring to fig. 9, taking a QLC NAND flash memory module as an example, before programming a certain physical cell, the memory cells of the physical cell all belong to state ERA. After performing a programming operation on the physical unit, the programmed memory unit will belong to the states 901-908. For example, the threshold voltage of the memory cell belonging to state 908 is greater than the threshold voltage of the memory cell belonging to state 901. Then, after the next programming operation is performed on the physical cell, the programmed cell will be in states 911-926 and the threshold voltage of the cell will be changed. For example, the threshold voltage of the memory cell belonging to state 926 is greater than the threshold voltage of the memory cell belonging to state 911. Each memory cell belonging to states 911-926 stores 4 bits.

In the exemplary embodiments of fig. 8 and 9, the first-stage programming operation may be considered the first-stage programming operation, and the second-stage programming operation may be considered the second-stage programming operation. For example, in an example embodiment of FIG. 8, a first stage programming operation programs memory cells to belong to states 801 and 802 (or 811-814), and a second stage programming operation programs memory cells to belong to states 811-814 (or 821-828). In an example embodiment of FIG. 9, a first phase of programming operations programs memory cells to belong to states 901-908, and a second phase of programming operations programs memory cells to belong to states 911-926. It should be noted that the present invention is not limited to the programming of memory cells by different programming stages in a multi-stage programming operation.

FIG. 10 is a schematic diagram of a programmable physical unit according to an example embodiment of the invention. The present exemplary embodiment also exemplifies the programming of the QLC NAND type flash memory module.

Referring to fig. 10, before programming a certain physical unit, the memory cells of the physical unit all belong to state ERA. After performing a programming operation on this physical unit, the programmed memory unit will belong to states 1001-1016. Then, after the next programming operation is performed on the physical unit, the programmed memory cell will belong to states 1021-1036. Each memory cell belonging to states 1021-1036 stores 4 bits. It should be noted that in the exemplary embodiment of fig. 10, the first stage programming operation is to roughly adjust the threshold voltage of the memory cell. Thereafter, in the second phase programming operation, the threshold voltage of the memory cell is more precisely adjusted to the voltage level corresponding to states 1021-1036.

FIG. 11 is a diagram illustrating programming of multiple entity units in a entity management unit according to an exemplary embodiment of the present invention.

Referring to fig. 11, an entity management unit 1110 includes a plurality of entity units 1110 (0) to 1110 (D). For example, D may be a positive integer of 8, 16, 32, etc., and the invention is not limited. In an exemplary embodiment, the physical units 1110 (0) -1110 (D) belonging to the physical management unit 1110 may be erased simultaneously. In addition, the physical units 1110 (0) to 1110 (D) are alternately programmed.

In an exemplary embodiment, when data is stored in the entity management unit 1110, the entity units 1110 (0) to 1110 (D) may sequentially perform multi-stage programming operations according to the numbers indicated in fig. 11. For example, some write data (also referred to as first data) may be temporarily stored in the buffer memory 610 of fig. 6. According to the first data in the buffer memory 610, a first-stage programming operation of the entity unit 1110 (0) may be performed (corresponding to reference numeral 1 of fig. 11). After performing the first-stage programming operation of the physical unit 1110 (0), another write data (also referred to as a second data) may be buffered in the buffer memory 610. According to the second data in the buffer memory 610, the first-stage programming operation of the entity unit 1110 (1) can be performed (corresponding to reference numeral 2 of fig. 11). After performing the first-stage programming operation of the entity unit 1110 (1), the second-stage programming operation of the entity unit 1110 (0) may be performed according to the first data in the buffer memory 610 (corresponding to reference numeral 3 of fig. 11). It should be noted that after the second-stage programming operation of the entity 1110 (0) is completed, it may be determined that the multi-stage programming operation for the entity 1110 (0) is completed and the first data is stored in the entity 1110 (0).

After performing the second phase programming operation of the physical unit 1110 (0), another write data (also referred to as a third data) may be buffered in the buffer memory 610 of fig. 6. Then, according to the third data in the buffer memory 610, the first-stage programming operation of the entity unit 1110 (2) may be performed (corresponding to reference numeral 4 of fig. 11). After performing the first-stage programming operation of the entity 1110 (2), the second data may be temporarily stored in the buffer memory 610 of fig. 6 again. Then, according to the second data in the buffer memory 610, the second stage programming operation of the entity unit 1110 (1) can be performed (corresponding to reference numeral 5 of fig. 11). It should be noted that after the second-stage programming operation of the entity 1110 (1) is completed, it may be determined that the multi-stage programming operation for the entity 1110 (1) is completed and the second data is stored in the entity 1110 (1). By so doing, the remaining physical units in the physical management unit 1110 may be programmed to store other data in an interleaved manner.

In an example embodiment, the available capacity of the buffer memory 610 may be limited by the cost of device implementation. For example, a designer may reduce the available capacity of the buffer memory 610 to reduce the cost of device construction. Thus, in an example embodiment, the available space of the buffer memory 610 of fig. 6 may not be sufficient to store the first data and the second data simultaneously. Alternatively, from another perspective, assuming each physical unit has a base capacity, the available capacity of the buffer memory 610 may be less than twice this base capacity. If the available capacity of the buffer memory 610 is less than twice this basic capacity, the available space of the buffer memory 610 is also insufficient to store the first data and the second data simultaneously.

According to the example embodiment of fig. 11, the first data is used to perform multi-stage programming operations (corresponding to reference numerals 1 and 3) for the physical unit 1110 (0), and the second data is used to perform multi-stage programming operations (corresponding to reference numerals 2 and 5) for the physical unit 1110 (1). If the available space of the buffer memory 610 is insufficient to store the first data and the second data simultaneously, at least a portion of the first data originally stored temporarily in the buffer memory 610 for performing the first phase programming operation (corresponding to the reference numeral 1 of fig. 11) for the entity unit 1110 (0) may be overwritten by the second data for performing the first phase programming operation (corresponding to the reference numeral 2 of fig. 11) for the entity unit 1110 (1) when the entity units 1110 (0) and 1110 (1) are programmed. Thus, after performing the first phase programming operation (corresponding to reference number 2 of FIG. 11) for entity unit 1110 (1), the buffer memory 610 may not have the first data in its entirety for use by the second phase programming operation (corresponding to reference number 3 of FIG. 11) for entity unit 1110 (0).

In an exemplary embodiment of fig. 11, after performing the first-stage programming operation (corresponding to reference numeral 2 of fig. 11) of the entity unit 1110 (1), the first data may be read again and temporarily stored in the buffer memory 610. For example, if the first data is instant data from the host system 11 of fig. 1, the first data may be received again from the host system 11. Alternatively, if the first data is data read from a certain physical unit in the storage area 710 of fig. 7, the first data may be read from the physical unit again. After the first data is saved in the buffer memory 610 again, the second-stage programming operation of the entity unit 1110 (0) may be performed according to the first data in the buffer memory 610 (corresponding to reference numeral 3 of fig. 11). Similarly, after the re-read first data is temporarily stored in the buffer memory 610, at least a portion of the second data in the buffer memory 610 may be overwritten. Thus, in an example embodiment of FIG. 11, prior to performing the second-stage programming operation (corresponding to reference number 5 of FIG. 11) for the entity 1110 (1), the second data may be received again from the host system 11 (or read again from a certain entity) and buffered in the buffer memory 610 for use in the second-stage programming operation for the entity 1110 (1).

Fig. 12 is a schematic diagram illustrating a data merging operation according to an exemplary embodiment of the present invention.

Referring to fig. 12, at a specific point in time, the memory management circuit 602 may perform a data merging operation. For example, this particular point in time may be any point in time when there are insufficient free physical units in the memory area 701 of fig. 7, when the memory storage device 10 of fig. 1 is in an idle state, or when the set condition is satisfied. In an example embodiment, the data consolidation operation is also referred to as a garbage collection operation. After initiating the data merge operation, the memory management circuit 602 may send a read command sequence to the rewritable nonvolatile memory module 406 of FIG. 4 to instruct to read valid data from the physical units 1210 (0) -1210 (E) as the source node 1210. The read valid data (also referred to as collected valid data) may be buffered in the buffer memory 610. The memory management circuitry 602 may then send a sequence of write instructions to the rewritable nonvolatile memory module 406 of fig. 4 to instruct to store the data in the buffer memory 610 (i.e., the collected valid data) to the entity units 1220 (0) to 1220 (F) as the reclamation node (or target node) 1220. After the valid data from a certain physical unit as the source node 1210 is completely stored in the source node 1220, the physical unit (or the physical management unit including the physical unit) can be erased. For example, it is assumed that the physical unit 1210 (0) (or the physical management unit including the physical unit 1210 (0)) can be erased after being completely programmed to the physical unit 1220 (0) through the multi-stage programming operation according to the valid data from the physical unit 1210 (0). The erased physical cell (or physical management cell) may become a new idle physical cell (or idle physical management cell). In other words, the new idle entity unit can be released through the data merge operation. In addition, if certain conditions are met (e.g., enough idle physical units are generated), the data merge operation may be stopped.

Fig. 13 to 17 are schematic diagrams illustrating a data merging operation according to an exemplary embodiment of the present invention.

Referring to fig. 13, it is assumed that in the data merging operation, valid data is collected from

source nodes

1310 and 1320 and written to an entity management unit 1110 as a reclamation node. After initiating the data merge operation, the data 1300 is read from at least one of the physical units 1310 (0) -1310 (G) in the source node 1310 and buffered to the buffer memory 610 via the read operation 1301. According to the data 1300 read via the read operation 1301 in the buffer memory 610, a first-stage programming operation 1302 may be performed to program the entity unit 1110 (0) in the entity management unit 1110 (corresponding to reference numeral 1 of fig. 13).

Referring to FIG. 14, the physical unit 1110 (0) programmed by the first-stage programming operation 1302 is marked with diagonal lines. After the first stage programming 1302 is performed, the data 1400 is read from at least one of the physical units 1320 (0) -1320 (H) in the source node 1320 and buffered to the buffer memory 610 via the read operation 1401. For example, the data 1400 may overwrite at least a portion of the data originally stored in the data 1300 in the buffer memory 610. According to the data 1400 read in the buffer memory 610 via the read operation 1401, a first-stage programming operation 1402 may be performed to program the physical unit 1110 (1) (corresponding to reference numeral 2 of fig. 14).

Referring to FIG. 15, the physical unit 1110 (1) programmed by the first-stage programming operation 1402 is marked with diagonal lines. After performing the first-stage programming 1402, the data 1300 is again read from at least one of the physical units 1310 (0) -1310 (G) in the source node 1310 and buffered in the buffer memory 610 via the read operation 1501. For example, the data 1300 may overwrite at least a portion of the data of the originally stored data 1400 in the buffer memory 610. According to the data 1300 read by the read operation 1501 in the buffer memory 610, the second-stage programming operation 1502 may be performed to program the entity unit 1110 (0) again (corresponding to the reference numeral 3 of fig. 15).

It should be noted that the read operation 1301 of fig. 13 and the read operation 1501 of fig. 15 are performed to read the data 1300 from the same physical cell. For example, if the read operation 1301 is to read the data 1300 from the physical unit 1310 (0), the read operation 1501 is also to read the data 1300 from the physical unit 1310 (0). In other words, the

read operations

1301 and 1501 are performed to read the data 1300 stored at the same physical address. Alternatively, from another perspective, the data 1300 repeatedly read from the same physical unit via the

read operations

1301 and 1501 may be used to perform a multi-stage programming operation on the physical unit 1110 (0).

Referring to FIG. 16, the physical unit 1110 (0) programmed by the second stage programming operation 1502 is marked with a bottom. After performing the second phase programming operation 1502, the data 1600 is read from at least one of the physical units 1610 (0) -1610 (I) in another source node 1610 and buffered to the buffer memory 610 via a read operation 1601. For example, data 1600 may overwrite at least a portion of data originally stored data 1300 in buffer memory 610. According to the data 1600 read by the read operation 1601 in the buffer memory 610, a first-stage programming operation 1602 may be performed to program the physical unit 1110 (2) (corresponding to reference numeral 4 of fig. 16).

Referring to FIG. 17, the physical unit 1110 (2) programmed by the first-stage programming operation 1602 is marked with diagonal lines. After performing the first stage programming operation 1602, the data 1400 is again read from at least one of the physical units 1320 (0) -1320 (H) in the source node 1320 and buffered in the buffer memory 610 via the read operation 1701. For example, the data 1400 may overwrite at least a portion of the data of the originally stored data 1600 in the buffer memory 610. According to the data 1400 read in the buffer memory 610 via the read operation 1701, a second stage programming operation 1702 may be performed to re-program the physical unit 1110 (1) (corresponding to reference numeral 5 of fig. 17).

It should be noted that the read operation 1401 of fig. 14 and the read operation 1701 of fig. 17 are used to read the data 1400 from the same physical unit. For example, if the read operation 1401 is to read the data 1400 from the physical unit 1320 (0), then the read operation 1701 is also to read the data 1400 from the physical unit 1320 (0). In other words, the

reading operations

1401 and 1701 are to read the data 1400 stored in the same physical address. Alternatively, from another perspective, the data 1400 repeatedly read from the same physical unit via the

read operations

1401 and 1701 may be used to perform multi-stage programming operations on the physical unit 1110 (1). And so on, more valid data may be collected from the source node and stored in the entity management unit 1110 as a reclamation node. In addition, the use of the entity management unit 1110 in the example embodiment of fig. 13-17 is the same as or similar to the use of the entity management unit 1110 in the example embodiment of fig. 11.

In an example embodiment, the memory management circuit 602 also records read information related to the reading of the physical unit in a management table. The read information may reflect whether a physical cell serving as the source node has been read by one or more read operations (or a predetermined number of times).

Taking the example embodiment of fig. 13 as an example, assume that the read information corresponding to the physical unit 1310 (0) in the management table is the initial read flag (e.g., value 0) when the data merging operation is just started. After reading the data 1300 from the entity unit 1310 (0) via the read operation 1301, the read information corresponding to the entity unit 1310 (0) may be updated. For example, the read information corresponding to entity unit 1310 (0) may be updated in the management table to a first read flag (e.g., a value of 1) to reflect that entity unit 1310 (0) has been read via read operation 1301 in the data merge operation. In the example embodiment of fig. 15, after the data 1300 is again read from the physical unit 1310 (0) via the read operation 1501, the read information corresponding to the physical unit 1310 (0) may be updated again. For example, the read information corresponding to entity unit 1310 (0) may be updated in the management table to a second read flag (e.g., a value of 2) to reflect that entity unit 1310 (0) has been read via read operation 1501 in the data merge operation. Alternatively, from another perspective, the initial read flag corresponding to entity 1310 (0) may reflect that entity 1310 (0) has not been read in the data merge operation; the first read flag corresponding to the entity 1310 (0) may reflect that the entity 1310 (0) was read once in the data merge operation; and/or a second read flag corresponding to entity 1310 (0) may reflect that entity 1310 (0) was read twice in a data merge operation. In addition, in an exemplary embodiment, the read information corresponding to the physical unit 1310 (0) may also include only the initial read flag and the second read flag to reflect whether the physical unit 1310 (0) has been read twice in the data merge operation.

In an exemplary embodiment, the memory management circuit 602 may determine whether to erase a physical cell based on read information corresponding to the physical cell. For example, after performing the data merging operation, the memory management circuit 602 can determine whether the read information corresponding to a certain physical cell is a second read flag. If the read information corresponding to the physical cell is a second read flag, which indicates that the physical cell has been read twice during the data merge operation, the memory management circuit 602 may instruct to erase the physical cell. Conversely, if the read information corresponding to the physical cell is not the second read flag, which indicates that the physical cell has not been read twice in the data merge operation, the memory management circuit 602 may not instruct to erase the physical cell. For example, in the example embodiment of FIG. 13, the physical cell 1310 (0) is read only once to provide the data 1300 for the first stage programming operation 1302, and the memory management circuit 602 may temporarily not erase the physical cell 1310 (0) according to the read information corresponding to the physical cell 1310 (0). In the example embodiment of FIG. 15, the physical cell 1310 (0) is read a second time to provide the data 1300 for the second stage programming operation 1502, so the memory management circuit 602 may erase the physical cell 1310 (0) according to the read information corresponding to the physical cell 1310 (0).

It should be noted that in the above exemplary embodiment, a certain memory cell subjected to the multi-stage programming operation may store 3 or 4 bits. However, in another exemplary embodiment, a certain memory cell subjected to the multi-stage programming operation may store more or less bits (e.g., 2 or 8 bits), which is not limited by the present invention. In addition, a multi-stage programming operation may include more stages of programming operations, and is not limited to the first-stage programming operation and the second-stage programming operation. For example, in an exemplary embodiment of fig. 8, the multi-stage programming operations that may be considered to be performed include a first-stage programming operation, a second-stage programming operation, and a third-stage programming operation. The first phase programming operation is used to program the memory cell to the

states

801 and 802. The second stage of programming is used to program the memory cells to the states 811-814. The third phase of programming is used to program memory cells to states 821-828. In an exemplary embodiment, a physical unit may also be read more times (e.g., 3 times or 4 times) to perform a third stage programming operation or a fourth stage programming operation.

Referring to fig. 18, in step S1810, a data merging operation is started. In step S1820, a data merging operation is performed. Step S1820 includes steps S1821 to S1824. In step S1821, first data is read from the first entity unit via a first read operation. In step S1822, a first-stage programming operation is performed on the second entity unit according to the first data. In step S1823, the first data is read from the first physical unit again via the second read operation. In step S1824, a second-stage programming operation is performed on the second physical unit according to the first data read via the second read operation. In step S1830, the data integration operation is ended.

However, the steps in fig. 18 are described in detail above, and will not be described again here. It should be noted that each step in fig. 18 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 18 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, in the data merging operation, the same data in the first physical unit may be read at least twice to complete the multi-stage programming operation for the second physical unit according to the data read by the different reading operations. Therefore, even if the available space of the buffer memory is reduced due to cost consideration, the multi-stage programming operation of a single physical unit can be successfully completed without additionally increasing the capacity of the buffer memory. In an exemplary embodiment, the foregoing mechanism for performing multiple data reading operations on the same physical unit to complete the multi-stage programming operation can also effectively improve the compatibility of the memory storage device with respect to the memory controller (or control chip) with smaller capacity of the buffer memory.

Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather, it should be apparent to one skilled in the art that various changes and modifications can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A data consolidation method for a memory storage device comprising a plurality of physical units, and the data consolidation method comprising:

performing a data merge operation to store valid data collected from the source node to the reclamation node,

wherein the source node comprises at least a first entity unit of the plurality of entity units, the recovery node comprises a second entity unit of the plurality of entity units, and

the data merging operation includes:

reading first data from the at least one first physical unit via a first read operation;

performing a first-stage programming operation on the second entity unit according to the first data;

after the first-stage programming operation is executed, the first data is read from the at least one first entity unit again through a second reading operation; and

and performing a second-stage programming operation on the second entity unit according to the first data read through the second reading operation.

2. The data consolidation method of claim 1, wherein the source node further comprises at least a third entity unit of the plurality of entity units, the reclamation node further comprises a fourth entity unit of the plurality of entity units, and the data consolidation operation further comprises:

reading second data from the at least one third entity unit; and

and programming the fourth entity unit according to the second data between the first-stage programming operation and the second-stage programming operation.

3. The data consolidation method of claim 1, wherein the data consolidation operation further comprises:

temporarily storing the first data read through the first read operation in a buffer memory to provide the first data for the first stage programming operation;

temporarily storing second data in the buffer memory, and the second data overwrites at least a portion of the first data read via the first read operation in the buffer memory; and

the first data read via the second read operation is suspended in the buffer memory to provide the first data for the second stage programming operation.

4. The data consolidation method of claim 1, further comprising:

recording read information in a management table, wherein the read information reflects whether the at least one first physical unit is read by at least one of the first read operation and the second read operation; and

and erasing the at least one first entity unit according to the read information.

5. The data consolidation method according to claim 1, wherein the second entity unit is programmed to store the first data via the first stage programming operation and the second stage programming operation in sequence.

6. The data consolidation method according to claim 1, wherein the first stage programming operation and the second stage programming operation belong to a multi-stage programming operation, and one memory cell of the second entity unit programmed by the multi-stage programming operation stores not less than 3 bits.

7. The data consolidation method of claim 1, further comprising:

temporarily storing the first data read by the first reading operation or the second reading operation in a buffer memory,

wherein the second entity unit has a basic capacity and the available capacity of the buffer memory is less than twice the basic capacity.

8. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module including a plurality of physical units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to perform a data merging operation to store valid data collected from the source node to the reclamation node,

the source node includes at least one first entity unit of the plurality of entity units, the recovery node includes a second entity unit of the plurality of entity units, and

the data merging operation includes:

sending a first read instruction sequence to instruct to read first data from the at least one first entity unit via a first read operation;

transmitting a first write instruction sequence to instruct the second entity unit to execute a first stage programming operation according to the first data;

after the first-stage programming operation is performed, sending a second read instruction sequence to instruct to read the first data from the at least one first entity unit again through a second read operation; and

A second sequence of write instructions is sent to instruct a second-stage programming operation to be performed on the second physical unit in accordance with the first data read via the second read operation.

9. The memory storage device of claim 8, wherein the source node further comprises at least a third entity of the plurality of entity units, the reclamation node further comprises a fourth entity of the plurality of entity units, and the data consolidation operation further comprises:

sending a third read instruction sequence to instruct to read second data from the at least one third entity unit; and

a third sequence of write instructions is sent between the first phase programming operation and the second phase programming operation to instruct programming of the fourth entity unit according to the second data.

10. The memory storage device of claim 8, wherein the data merge operation further comprises:

11. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to record read information in a management table and erase the at least one first physical unit according to the read information, wherein the read information reflects whether the at least one first physical unit is read by at least one of the first read operation and the second read operation.

12. The memory storage device of claim 8, wherein the second entity unit is programmed to store the first data via the first phase programming operation and the second phase programming operation in sequence.

13. The memory storage device of claim 8, wherein the first-stage programming operation and the second-stage programming operation belong to a multi-stage programming operation, and one memory cell of the second physical unit programmed by the multi-stage programming operation stores not less than 3 bits.

14. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to temporarily store the first data read via the first read operation or the second read operation in a buffer memory,

15. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, wherein the memory control circuit unit comprises:

a host interface for connecting to a host system;

a memory interface to connect to the rewritable non-volatile memory module; and

a memory management circuit coupled to the host interface and the memory interface,

wherein the memory management circuit is configured to perform a data merge operation to store valid data collected from the source node to the reclamation node,

The data merging operation includes:

16. The memory control circuit unit of claim 15, wherein the source node further comprises at least a third entity unit of the plurality of entity units, the reclamation node further comprises a fourth entity unit of the plurality of entity units, and the data merge operation further comprises:

17. The memory control circuit unit of claim 15, further comprising a buffer memory, wherein the buffer memory is connected to the memory management circuit, and the data merge operation further comprises:

temporarily storing the first data read via the first read operation in the buffer memory to provide the first data for the first stage programming operation;

18. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to record read information in a management table and erase the at least one first physical unit according to the read information, wherein the read information reflects whether the at least one first physical unit is read by at least one of the first read operation and the second read operation.

19. The memory control circuit unit of claim 15, wherein the second entity unit is programmed to store the first data via the first phase programming operation and the second phase programming operation in sequence.

20. The memory control circuit unit of claim 15, wherein the first-stage programming operation and the second-stage programming operation belong to a multi-stage programming operation, and one memory cell of the second physical unit programmed by the multi-stage programming operation stores not less than 3 bits.

21. The memory control circuit unit of claim 15, further comprising a buffer memory, wherein the buffer memory is connected to the memory management circuit, and the memory management circuit is further configured to store the first data read via the first read operation or the second read operation temporarily in the buffer memory,