CN107015846A - A kind of emulation mode and device for realizing processor simulation core - Google Patents
A kind of emulation mode and device for realizing processor simulation core Download PDFInfo
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- CN107015846A CN107015846A CN201710243286.XA CN201710243286A CN107015846A CN 107015846 A CN107015846 A CN 107015846A CN 201710243286 A CN201710243286 A CN 201710243286A CN 107015846 A CN107015846 A CN 107015846A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
- G06F9/45516—Runtime code conversion or optimisation
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Abstract
The embodiment of the invention discloses a kind of emulation mode and device for realizing processor simulation core.This method includes：S1. program counter value is obtained according to target simulator program；S2. emulator command is obtained from memory according to described program Counter Value；If S3. the emulator command is break-poing instruction, breakpoint processing is carried out according to the simulation status that breakpoint performs type and the simulated core；S4. running status is switched to preset operating state by the simulated core；If S5. the emulator command is non-break-poing instruction, the emulator command is performed, returns and performs step S1, until obtaining simulation result.The emulation mode for realizing processor simulation core that the application is provided, adds break-poing instruction, the debugging of program can be with segment processing, so as to improve the flexibility of simulation process in simulated program.
Description
Technical field
The present embodiments relate to simulation process technology field, more particularly to a kind of emulation side for realizing processor simulation core
Method and device.
Background technology
Processor simulation core virtual operation system is that the software systems of full simulation can be carried out to embedded hardware system.
User can dry run embedded software on this system, without corresponding hardware embedded software can be carried out test with
Debugging.By using the system, user not only can greatly shorten the embedded software lead time, and can avoid high
Subtest hardware development expense, greatly reduce system cost.The system can be widely applied to Aeronautics and Astronautics, weapon
The embedded system development such as equipment, automobile, robot, Industry Control field, lifts labor productivity, the reduction of these industries
Cost, make its goods more competitive.
In the prior art, it is flexible during debugging operations when being emulated using processor simulation core virtual operation system
Property is poor.
The content of the invention
The present invention provides a kind of emulation mode and device for realizing processor simulation core, to improve the flexible of simulation process
Property.
In a first aspect, the embodiments of the invention provide a kind of emulation mode for realizing processor simulation core, this method includes：
S1. program counter value is obtained according to target simulator program；
S2. emulator command is obtained from memory according to described program Counter Value；
If S3. the emulator command is break-poing instruction, the emulation shape of type and the simulated core is performed according to breakpoint
State carries out breakpoint processing；
S4. running status is switched to preset operating state by the simulated core；
If S5. the emulator command is non-break-poing instruction, the emulator command is performed, returns and performs step S1, directly
To acquisition simulation result.
Further, if the emulator command is break-poing instruction, type and the simulated core are performed according to breakpoint
Simulation status carries out breakpoint processing, including：
If the non-break-poing instruction of code behavior currently performed, configures at least one break-poing instruction, by the simulated core
Simulation status be set to continuous state；It is current line to set initial program Counter Value, starts the simulated core；
If the code behavior break-poing instruction currently performed, it is single step state to set the emulation nuclear state, is set just
Beginning program counter value is current line, starts the simulated core, at least one break-poing instruction is configured, by the emulation of the simulated core
State is set to continuous state, and it is current line to set initial program Counter Value, starts the simulated core；
Recover at least one described break-poing instruction to instruct to be former.
Further, if the emulator command is break-poing instruction, type and the simulated core are performed according to breakpoint
Simulation status carries out breakpoint processing, including：
If the non-break-poing instruction of code behavior currently performed, configures at least one break-poing instruction, by the simulated core
Simulation status be set to single step state；It is current line to set initial program Counter Value, starts the simulated core；
If the code behavior break-poing instruction currently performed, it is single step state to set the emulation nuclear state, is set just
Beginning program counter value is current line, starts the simulated core；
Recover at least one described break-poing instruction to instruct to be former.
Further, described at least one break-poing instruction of configuration, including：
Break-poing instruction is configured by debugging acid GDB and simulated core.
Further, it is described that emulator command is obtained from memory according to described program Counter Value, including：
Binary command is obtained from memory according to described program Counter Value；
Judge whether simulation process exception occurs；
If there is not exception, row decoding is entered to the binary command, emulator command is obtained.
Second aspect, the embodiment of the present invention additionally provides a kind of simulator for realizing processor simulation core, the device bag
Include：
Program counter value acquisition module, for obtaining program counter value according to target simulator program；
Emulator command acquisition module, for obtaining emulator command from memory according to described program Counter Value；
Breakpoint processing module, for when the emulator command is break-poing instruction, type to be performed and described imitative according to breakpoint
The simulation status of eucaryon carries out breakpoint processing；
Running status handover module, preset operating state is switched to for the simulated core by running status；
Emulator command performing module, for when the emulator command is non-break-poing instruction, performing the emulator command.
Further, the breakpoint processing module, is additionally operable to：
If the non-break-poing instruction of code behavior currently performed, configures at least one break-poing instruction, by the simulated core
Simulation status be set to continuous state；It is current line to set initial program Counter Value, starts the simulated core；
If the code behavior break-poing instruction currently performed, it is single step state to set the emulation nuclear state, is set just
Beginning program counter value is current line, starts the simulated core, at least one break-poing instruction is configured, by the emulation of the simulated core
State is set to continuous state, and it is current line to set initial program Counter Value, starts the simulated core；
Recover at least one described break-poing instruction to instruct to be former.
Further, the breakpoint processing module, is additionally operable to：
If the non-break-poing instruction of code behavior currently performed, configures at least one break-poing instruction, by the simulated core
Simulation status be set to single step state；It is current line to set initial program Counter Value, starts the simulated core；
If the code behavior break-poing instruction currently performed, it is single step state to set the emulation nuclear state, is set just
Beginning program counter value is current line, starts the simulated core；
Recover at least one described break-poing instruction to instruct to be former.
Further, the breakpoint processing module, is additionally operable to：
Break-poing instruction is configured by debugging acid GDB and simulated core.
Further, the emulator command acquisition module, is additionally operable to：
Binary command is obtained from memory according to described program Counter Value；
Judge whether simulation process exception occurs；
If there is not exception, row decoding is entered to the binary command, emulator command is obtained.
The embodiment of the present invention, obtains program counter value, then according to program counter according to target simulator program first
Value obtains emulator command from memory, if emulator command is break-poing instruction, type and simulated core are performed according to breakpoint
Simulation status carries out breakpoint processing, and then running status is switched to preset operating state by simulated core, if emulator command is non-
Break-poing instruction, then perform emulator command, until obtaining simulation result.In the prior art, virtually transported using processor simulation core
, it is necessary to which whole program can just be debugged after the completion of performing when row system is emulated so that flexibility during debugging operations
Difference.In the application, break-poing instruction is added in simulated program, the debugging of program can be with segment processing, so as to improve simulation process
Flexibility.
Brief description of the drawings
Fig. 1 is a kind of flow chart of emulation mode for realizing processor simulation core in the embodiment of the present invention one；
Fig. 2 is a kind of structural representation of simulator for realizing processor simulation core in the embodiment of the present invention two.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, in order to just
Part related to the present invention rather than entire infrastructure are illustrate only in description, accompanying drawing.
Embodiment one
Fig. 1 is a kind of flow chart for emulation mode for realizing processor simulation core that the embodiment of the present invention one is provided, this reality
Apply example to be applicable to using the situation that check program is emulated is emulated, this method can be performed by server, such as Fig. 1 institutes
Show, this method specifically includes following steps：
S1, program counter value is obtained according to target simulator program.
Wherein, program counter (Program Counter, PC) can be used for the address of storage instruction.In the present embodiment,
When target program is performed, PC initial value is the address of first instruction of target program, and when order is performed, server is pressed first
An instruction is taken out from internal memory according to the signified IAes of PC, the instruction is then analyzed and perform, while the sensing of PC values is next
The instruction that bar will be performed.
Wherein, the renewal of PC values need to be updated according to the structure of streamline.The structure of streamline can include one-level, three
Level, Pyatyi and seven grades etc..Exemplary, by taking three class pipeline structure as an example, the storage variable in three class pipeline includes fetching
Section, decoding section and execution section., it is necessary to update streamline before each execute instruction in emulation, needs consider as follows during renewal
Two kinds of situations.
When streamline is under normal circumstances, it is necessary to the filling streamline of order before each execute instruction.Filling stream
During waterline, first, PC values move forward 4 bytes, point to the address of the next instruction for entering streamline；Then, currently hold
The address value of row instruction can also move forward 4 bytes, obtain the next instruction for needing to perform, meanwhile, it is in current pipeline
The instruction in decoding stage can become to be in the instruction in fetching stage in last time streamline；Finally, fetching section will take from internal memory
Instruction newly is obtained, streamline is filled into.
, it is necessary to refill streamline after streamline is blocked.The content having in streamline will be washed,
Need again from fetching at current program counter value, the then fetching of order 3 times are sequentially filled into streamline, formed newly
Pipeline organization.
Optionally, it is necessary to consider following several situations respectively when adjustment programme Counter Value：
When emulator command is jump instruction, program counter value should be equal to current program counter value plus skew
Field.Moreover, need to refresh streamline again before execute instruction next time.
When emulator command is interrupt instruction, and interrupts and do not occur in break-poing instruction.Interrupt after producing, program will arrive new
Fetching, execution at address, accordingly, it would be desirable to change program counter value.But, it is necessary to return to continuation after interrupt processing is complete
Interrupt IA when producing.
When emulator command is interrupt instruction, and interrupts and occur in break-poing instruction.When interrupting return, the institute of PC values -8 is back to
The address of sensing, rather than the address that PC values -4 are pointed to.
S2, emulator command is obtained according to program counter value from memory.
The address that server is pointed to according to program counter value obtains emulator command from memory.It is preferred that, according to journey
The process that sequence Counter Value obtains emulator command from memory can be that two are obtained from memory according to program counter value
System is instructed, and judges whether simulation process exception occurs, if there is not exception, row decoding is entered to binary command, is obtained
Emulator command.Wherein, the process of decoding can be the process parsed to binary command.
Optionally, if simulation process has abnormal generation, simulated core switches to abnormal patterns.Switch to the mode of abnormal patterns
Including：Switch mode, switching register and switching designated mode PC values.After the completion of abnormality processing, it is true that simulated core returns to orthoform
Process, reacquires PC values and continues to emulate.
Optionally, if abnormal to interrupt, simulated core switches to interrupt mode.After the completion of interrupt processing, then return and interrupt,
Simulated core continues to emulate since the place of interruption.
S3, if emulator command is break-poing instruction, is broken according to the simulation status that breakpoint performs type and simulated core
Point processing.
Wherein, break-poing instruction can be off the instruction of simulation flow.The execution type of breakpoint can include continuously performing
Performed with single step.The instruction of program interrupt point is user to be needed the instruction of some positions in program replacing with breakpoint and refers to according to emulation
Make and come.When the emulator command that decoding is obtained is break-poing instruction, simulation flow is marked as " stopping " state, exits this
Simulation flow.Meanwhile, breakpoint processing is carried out according to the simulation status of the execution type of breakpoint and simulated core.
It is preferred that, the method for the simulation status progress breakpoint processing of type and simulated core is performed according to breakpoint can be included such as
Lower two kinds of situations.
When breakpoint perform type for continuously perform when, if the non-break-poing instruction of code behavior currently performed, configure to
A few break-poing instruction, continuous state is set to by the simulation status of simulated core；It is current line to set initial program Counter Value,
Start simulated core.If the code behavior break-poing instruction currently performed, it is single step state to set emulation nuclear state, sets initial
Program counter value is current line, starts simulated core, configures at least one break-poing instruction, the simulation status of simulated core is set to
Continuous state, it is current line to set initial program Counter Value, starts simulated core.Recover at least one break-poing instruction for original to refer to
Order.
When breakpoint perform type be single step perform when, if the non-break-poing instruction of code behavior currently performed, configure to
A few break-poing instruction, single step state is set to by the simulation status of simulated core；It is current line to set initial program Counter Value,
Start simulated core.If the code behavior break-poing instruction currently performed, it is single step state to set emulation nuclear state, sets initial
Program counter value is current line, starts simulated core.Recover at least one break-poing instruction to instruct to be former.
It is preferred that, configuring the mode of at least one break-poing instruction can be, by debugging acid GDB and simulated core to breakpoint
Instruction is configured.
Running status is switched to preset operating state by S4, simulated core.
Wherein, running status can include continuous running status and single step performs state.User can be according to emulation demand
Switchover operation state.
S5, if emulator command is non-break-poing instruction, performs emulator command, returns and perform step S1, until being imitated
True result.
Wherein, non-break-poing instruction can include jump instruction, access instruction and visit register instruction etc..When decoding result is
During jump instruction, if not redirecting, performed according to current order；If redirecting, current program counter value needs biasing
Move the program counter value after field is redirected.When it is access instruction to decode result, then the memory headroom of access instruction.When
Result is decoded to access register instruction, then accesses and specifies register.After simulated core has performed emulator command, then S1 is returned to,
Program counter value is reacquired, circulation carries out the process of fetching-decoding-execution, the simulation result until obtaining program.
The technical scheme of the present embodiment, obtains program counter value, then according to program according to target simulator program first
Counter Value obtains emulator command from memory, if emulator command is break-poing instruction, and type is performed and imitative according to breakpoint
The simulation status of eucaryon carries out breakpoint processing, and then running status is switched to preset operating state by simulated core, if emulation refers to
Make as non-break-poing instruction, then perform emulator command, until obtaining simulation result.In the prior art, processor simulation core is being utilized
, it is necessary to which whole program can just be debugged after the completion of performing when virtual operation system is emulated so that during debugging operations
Very flexible.In the application, break-poing instruction is added in simulated program, the debugging of program can be with segment processing, so as to improve imitative
The flexibility of true process.
Embodiment two
Fig. 2 is a kind of structural representation for simulator for realizing processor simulation core that the embodiment of the present invention two is provided.
As shown in Fig. 2 the device includes：Program counter value acquisition module 210, emulator command acquisition module 220, breakpoint processing module
230, running status handover module 240 and emulator command performing module 250.
Program counter value acquisition module 210, for obtaining program counter value according to target simulator program；
Emulator command acquisition module 220, for obtaining emulator command from memory according to program counter value；
Breakpoint processing module 230, for when emulator command is break-poing instruction, type and simulated core to be performed according to breakpoint
Simulation status carries out breakpoint processing；
Running status handover module 240, preset operating state is switched to for simulated core by running status；
Emulator command performing module 250, for when emulator command is non-break-poing instruction, performing emulator command.
Further, breakpoint processing module 230, is additionally operable to：
If the non-break-poing instruction of code behavior currently performed, configures at least one break-poing instruction, by the imitative of simulated core
True state is set to continuous state；It is current line to set initial program Counter Value, starts simulated core；
If the code behavior break-poing instruction currently performed, it is single step state to set emulation nuclear state, sets initial journey
Sequence Counter Value is current line, starts simulated core, configures at least one break-poing instruction, and the simulation status of simulated core is set to connect
Continuous state, it is current line to set initial program Counter Value, starts simulated core；
Recover at least one break-poing instruction to instruct to be former.
Further, breakpoint processing module 230, is additionally operable to：
If the non-break-poing instruction of code behavior currently performed, configures at least one break-poing instruction, by the imitative of simulated core
True state is set to single step state；It is current line to set initial program Counter Value, starts simulated core；
If the code behavior break-poing instruction currently performed, it is single step state to set emulation nuclear state, sets initial journey
Sequence Counter Value is current line, starts simulated core；
Recover at least one break-poing instruction to instruct to be former.
Further, breakpoint processing module 230, is additionally operable to：
Break-poing instruction is configured by debugging acid GDB and simulated core.
Further, emulator command acquisition module 220, is additionally operable to：
Binary command is obtained from memory according to program counter value；
Judge whether simulation process exception occurs；
If there is not exception, row decoding is entered to binary command, emulator command is obtained.
The said goods can perform the method that any embodiment of the present invention is provided, and possess the corresponding functional module of execution method
And beneficial effect.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art it is various it is obvious change,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although the present invention is carried out by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
Other more equivalent embodiments can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (10)
1. a kind of emulation mode for realizing processor simulation core, it is characterised in that including：
S1. program counter value is obtained according to target simulator program；
S2. emulator command is obtained from memory according to described program Counter Value；
If S3. the emulator command is break-poing instruction, entered according to the simulation status that breakpoint performs type and the simulated core
The processing of row breakpoint；
S4. running status is switched to preset operating state by the simulated core；
If S5. the emulator command is non-break-poing instruction, the emulator command is performed, returns and performs step S1, until obtaining
Obtain simulation result.
2. the emulation mode according to claim 1 for realizing processor simulation core, it is characterised in that if the emulation refers to
Make as break-poing instruction, then the simulation status for performing type and the simulated core according to breakpoint carries out breakpoint processing, including：
If the non-break-poing instruction of code behavior currently performed, configures at least one break-poing instruction, by the imitative of the simulated core
True state is set to continuous state；It is current line to set initial program Counter Value, starts the simulated core；
If the code behavior break-poing instruction currently performed, it is single step state to set the emulation nuclear state, sets initial journey
Sequence Counter Value is current line, starts the simulated core, at least one break-poing instruction is configured, by the simulation status of the simulated core
Continuous state is set to, it is current line to set initial program Counter Value, starts the simulated core；
Recover at least one described break-poing instruction to instruct to be former.
3. the emulation mode according to claim 1 for realizing processor simulation core, it is characterised in that if the emulation refers to
Make as break-poing instruction, then the simulation status for performing type and the simulated core according to breakpoint carries out breakpoint processing, including：
If the non-break-poing instruction of code behavior currently performed, configures at least one break-poing instruction, by the imitative of the simulated core
True state is set to single step state；It is current line to set initial program Counter Value, starts the simulated core；
If the code behavior break-poing instruction currently performed, it is single step state to set the emulation nuclear state, sets initial journey
Sequence Counter Value is current line, starts the simulated core；
Recover at least one described break-poing instruction to instruct to be former.
4. the emulation mode for realizing processor simulation core according to Claims 2 or 3, it is characterised in that the configuration is extremely
A few break-poing instruction, including：
Break-poing instruction is configured by debugging acid GDB and simulated core.
5. the emulation mode according to claim 1 for realizing processor simulation core, it is characterised in that described according to the journey
Sequence Counter Value obtains emulator command from memory, including：
Binary command is obtained from memory according to described program Counter Value；
Judge whether simulation process exception occurs；
If there is not exception, row decoding is entered to the binary command, emulator command is obtained.
6. a kind of simulator for realizing processor simulation core, it is characterised in that including：
Program counter value acquisition module, for obtaining program counter value according to target simulator program；
Emulator command acquisition module, for obtaining emulator command from memory according to described program Counter Value；
Breakpoint processing module, for when the emulator command is break-poing instruction, type and the simulated core to be performed according to breakpoint
Simulation status carry out breakpoint processing；
Running status handover module, preset operating state is switched to for the simulated core by running status；
Emulator command performing module, for when the emulator command is non-break-poing instruction, performing the emulator command.
7. the simulator according to claim 6 for realizing processor simulation core, it is characterised in that the breakpoint handles mould
Block, is additionally operable to：
If the non-break-poing instruction of code behavior currently performed, configures at least one break-poing instruction, by the imitative of the simulated core
True state is set to continuous state；It is current line to set initial program Counter Value, starts the simulated core；
If the code behavior break-poing instruction currently performed, it is single step state to set the emulation nuclear state, sets initial journey
Sequence Counter Value is current line, starts the simulated core, at least one break-poing instruction is configured, by the simulation status of the simulated core
Continuous state is set to, it is current line to set initial program Counter Value, starts the simulated core；
Recover at least one described break-poing instruction to instruct to be former.
8. the simulator according to claim 6 for realizing processor simulation core, it is characterised in that the breakpoint handles mould
Block, is additionally operable to：
If the non-break-poing instruction of code behavior currently performed, configures at least one break-poing instruction, by the imitative of the simulated core
True state is set to single step state；It is current line to set initial program Counter Value, starts the simulated core；
If the code behavior break-poing instruction currently performed, it is single step state to set the emulation nuclear state, sets initial journey
Sequence Counter Value is current line, starts the simulated core；
Recover at least one described break-poing instruction to instruct to be former.
9. the simulator for realizing processor simulation core according to claim 7 or 8, it is characterised in that at the breakpoint
Module is managed, is additionally operable to：
Break-poing instruction is configured by debugging acid GDB and simulated core.
10. the simulator according to claim 6 for realizing processor simulation core, it is characterised in that the emulator command
Acquisition module, is additionally operable to：
Binary command is obtained from memory according to described program Counter Value；
Judge whether simulation process exception occurs；
If there is not exception, row decoding is entered to the binary command, emulator command is obtained.
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| CN201710243286.XA CN107015846B (en) | 2017-04-14 | 2017-04-14 | Simulation method and device for realizing eukaryon simulation of processor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108182083A (en) * | 2017-12-06 | 2018-06-19 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of fetching decoding circuit for supporting debugging breakpoints |
| CN114442506A (en) * | 2021-12-06 | 2022-05-06 | 埃夫特智能装备股份有限公司 | Simulation debugging platform based on virtual robot controller and debugging method thereof |
| CN115018466A (en) * | 2022-06-28 | 2022-09-06 | 北京世冠金洋科技发展有限公司 | Simulation control method and device, storage medium and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050066313A1 (en) * | 2003-09-18 | 2005-03-24 | International Business Machines Corporation | Run into function |
| CN101178685A (en) * | 2007-09-27 | 2008-05-14 | 上海大学 | Enhancement type microprocessor piece on-chip dynamic state tracking method with special function register breakpoints |
| CN104239201A (en) * | 2013-06-20 | 2014-12-24 | 上海博达数据通信有限公司 | Memory read-write monitoring method in flexible single-step system |
-
2017
- 2017-04-14 CN CN201710243286.XA patent/CN107015846B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050066313A1 (en) * | 2003-09-18 | 2005-03-24 | International Business Machines Corporation | Run into function |
| CN101178685A (en) * | 2007-09-27 | 2008-05-14 | 上海大学 | Enhancement type microprocessor piece on-chip dynamic state tracking method with special function register breakpoints |
| CN104239201A (en) * | 2013-06-20 | 2014-12-24 | 上海博达数据通信有限公司 | Memory read-write monitoring method in flexible single-step system |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108182083A (en) * | 2017-12-06 | 2018-06-19 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of fetching decoding circuit for supporting debugging breakpoints |
| CN108182083B (en) * | 2017-12-06 | 2021-12-24 | 中国航空工业集团公司西安航空计算技术研究所 | Instruction fetching decoding circuit supporting breakpoint debugging |
| CN114442506A (en) * | 2021-12-06 | 2022-05-06 | 埃夫特智能装备股份有限公司 | Simulation debugging platform based on virtual robot controller and debugging method thereof |
| CN115018466A (en) * | 2022-06-28 | 2022-09-06 | 北京世冠金洋科技发展有限公司 | Simulation control method and device, storage medium and electronic equipment |
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