CN108182083A - A kind of fetching decoding circuit for supporting debugging breakpoints - Google Patents

A kind of fetching decoding circuit for supporting debugging breakpoints Download PDF

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Publication number
CN108182083A
CN108182083A CN201711281084.0A CN201711281084A CN108182083A CN 108182083 A CN108182083 A CN 108182083A CN 201711281084 A CN201711281084 A CN 201711281084A CN 108182083 A CN108182083 A CN 108182083A
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Prior art keywords
breakpoint
register
instruction
module
address
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CN201711281084.0A
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CN108182083B (en
Inventor
牛少平
魏艳艳
韩鹏
韩一鹏
邓艺
郝冲
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Xian Aeronautics Computing Technique Research Institute of AVIC
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Xian Aeronautics Computing Technique Research Institute of AVIC
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3644—Software debugging by instrumenting at runtime
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/327—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for interrupts

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The invention belongs to technical field of integrated circuits, are related to a kind of fetching decoding circuit for supporting debugging breakpoints, including：Software interface register module 1, breakpoint identification module 2, breakpoint processing module 3.It is an advantage of the invention that：1st, debugging breakpoints circuit is simple, and break point debugging function does not influence normal fetching decoding circuit；2nd, break point debugging function facilitates programmer to carry out the exploitation and debugging of stainer program, accelerates the development progress of software stainer application program and the verification progress of hardware design.

Description

A kind of fetching decoding circuit for supporting debugging breakpoints
Technical field
The invention belongs to technical field of integrated circuits, are related to a kind of fetching decoding circuit for supporting debugging breakpoints.
Background technology
For convenience of being observed as needed to data in software running process is dyed, facilitate programmer's exploitation, debugging Dyeing procedure in stainer hardware design, adds in break point debugging function.
Invention content
The purpose of the present invention is：
The present invention provides a kind of fetching decoding circuit for supporting debugging breakpoints, and programmer is facilitated to carry out opening for stainer program Hair and debugging, accelerate the development progress of software stainer application program and the verification progress of hardware design.
The present invention technical solution be：
A kind of fetching decoding circuit for supporting debugging breakpoints, including：Software interface register module 1, breakpoint identification module 2nd, breakpoint processing module 3；
Software interface register module 1 realizes that software enables register to breakpoint address register, breakpoint, breakpoint succession is held The read and write access of row register and breakpoint status register；It is defeated that 32 breakpoint address register values and breakpoint are enabled into register value Go out to breakpoint identification module 2；Breakpoint succession execution register value is exported to breakpoint processing module 3；
It is 1 effective that breakpoint identification module 2 enables register value to correspond to position in the breakpoint that software interface register module 1 is configured When, 32 breakpoint address registers that address and software interface register module 1 that the instruction of n items is fetched in the fetching stage are configured 31 to m in address are compared judgement；When more identical, produced according to the m-1 of breakpoint register address to 0 into row decoding The breakpoint mark of raw corresponding instruction；And by instruction breakpoint mark output to breakpoint processing module 3；
Breakpoint processing module 3 is primarily implemented in pre-decode stage and identifies progress according to the instruction breakpoint of breakpoint identification module 2 The deconsolidation process of instruction, and stop decoding and firing order, breakpoint status is generated to software interface register module 1, treats software It inquires the breakpoint status software to be read out the corresponding program storage of the breakpoint, obtains the data that need to be observed；Also may be used simultaneously Register value is performed with the breakpoint succession given according to software interface register module 1, instruction is continued to execute at the breakpoint.
In software interface register module 1, breakpoint address register can set it is multiple, breakpoint enable register bit wide and The number of breakpoint address register corresponds, breakpoint enable register corresponding positions section it is effective when the breakpoint address register that sets Just effectively.
In software interface register module 1, breakpoint succession performs register and the bit wide of breakpoint status register and can set Multidigit, every represents that a kind of interruption of program continues and occurs.
In breakpoint identification module 2, the breakpoint mark of every instruction is transmitted down with the processing stage of instruction.
In breakpoint processing module 3,2 instruction a and b of pre-decode when the breakpoint of b being instructed to identify effective, need to carry out instruction and tear open Point.
In breakpoint processing module 3,2 instruction a and b are decoded, wherein when the breakpoint mark of any one instruction is effective, are just stopped The decoding and transmitting only instructed.
2m=n, m=[1,31].
It is an advantage of the invention that：
1st, debugging breakpoints circuit is simple, and break point debugging function does not influence normal fetching decoding circuit；
2nd, break point debugging function facilitates programmer to carry out the exploitation and debugging of stainer program, accelerates software stainer The development progress of application program and the verification progress of hardware design.
Description of the drawings
Fig. 1 is the circuit diagram of the present invention.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to embodiments, to the present invention It is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not used to Limit the present invention.
As shown in Figure 1, a kind of fetching decoding circuit for supporting debugging breakpoints, mainly by software interface register module 1, disconnected Point identification module 2, breakpoint processing module 3 form.
Software interface register module 1 mainly realizes that software is enabled and posted to breakpoint address register (bit wide 32), breakpoint Storage, breakpoint succession perform the read and write access of register and breakpoint status register；Breakpoint address register value and breakpoint are made Energy register value is exported to breakpoint identification module 2；Breakpoint succession execution register value is exported to breakpoint processing module 3；Wherein, Breakpoint address register can set it is multiple, breakpoint enable register bit wide and breakpoint address register number correspond, Breakpoint enable register corresponding positions section it is effective when the breakpoint address register that sets it is just effective；Breakpoint succession performs register and breaks The bit wide of dotted state register can set multidigit, and every represents that a kind of interruption of program continues and occurs.
The breakpoint that breakpoint identification module 2 is primarily implemented in the configuration of software interface register module 1 enables register value correspondence When position is 1 effective, by the address that instruction is fetched in the fetching stage (address corresponds to the instruction of n items) and software interface register module The breakpoint address register high address ([31 of 1 configuration:M]) judgement is compared, wherein 2m=n, m=[1,31]；Compare phase Meanwhile according to breakpoint register low order address [m-1:0] the breakpoint mark of corresponding instruction is generated into row decoding；And the instruction is broken Point identification is exported to breakpoint processing module 3；The breakpoint mark of every instruction is transmitted down with the processing stage of instruction.
Breakpoint processing module 3 is primarily implemented in pre-decode stage and identifies progress according to the instruction breakpoint of breakpoint identification module 2 The deconsolidation process of instruction, and stop decoding and firing order, breakpoint status is generated to software interface register module 1, treats software Inquire the breakpoint status (software is read out the corresponding program storage of the breakpoint, obtains the data that need to be observed)；Simultaneously The breakpoint succession that can be given according to software interface register module 1 performs register value and instruction is continued to execute at the breakpoint.
2 instructions of pre-decode (instruction a and b) in breakpoint processing module 3, when the breakpoint of b being instructed to identify effective, pre-decode needs Carry out instruction fractionation；During decoding, wherein when the breakpoint mark of any one instruction is effective, just stop decoding and the hair of the instruction It penetrates.
Embodiment
As shown in Figure 1, a kind of fetching decoding circuit for supporting debugging breakpoints, mainly by software interface register module 1, disconnected Point identification module 2, breakpoint processing module 3 form.
Software interface register module 1 mainly realize software breakpoint address register, breakpoint are enabled register, breakpoint after The continuous read and write access for performing register, breakpoint status register；It is defeated that breakpoint address register value and breakpoint are enabled into register value Go out to breakpoint identification module 2；Breakpoint succession execution register value is exported to breakpoint processing module 3；Wherein, breakpoint address is deposited Device sets 2, respectively breakpoint address register 1 and breakpoint address register 2, and the bit wide that breakpoint enables register is 2, high-order Corresponding breakpoint address register 2, low level correspond to breakpoint address register 1, breakpoint enable register corresponding positions section it is effective when set Breakpoint address register just it is effective；It is 8 that breakpoint succession, which performs register and the bit wide of breakpoint status register, every table Show that a kind of interruption of program continues and occurs.
The breakpoint that breakpoint identification module 2 is primarily implemented in the configuration of software interface register module 1 enables register value correspondence When position is 1 effective, the address (address corresponds to 8 instructions) of instruction and software interface register module will be fetched in the fetching stage The breakpoint address register high address ([31 of 1 configuration:3]) it is compared judgement；It is low according to breakpoint register when more identical Bit address [2:0] the breakpoint mark of 8 instructions is generated into row decoding；And give instruction breakpoint mark output to breakpoint processing module 3.The breakpoint mark of every instruction is transmitted down with the processing stage of instruction.
Breakpoint processing module 3 is primarily implemented in pre-decode stage and identifies progress according to the instruction breakpoint of breakpoint identification module 2 The deconsolidation process of instruction, and stop decoding and firing order, breakpoint status is generated to software interface register module 1, treats software Inquire the breakpoint status (software is read out the corresponding program storage of the breakpoint, obtains the data that need to be observed)；Simultaneously The breakpoint succession that can be given according to software interface register module 1 performs register value and instruction is continued to execute at the breakpoint.
2 instructions of pre-decode (instruction a and b) in breakpoint processing module 3, when the breakpoint of b being instructed to identify effective, pre-decode needs Carry out instruction fractionation；During decoding, wherein when the breakpoint mark of any one instruction is effective, just stop decoding and the hair of the instruction It penetrates.
For example, fetching address is 32'h8 in above-described embodiment, 8 instructions are fetched；The breakpoint address register of software setting 1 is 32'ha and breakpoint address register 2 is 32'hf, and breakpoint enables register as 2'h3, the 8 instruction marks generated in this case Know for 8'h84, that is, fetch the 3rd article in instruction instruction and the 8th article of instruction is respectively necessary for stopping decoding and transmitting.It so interrupts and adjusts It is as follows to try flow：
1) when the 3rd article and the 4th article instruction of decoding transmitting (the 3rd article is instruction a, the 4th article to instruct b) when, instruct the breakpoint of a Mark is effective, and the breakpoint of b is instructed to identify in vain, is not required to split, stops the decodings and transmitting of this 2 instructions；
2) when software detection breakpoint status register value is 8'h1, corresponding to obtain in the memory of program from the breakpoint needs to see The data of survey, it is 8'h1 then to put breakpoint succession again and perform register；
3) continue to decode transmitting since instructing the 3rd article；
4) then when decoding is emitted to the 7th article and 8 articles instruction, (the 7th article is instruction a, and the 8th article is when instructing b), to instruct a's Breakpoint mark is invalid, and the breakpoint of b is instructed to identify effectively, then splits this 2 instructions, the 7th article of transmitting, the 8th article stops transmitting；
5) software detection to breakpoint status register value be 8'h1 when, obtain the observation data of corresponding program again, then It is 8'h1 to put breakpoint succession and perform register；
6) and then, at the 8th article of instruction continue decoding transmitting.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although The present invention is explained in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that：It still may be used To modify to the technical solution recorded in foregoing embodiments or carry out equivalent replacement to which part technical characteristic； And these modification or replace, various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution spirit and Range.

Claims (7)

1. a kind of fetching decoding circuit for supporting debugging breakpoints, it is characterised in that：Including：Software interface register module (1) breaks Point identification module (2), breakpoint processing module (3)；
Software interface register module (1) realizes that software enables breakpoint address register, breakpoint in register, breakpoint succession performs The read and write access of register and breakpoint status register；32 breakpoint address register values and breakpoint are enabled into register value output Give breakpoint identification module (2)；Breakpoint succession execution register value is exported and gives breakpoint processing module (3)；
It is 1 effective that breakpoint identification module (2) enables register value to correspond to position in the breakpoint that software interface register module (1) is configured When, the address that the instruction of n items is fetched in the fetching stage and 32 breakpoint address of software interface register module (1) configuration are deposited 31 to m in device address are compared judgement；When more identical, according to the m-1 of breakpoint register address to 0 into row decoding Generate the breakpoint mark of corresponding instruction；And give instruction breakpoint mark output to breakpoint processing module (3)；
Breakpoint processing module (3) is primarily implemented in pre-decode stage and identifies progress according to the instruction breakpoint of breakpoint identification module (2) The deconsolidation process of instruction, and stop decoding and firing order, it generates breakpoint status and gives software interface register module (1), treat soft Part inquires the breakpoint status (software is read out the corresponding program storage of the breakpoint, obtains the data that need to be observed)；Simultaneously Can also register value be performed according to the breakpoint succession that software interface register module (1) is given and finger is continued to execute at the breakpoint It enables.
2. a kind of fetching decoding circuit for supporting debugging breakpoints according to claim 1, it is characterised in that：Software interface is posted In buffer module (1), breakpoint address register can set multiple, and breakpoint enables the bit wide and breakpoint address register of register Number corresponds, breakpoint enable register corresponding positions section it is effective when the breakpoint address register that sets it is just effective.
3. a kind of fetching decoding circuit for supporting debugging breakpoints according to claim 1, it is characterised in that：Software interface is posted In buffer module (1), breakpoint succession, which performs register and the bit wide of breakpoint status register, can set multidigit, and every represents a kind of The interruption of program continues and occurs.
4. a kind of fetching decoding circuit for supporting debugging breakpoints according to claim 1, it is characterised in that：Breakpoint identifies mould In block (2), the breakpoint mark of every instruction is transmitted down with the processing stage of instruction.
5. a kind of fetching decoding circuit for supporting debugging breakpoints according to claim 1, it is characterised in that：Breakpoint handles mould In block (3), 2 instruction a and b of pre-decode when the breakpoint of b being instructed to identify effective, need to carry out instruction fractionation.
6. a kind of fetching decoding circuit for supporting debugging breakpoints according to claim 1, it is characterised in that：Breakpoint handles mould In block (3), 2 instruction a and b are decoded, wherein when the breakpoint mark of any one instruction is effective, decoding and hair with regard to halt instruction It penetrates.
7. a kind of fetching decoding circuit for supporting debugging breakpoints according to claim 1, it is characterised in that：2m=n, m= [1,31].
CN201711281084.0A 2017-12-06 2017-12-06 Instruction fetching decoding circuit supporting breakpoint debugging Active CN108182083B (en)

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