TWI466025B - A method of simulating a sequential processor using a parallel processor - Google Patents

Description

Method of simulating a sequential processor using a parallel processor

The present invention relates to a method of simulating a sequential processor using a parallel processor, and more particularly to an interrupt simulator that can be performed quickly, efficiently, and correctly.

When using A processor 1 (real processor) to simulate B processor 2 (virtual processor), as shown in Fig. 1, it must use several instructions on A processor 1 to simulate a B processor 2 The instruction on the real, on the real B processor 2, the interrupt can only occur before an instruction or after an instruction, but because the A processor 1 uses the instructions of the n A processor 1 to simulate a B processor 2 instruction Therefore, the interrupt may occur in the middle of a virtual B processor 2 instruction, and the dotted line in Figure 1 represents that the interrupt includes an abnormal and normal interrupt occurrence for the B processor 2 because When the A processor 1 simulates the operation of the B processor 2, the A processor 1 must completely simulate the execution of the B processor 2 command before the interrupt can occur. And because an instruction on the B processor 2 can only have two cases when a virtual interrupt occurs: 1. This instruction has not been executed yet.

2. This instruction has been fully executed.

So when using A processor 1 to emulate B processor 2, it must be ensured that the interrupt occurs after or before a virtual B processor 2 instruction.

The most common way to solve this problem is as shown in Figure 2. It is shown that all interrupt events are temporarily not processed, and the interrupt is allowed to be (checked) at some appropriate time. The main disadvantage of this method is that on the real B processor 2, the interrupt can be made at any time. Occurs, but when using the A processor 1 to virtualize the B processor 2, the interrupt can only occur at a specific point in time, so the B processor 2 virtualized by the A processor 1 and the real B processor 2 are not completely equal. price.

The second method, as shown in Figure 3, uses the roll back mechanism. When an interrupt occurs, the system rolls back to a recent checkpoint. When the interrupt occurs, the state of the B processor 2 is immediately restored to the checkpoint. State, then interrupts can be processed immediately, or in a single-step execution/simulation technique, after execution of instruction 9 and then start processing interrupts; but the main disadvantage of this approach is that the speed of the simulation may be much slower, and the number of checkpoints is second. It is very difficult to decide with the location (for example: where to set up the check point in the for loop).

The third method, as shown in Figure 4, uses a specially designed VLIW processor as the A processor 1. Since the VLIW can complete several instructions in one clock cycle, the B processor can be used. The instruction is completed with a VLIW instruction. This ensures that during the execution of the analog B processor 2, the interrupt will only occur between any two adjacent virtual B processor instructions, and the main disadvantage of this method. The hardware design cost is very high.

The main purpose of the present invention is to make it fast, effective and correct. The interrupt simulation required for the line.

In order to achieve the above object, the present invention is a method for simulating a sequential processor using a parallel processor (this parallel processor can also be a sequential processor), which is required when a device or virtual device (device/virtual device) generates an interrupt. When the second processor executes, the first processor queries the symbol table or recalculates the interrupt point by reorganizing the translation project; and then sets an interrupt by the interrupt management unit on the first processor. Breakpoint, which is the last instruction position that the first processor is currently using to simulate the second processor instruction; and when the first processor executes the instruction to step two, the first The processor then begins to simulate the interrupt behavior of the second processor processing.

Please refer to FIG. 5, which is a schematic diagram of the processing method of the present invention. As shown in the figure: The present invention is a method of simulating a sequential processor using a parallel processor.

Step 1: When a device/virtual device 5 (storage device) generates an interrupt and needs to be executed by the second processor 4, the first processor first queries the symbol table 6 (or recalculated by recombination engineering). The instructions in the symbol table 6 that describe the second processor 4 are simulated by the instructions of the first processor 3.

Step 2: A breakpoint 71 is set by the interrupt management unit 7 on the first processor 3, and the breakpoint 71 is the current processor 3 It is being used to simulate the last instruction position of the second processor 4 instruction.

Step 3: When the first processor 3 executes the instruction described in the second step (after the execution of the instruction 9 in this embodiment), the first processor 3 starts to simulate the interrupt behavior of the processing by the second processor 4.

In this way, when the emulator running on multiple cores of the present invention can make the main components of the emulator (such as: several cpu, several devices, exceptions that may be generated on each CPU, Very common conditions, etc.) To achieve the required interrupt simulation quickly, efficiently and correctly to ensure the correctness of the simulation.

In summary, the method of using the parallel processor to simulate the sequential processor can effectively improve various shortcomings of the prior art, and can quickly, effectively and correctly perform the required interrupt simulation, thereby making the invention more progressive and practical. It is more in line with the needs of consumers, and it has indeed met the requirements of the invention patent application, and has filed a patent application according to law.

However, the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto; therefore, the simple equivalent changes and modifications made in accordance with the scope of the present invention and the contents of the invention are modified. All should remain within the scope of the invention patent.

(customized part)

A processor ‧‧1

B processor ‧‧2

(part of the invention)

First processor ‧‧3

Second processor ‧‧4

Virtual device ‧‧5

Symbol table‧‧‧6

Interrupt management unit ‧‧7

Break point ‧‧‧71

Figure 1 is a schematic diagram of the execution of virtual instructions.

Figure 2 is a schematic diagram of the processing of the critical section.

Figure 3 is a schematic diagram of the processing of the custom roll back mechanism.

Figure 4 is a schematic diagram of the processing of a conventional VLIW processor.

Fig. 5 is a schematic view showing the treatment method of the present invention.

First processor ‧‧3

Second processor ‧‧4

Virtual device ‧‧5

Symbol table‧‧‧6

Interrupt management unit ‧‧7

Break point ‧‧‧71

Claims (3)

A method for simulating a sequential processor using a parallel processor includes the following steps: Step 1: When a virtual device generates an interrupt and needs to be executed by the second processor, the first processor queries the symbol table or reorganizes The translation project recalculates; step 2: a breakpoint is set by an interrupt management unit on the first processor, and the interrupt point is currently used by the first processor to simulate the second The last instruction location of the processor instruction; and step three: when the first processor executes the instruction to step two, the first processor begins to simulate the interrupt behavior of the second processor processing. The method for simulating a sequential processor by using a parallel processor according to the first aspect of the patent application, wherein the symbol table records that the instructions of the second processor are simulated by the instructions of the first processor. The method for simulating a sequential processor using a parallel processor according to claim 1 of the scope of the patent application, wherein the recombination engineering recalculates the instructions of the second processor by the instructions of the first processor.