CN107004636B - 通孔材料选择和处理 - Google Patents

通孔材料选择和处理 Download PDF

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Publication number
CN107004636B
CN107004636B CN201580020697.1A CN201580020697A CN107004636B CN 107004636 B CN107004636 B CN 107004636B CN 201580020697 A CN201580020697 A CN 201580020697A CN 107004636 B CN107004636 B CN 107004636B
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CN
China
Prior art keywords
interconnect layer
conductive material
conductive
layer
semiconductor device
Prior art date
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Active
Application number
CN201580020697.1A
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English (en)
Chinese (zh)
Other versions
CN107004636A (zh
Inventor
J·J·朱
J·J·徐
S·S·宋
K·利姆
Z·王
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Qualcomm Inc
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Qualcomm Inc
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Publication date
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Publication of CN107004636A publication Critical patent/CN107004636A/zh
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Publication of CN107004636B publication Critical patent/CN107004636B/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/498—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
    • H10W20/4441—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal the principal metal being a refractory metal

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
CN201580020697.1A 2014-05-09 2015-04-02 通孔材料选择和处理 Active CN107004636B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/274,470 2014-05-09
US14/274,470 US9196583B1 (en) 2014-05-09 2014-05-09 Via material selection and processing
PCT/US2015/024083 WO2015171223A1 (en) 2014-05-09 2015-04-02 Via material selection and processing

Publications (2)

Publication Number Publication Date
CN107004636A CN107004636A (zh) 2017-08-01
CN107004636B true CN107004636B (zh) 2020-07-28

Family

ID=52875811

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580020697.1A Active CN107004636B (zh) 2014-05-09 2015-04-02 通孔材料选择和处理

Country Status (5)

Country Link
US (1) US9196583B1 (cg-RX-API-DMAC10.html)
EP (1) EP3140857A1 (cg-RX-API-DMAC10.html)
JP (1) JP2017516305A (cg-RX-API-DMAC10.html)
CN (1) CN107004636B (cg-RX-API-DMAC10.html)
WO (1) WO2015171223A1 (cg-RX-API-DMAC10.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9620454B2 (en) * 2014-09-12 2017-04-11 Qualcomm Incorporated Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods
US9793212B2 (en) 2015-04-16 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
EP3704737B1 (en) * 2017-11-03 2025-12-17 INTEL Corporation Vias for integrated circuit structures and their method of fabrication

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6261960B1 (en) * 2000-04-06 2001-07-17 Advanced Micro Devices, Inc High density contacts having rectangular cross-section for dual damascene applications
CN102231361A (zh) * 2006-12-29 2011-11-02 半导体元件工业有限责任公司 半导体部件及其制造方法

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KR950010858B1 (ko) * 1992-10-20 1995-09-25 현대전자산업주식회사 반도체 소자의 금속콘택 형성방법
JP3175705B2 (ja) * 1998-09-18 2001-06-11 日本電気株式会社 不揮発性半導体記憶装置の製造方法
US6974766B1 (en) 1998-10-01 2005-12-13 Applied Materials, Inc. In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
JP3895126B2 (ja) * 2001-04-23 2007-03-22 株式会社東芝 半導体装置の製造方法
JPWO2004061947A1 (ja) * 2002-12-27 2006-05-18 富士通株式会社 半導体装置、ｄｒａｍ集積回路装置およびその製造方法
US20050285269A1 (en) 2004-06-29 2005-12-29 Yang Cao Substantially void free interconnect formation
US7160772B2 (en) 2005-02-23 2007-01-09 International Business Machines Corporation Structure and method for integrating MIM capacitor in BEOL wiring levels
US7863188B2 (en) * 2005-07-29 2011-01-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20070218685A1 (en) 2006-03-17 2007-09-20 Swaminathan Sivakumar Method of forming trench contacts for MOS transistors
US7767570B2 (en) * 2006-03-22 2010-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy vias for damascene process
US8089160B2 (en) * 2007-12-12 2012-01-03 International Business Machines Corporation IC interconnect for high current
JP5554951B2 (ja) 2008-09-11 2014-07-23 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2010087350A (ja) * 2008-10-01 2010-04-15 Fujitsu Microelectronics Ltd 半導体装置とその製造方法
US7999320B2 (en) 2008-12-23 2011-08-16 International Business Machines Corporation SOI radio frequency switch with enhanced signal fidelity and electrical isolation
US7843005B2 (en) 2009-02-11 2010-11-30 International Business Machines Corporation SOI radio frequency switch with reduced signal distortion
US8133774B2 (en) 2009-03-26 2012-03-13 International Business Machines Corporation SOI radio frequency switch with enhanced electrical isolation
US8796855B2 (en) * 2012-01-13 2014-08-05 Freescale Semiconductor, Inc. Semiconductor devices with nonconductive vias
US9355956B2 (en) * 2013-11-01 2016-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Inductor for semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6261960B1 (en) * 2000-04-06 2001-07-17 Advanced Micro Devices, Inc High density contacts having rectangular cross-section for dual damascene applications
CN102231361A (zh) * 2006-12-29 2011-11-02 半导体元件工业有限责任公司 半导体部件及其制造方法

Also Published As

Publication number Publication date
US9196583B1 (en) 2015-11-24
CN107004636A (zh) 2017-08-01
US20150325515A1 (en) 2015-11-12
WO2015171223A1 (en) 2015-11-12
JP2017516305A (ja) 2017-06-15
EP3140857A1 (en) 2017-03-15

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