CN106992194B - Image sensor for improving light utilization rate and manufacturing method thereof - Google Patents
Image sensor for improving light utilization rate and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses an image sensor for improving light utilization rate, which comprises an integrated substrate unit and an alternative isolation layer, wherein the integrated substrate unit comprises a photodiode; the light source also comprises a light channel groove, a light channel and a reflecting film; the optical channel groove is formed by etching the alternating isolation layer, is positioned right above the photodiode and is a conical groove; the light channel is filled in the light channel groove, the reflecting films are positioned on the side walls of two sides of the conical light channel groove and are convex surfaces with fixed curvature, the two sides of the reflecting films are thin, the middle of the reflecting films is thick, and incident light reaches the photodiode through the light channel. The image sensor reflection film for improving the light utilization rate has a good shading effect, the light channel has a good refraction effect, the light utilization rate is increased, and the image sensor reflection film is simple in process, low in cost, low in sensitivity and low in noise.
Description
Technical Field
The invention relates to the field of image sensors, in particular to an image sensor for improving light utilization rate and a manufacturing method thereof.
Background
The image sensor comprises a Charge Coupled Device (CCD) and a Complementary Metal Oxide Semiconductor (CMOS), the CCD manufacturing process is complex, the cost is high, the CMOS is easy to generate miscellaneous points, and the process is complex. The back side illumination technology (BSI) type CMOS commonly used at present adopts a wafer bonding technology to change the internal structure of an element, i.e., to turn the direction of the element of a photosensitive layer and allow light energy to enter from the back side directly, thereby avoiding the influence of a circuit and a transistor between a micro lens and a photodiode on light rays in the traditional CMOS sensor structure, remarkably improving the efficiency of light and greatly improving the shooting effect under a low illumination condition.
However, there are three drawbacks in back side illumination technology (BSI) type CMOS technology: (1) incident light enters from the back of the wafer and reaches the photodiode, photoelectric conversion occurs in the light transmission process, and signals are read out through certain equipment; in a general optical path to the photodiode, the most significant problem is that birefringence occurs at the interface of different isolation films, or light is reflected or internally scattered from the microlens to the photodiode, which reduces the light utilization rate. (2) In the BSI technique, the light absorption layer is fabricated on the epitaxial wafer, which is very demanding on the quality of the epitaxial wafer, and the dislocation or irregularity of the crystal in the epitaxial wafer can affect the propagation dislocation of light, thereby affecting the quality of the image sensor. (3) In the BSI technique, carrier leakage between adjacent pixels needs to be prevented, so a deep trench isolation is generally generated on the structure or a trench is completed first and then polished by the CMP technique, which is complicated and tedious in process and causes a substantial increase in cost.
Disclosure of Invention
The invention aims to solve the technical problem of providing an image sensor for improving the light utilization rate and a manufacturing method thereof.A light channel is filled in a light channel groove, and a reflecting film with two thin sides and a thick middle part is formed on the side wall, the reflecting film has a shading effect, the light channel has a good refraction effect, the light utilization rate is increased, the process is simple, the cost is low, the sensitivity is low, and the noise is low.
In order to achieve the purpose, the invention adopts the following technical scheme: the integrated substrate unit comprises an N-type photodiode and a P-type photodiode; the light source also comprises a light channel groove, a light channel and a reflecting film; the alternating isolation layer and the optical channel groove are positioned above the integrated substrate unit, the optical channel groove is formed by etching the alternating isolation layer, and the optical channel groove is positioned right above the N-type photodiode and the P-type photodiode and is a conical groove; the light channel is filled in the light channel groove, the reflecting films are positioned on the side walls of two sides of the conical light channel groove and are convex surfaces with fixed curvatures, the two sides of the reflecting films are thin, the middle of the reflecting films is thick, and incident light reaches the N-type photodiode and the P-type photodiode through the light channel.
Furthermore, the integrated substrate unit comprises a semiconductor substrate, an N-channel stop layer, shallow trench isolation, a P-type buried layer, a P-well region, an N-type photodiode, a P-type photodiode, a gate oxide layer, a transfer gate electrode, a reset gate electrode, a thermal oxidation layer, an N-type lightly doped region, an N-type source drain region, a photodiode protective film, an isolation layer, a contact hole and a tungsten plug.
Further, the thickness of the reflective film is 30 nm.
Further, the reflecting film is a metal film.
Further, the reflecting film is TiN.
Further, the reflecting film is Al2O3。
Further, the optical channel is filled with SiN.
Further, the alternating isolation layers are SiN and SiO2Alternating deposition formation.
The present invention also provides a method for manufacturing an image sensor with improved light utilization, comprising:
(1) manufacturing an integrated substrate unit comprising a semiconductor substrate, an N-channel stop layer, shallow trench isolation, a P-type buried layer, a P-well region, an N-type photodiode, a P-type photodiode, a gate oxide layer, a transfer gate electrode, a reset gate electrode, a thermal oxide layer, an N-type lightly doped region, an N-type source drain region, a photodiode protective film, an isolation layer, a contact hole and a tungsten plug, wherein the upper surfaces of the tungsten plug and the isolation layer are parallel and are positioned at the uppermost part of the integrated substrate unit;
(2) alternately depositing SiN isolating layer and SiO isolating layer on the tungsten plug and the isolating layer2An isolation layer forming an alternate isolation layer and performing metal wiring in the alternate isolation layer;
(3) dry etching a conical light channel groove in the alternating isolation layer right above the photodiode;
(4) coating a reflective film material and photoresist in sequence along the upper surface of the tapered light channel;
(5) etching a thin reflecting film with two sides, a thick middle part and a convex surface with fixed curvature through masking and imaging;
(6) and depositing SiN in the light channel groove, and removing redundant SiN through a chemical mechanical polishing technology to form a light channel.
The invention has the beneficial effects that: fill the light channel in the toper light channel slot, good refraction effect has, the reflection film of the both sides of toper light channel slot is metal film, has fine shading effect, prevent that the incident light from getting into in the alternative isolation layer, and the bottom opening is the biggest to the thin shape in middle thick both sides ensures that the incident light gets into the photodiode process through the light channel furthest, optical loss behaviors such as birefringence, reflection, internal scattering that have avoided appearing in the isolation layer have increased the utilization ratio of light.
Drawings
Fig. 1-12 are schematic cross-sectional views of the manufacturing method of the present invention.
In the figure: 1 semiconductor substrate, 2N channel stop layer, 3 shallow trench isolation, 4P type buried layer, 5P well region, 6N type photodiode, 7P type photodiode, 8 gate oxide layer, 9 transfer gate electrode, 10 reset gate electrode, 11 thermal oxide layer, 12N type lightly doped region, 13N type source drain region, 14 photodiode protective film, 15 isolation layer, 16 contact hole, 17 tungsten plug, 18SiN isolation layer, 19SiO2Isolation layer, 20SiN isolation layer, 21SiN isolation layer, 22SiO2Isolation layer, 23SiN isolation layer, 24SiO2Isolation layer, 25SiN isolation layer, 26SiN isolation layer, 27SiO2Isolation layer, 28SiN isolation layer, 29SiO2Isolation layer, 30SiN isolation layer, 31SiN isolation layer, 32SiO2Spacer, 33 light channel trench, 34 reflective thin film metal, 35 photoresist, 36 etch plasma, 37 light channel metal, 38SiN spacer, 39 light channel.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
The specific manufacturing process of the image sensor for improving the light utilization rate comprises the following steps:
referring to fig. 1, a silicon substrate with resistivity of 80-100 Ω · m in the N (100) direction is used as a semiconductor substrate 1, RCA cleaning is performed with a cleaning solution containing SC1, HF, SC2, a 10nm thermal oxide layer is formed on the silicon semiconductor substrate 1 by wet thermal oxidation, a 35nm polysilicon layer and a 15nm SiN isolation layer are sequentially deposited on the thermal oxide layer by chemical vapor deposition, a 50nm deep trench is etched through a photoresist mask and the photoresist is removed, and a 25nm SiO is formed in the trench2Oxide layer on the formed SiO2Performing ion implantation on the oxide layer to form an N-channel stop layer 2, and forming an N-channel stop layer 2 on the N-channel stop layer 2Wherein 500nm SiO is formed by chemical vapor deposition2And annealing the layer in a nitrogen atmosphere at 950 ℃ for 60 minutes to form the shallow trench isolation 3 by a planarization technology.
And forming a P-type buried layer 4 on the semiconductor substrate by etching and boron ion implantation by taking the photoresist as a mask, and removing the photoresist. And forming a P well region 5 on the P type buried layer 4 by etching and boron ion implantation by taking photoresist as a mask, and removing the photoresist.
Forming an N-type photodiode 6 by etching and arsenic ion implantation with the photoresist as a mask, and removing the photoresist; and forming a P-type photodiode 7 by etching and boron ion implantation by using the photoresist as a mask, removing the photoresist, and thermally annealing the photodiode at 1000 ℃ for 30 minutes.
RCA cleaning is carried out on the annealed semiconductor substrate, a gate oxide layer 8 with the thickness of 7nm is formed through an in-situ water vapor generation method, and a layer of polycrystalline silicon with the thickness of 200nm is deposited on the gate oxide layer 8 through a chemical vapor deposition method. Forming N-type polycrystal on the polycrystalline silicon by taking photoresist as a mask through etching and arsenic ion implantation, and removing the photoresist; and similarly, taking the photoresist as a mask, forming a P-type polycrystal through etching and boron ion implantation, and removing the photoresist. After that, with the photoresist as a mask agent, the transfer gate electrode 9 and the reset gate electrode 10 are formed by dry etching the polysilicon and removing the photoresist.
And taking the photoresist as a mask, and implanting phosphorus ions and removing the photoresist to obtain the N-type lightly doped region 12. The thermal oxide layer 11 is formed on the semiconductor substrate by wet oxidation at 900 ℃. RCA cleaning is carried out on the thermal oxidation layer 11, and SiO with the thickness of 10nm is deposited on the surface in sequence2And photoresist is coated on the layer and the 30nm SiN isolation layer, the position right above the photodiode is coated with the photoresist, the thermal oxidation layer of the rest part is removed through dry etching, the photodiode protection film 14 positioned above the photodiode is formed, and then the photoresist is removed. And coating photoresist on the floating diffusion pixel region, taking the photoresist as a mask, etching, injecting arsenic ions, and removing the photoresist to form the N-type source drain region 13. Finally, 80nm of silicon oxide and 1200nm of borophosphosilicate glass are deposited on the upper surface of the semiconductor substrate in sequence, and nitrogen gas at 825 DEG CAnnealing is carried out in the environment for 30 minutes and the isolation layer 15 is formed by chemical mechanical polishing.
As shown in fig. 2, a photoresist is coated on the isolation layer 15, and the contact hole 16 is etched by using a photoresist mask, and the photoresist is removed.
As shown in fig. 3, a Ti layer of 10nm, a TiN layer of 7nm, and a W layer of 300nm are sequentially deposited in the contact hole 16, and an excess portion of the W layer is removed by CMP to form a tungsten plug 17.
As shown in FIG. 4, a 28nm SiN spacer 18 and a 200nm SiO spacer are sequentially deposited on the upper surfaces of the tungsten plug 17 and the spacer 152An isolation layer 19 and a 60nm SiN isolation layer 20, metal wiring is performed in the isolation layer, and a mixture of Ta — Cu and Cu is used for the metal wiring. Then, a 50nm SiN isolation layer 21 and a 270nm SiO isolation layer are sequentially deposited on the upper surface of the SiN isolation layer 202 Isolation layer 22, 40nm SiN isolation layer 23, 300nm SiO2The isolation layer 24 is an 80nm SiN isolation layer 25, metal wiring is carried out in the isolation layer, and the metal wiring adopts a mixture of Ta-Cu and Cu. Then, a 50nm SiN isolation layer 26 and a 270nm SiO isolation layer are sequentially deposited on the upper surface of the SiN isolation layer 252 Isolation layer 27, 40nm SiN isolation layer 28, 300nm SiO2Isolation layer 29, 100nm SiN isolation layer 30, metal wiring in the isolation layer, Ta-Cu and C as metal wireuA mixture of (a).
As shown in FIG. 5, 50nm SiO is sequentially deposited on the upper surface of the SiN spacer 30 by chemical vapor deposition2Spacer 31 and 220nm SiN spacer 32.
As shown in fig. 6, 200nm bottom anti-reflective coating, 2500nm photoresist and 200nm top anti-reflective coating are coated on the SiN isolation layer 32, the alternating isolation layers are dry etched using the photoresist as a mask, and the light channel trench 33 located above the photodiode is formed after the photoresist is removed.
As shown in fig. 7, a layer of reflective thin film metal 34 is deposited by physical vapor deposition along the surface of the light channel trench 33 and the SiN isolation layer 32. Wherein the reflective film metal is 60nm TiN metal layer or 80nm Al2O3A metal layer.
As shown in fig. 8, a 100nm photoresist 35 is coated along the outer surface of the reflective thin film metal 34.
As shown in fig. 9 and 10, the reflective thin film metal 34 and the photoresist 35 in the light channel trench 33 are etched, the photoresist is used as a mask, the upper half portion of the reflective thin film metal 34 is etched into a circular shape, and then the lower half portion of the reflective thin film metal 34 is etched into a circular shape. Finally, the reflective film 37 with two thin sides and a fixed curvature in the middle is etched on the surface of the reflective film metal 34, the rest reflective film metal is completely etched, and then the photoresist 35 is removed.
As shown in fig. 11, an 1800nm SiN spacer 38 is deposited on the upper surfaces of the light channel trench 33, the reflective film 37 and the SiN spacer 32, and the SiN spacer 38 completely fills the light channel trench 33.
As shown in fig. 12, the excess SiN isolation layer 38 is removed by chemical mechanical polishing, so that the SiN isolation layer 38 is completely filled in the light channel trench 33, forming a light channel 39 in the light channel trench.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.
Claims (9)
1. An image sensor for improving light utilization rate comprises an integrated substrate unit and alternating isolation layers, wherein the integrated substrate unit comprises an N-type photodiode and a P-type photodiode; the LED light source is characterized by also comprising a light channel groove, a light channel and a reflecting film; the alternating isolation layer and the optical channel groove are positioned above the integrated substrate unit, the optical channel groove is formed by etching the alternating isolation layer, and the optical channel groove is positioned right above the N-type photodiode and the P-type photodiode and is a conical groove; the light channel is filled in the light channel groove, the reflecting films are positioned on the side walls of two sides of the conical light channel groove and are convex surfaces with fixed curvatures, the two sides of the reflecting films are thin, the middle of the reflecting films is thick, and incident light reaches the N-type photodiode and the P-type photodiode through the light channel.
2. The image sensor of claim 1, wherein the integrated substrate unit comprises a semiconductor substrate, an N-channel stop layer, a shallow trench isolation, a P-type buried layer, a P-well region, an N-type photodiode, a P-type photodiode, a gate oxide layer, a transfer gate electrode, a reset gate electrode, a thermal oxide layer, an N-type lightly doped region, an N-type source/drain region, a photodiode protection film, an isolation layer, a contact hole, and a tungsten plug.
3. The image sensor for improving light utilization according to claim 1, wherein the central thickness of the reflective film is 30 nm.
4. The image sensor of claim 1, wherein the reflective film is a metal film.
5. The image sensor of claim 4, wherein the reflective film is TiN.
6. The image sensor as claimed in claim 1, wherein the reflective film is Al2O3。
7. The image sensor of claim 1, wherein the light channel is filled with SiN.
8. The image sensor of claim 1, wherein the alternating isolation layers are SiN and SiO2Alternating deposition formation.
9. A method of making the image sensor of claim 2, comprising:
(1) manufacturing an integrated substrate unit comprising a semiconductor substrate, an N-channel stop layer, shallow trench isolation, a P-type buried layer, a P-well region, an N-type photodiode, a P-type photodiode, a gate oxide layer, a transfer gate electrode, a reset gate electrode, a thermal oxide layer, an N-type lightly doped region, an N-type source drain region, a photodiode protective film, an isolation layer, a contact hole and a tungsten plug, wherein the upper surfaces of the tungsten plug and the isolation layer are parallel and are positioned at the uppermost part of the integrated substrate unit;
(2) alternately depositing SiN isolating layer and SiO isolating layer on the tungsten plug and the isolating layer2An isolation layer forming an alternate isolation layer and performing metal wiring in the alternate isolation layer;
(3) etching a conical light channel groove in the alternating isolation layer right above the N-type photodiode and the P-type photodiode;
(4) coating a reflective film material and photoresist along the upper surface of the tapered light channel groove in sequence;
(5) imaging the reflective film material through a mask, and etching to obtain a reflective film with thin two sides and thick middle part and a convex surface with fixed curvature;
(6) and depositing SiN in the light channel groove, and removing redundant SiN through a chemical mechanical polishing technology to form a light channel.
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