CN106981557A - The method for packing and encapsulating structure of a kind of optoelectronic semiconductor chip - Google Patents
The method for packing and encapsulating structure of a kind of optoelectronic semiconductor chip Download PDFInfo
- Publication number
- CN106981557A CN106981557A CN201710223229.5A CN201710223229A CN106981557A CN 106981557 A CN106981557 A CN 106981557A CN 201710223229 A CN201710223229 A CN 201710223229A CN 106981557 A CN106981557 A CN 106981557A
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- Prior art keywords
- semiconductor chip
- optoelectronic semiconductor
- metal framework
- hard
- resinite
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims description 18
- 238000012856 packing Methods 0.000 title claims description 12
- 239000002184 metal Substances 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 15
- 238000000227 grinding Methods 0.000 claims abstract description 13
- 238000000465 moulding Methods 0.000 claims abstract description 6
- 239000000126 substance Substances 0.000 claims abstract description 5
- 229920005989 resin Polymers 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000002390 adhesive tape Substances 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 7
- 239000000919 ceramic Substances 0.000 claims description 6
- 238000007493 shaping process Methods 0.000 claims description 6
- 230000005496 eutectics Effects 0.000 claims description 5
- 239000003292 glue Substances 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- TZCXTZWJZNENPQ-UHFFFAOYSA-L barium sulfate Chemical compound [Ba+2].[O-]S([O-])(=O)=O TZCXTZWJZNENPQ-UHFFFAOYSA-L 0.000 claims description 4
- 239000003795 chemical substances by application Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 230000006641 stabilisation Effects 0.000 claims description 3
- 238000011105 stabilization Methods 0.000 claims description 3
- 230000000087 stabilizing effect Effects 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 239000011230 binding agent Substances 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- 239000006071 cream Substances 0.000 claims description 2
- 229910052906 cristobalite Inorganic materials 0.000 claims description 2
- 239000000945 filler Substances 0.000 claims description 2
- 230000013011 mating Effects 0.000 claims description 2
- 239000002245 particle Substances 0.000 claims description 2
- 229920001296 polysiloxane Polymers 0.000 claims description 2
- 238000007639 printing Methods 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000013464 silicone adhesive Substances 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- 229910052682 stishovite Inorganic materials 0.000 claims description 2
- 229910052905 tridymite Inorganic materials 0.000 claims description 2
- 238000005253 cladding Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 7
- 239000000741 silica gel Substances 0.000 description 4
- 229910002027 silica gel Inorganic materials 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000005622 photoelectricity Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000011265 semifinished product Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 241001025261 Neoraja caerulea Species 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/50—Wavelength conversion elements
- H01L33/505—Wavelength conversion elements characterised by the shape, e.g. plate or foil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/56—Materials, e.g. epoxy or silicone resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/641—Heat extraction or cooling elements characterized by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a kind of encapsulating structure of optoelectronic semiconductor chip, metal framework is included；Fixed at least one optoelectronic semiconductor chip on the metal framework；Fixed hard flourescent sheet above the photosemiconductor chip；Contain on the metal framework or do not contain other half electric conductor chips, the metal framework gap and top and the photosemiconductor chip, hard flourescent sheet, semiconductor chip periphery and top pass through mould molding resinite；The resinite subtracts material to the height of not higher than described hard fluorescent material by grinding, chemical attack；The metal framework and the resinite cut into the functional unit including at least a photosemiconductor chip and the hard flourescent sheet.
Description
Technical field
The invention belongs to field of semiconductor package, it is related to a kind of method for packing of optoelectronic semiconductor chip, a kind of photoelectricity half
The dress technique and structure of conductor chip high reliability envelope.
Background technology
It is that mode of the transparent fluorescent glue with fluorescent material is packaged that current white light emitting diode, which encapsulates general method,.Silicon
There is substantial amounts of hole inside glue, steam and oxidizing gas can enter LED internal by silica gel hole, cause
Light emitting diode is deteriorated；There is also yellow, cracking the problem of deterioration, occur to show under hot and humid environment in itself for other silica gel
As causing light emitting diode to produce light decay or color drift.Silica gel packaging band can be prevented by being packaged with air-locked hard flourescent sheet
The problem of coming.In addition, with the lifting of LED power, one of the problem of radiating also turns into primary solve.Traditional is big
, there is the problem of cost is high, thermal resistance is not low enough, should there is a kind of encapsulating structure in power led use ceramics bracket, can
To realize quickly heat conduction, and effectively reduce cost.Solve silica gel packaging gas permeability and support high thermal resistance, automobile,
The application such as street lamp above has become urgent demand.
The content of the invention
The problem of existing present invention mainly solves prior art comes real there is provided a kind of encapsulating structure of optoelectronic semiconductor chip
It is existing.Meanwhile, present invention addresses a kind of method of photoelectron semiconductor assembly structure of high efficiency manufacture, sealed with high reliability light half
The characteristics of dress
The present invention solves above-mentioned technical problem and is mainly what is be addressed by following technical proposals:
The invention provides a kind of method for packing of optoelectronic semiconductor chip, method comprises the following steps：
S1) metal framework is provided；
S2) at least one optoelectronic semiconductor chip is provided, the optoelectronic semiconductor chip is fixed on the metal framework
On；
S3) above each optoelectronic semiconductor chip, fixed hard flourescent sheet；
S4) by mould above the metal framework inside moulding resin body, resinite filling metal framework
Gap simultaneously coats all structures above metal framework；
S5) resinite is thinned to the height of not higher than described hard flourescent sheet by grinding or chemical attack；
S6 the metal framework) is cut to obtain comprising at least an optoelectronic semiconductor chip and institute with the resinite
State the photoelectron semiconductor assembly structure of hard flourescent sheet.
As the technical program preferred embodiment, the mode that the optoelectronic semiconductor chip is fixed welded for eutectic or
Tin cream is welded or conductive silver glue is bonded or silicone adhesive agent is bonded.
As the technical program preferred embodiment, the hard flourescent sheet is the mixture or ceramics of glass and fluorescent material
With the mixture of fluorescent material.
As the technical program preferred embodiment, the hard flourescent sheet is bonded in the photoelectricity half with printing opacity binding agent
Above conductor chip.
It can also be fixed as the technical program preferred embodiment, on the metal framework or unfixed be provided with one
Other individual or multiple semiconductor chips, other semiconductor chips play voltage stabilizing, current stabilization.
As the technical program preferred embodiment, the resinite is epoxy resin composition or silicone compound,
Wherein mixture comprises at least one kind in TiO2, SiO2, BaSO4, ZnO filler particles.
As the technical program preferred embodiment, before the resinite is molded, post resistance to below the metal framework
High temperature gummed tape, the High temperature-resistanadhesive adhesive tape can stop the resin flash produced during shaping.
As the technical program preferred embodiment, the High temperature-resistanadhesive adhesive tape is peeled off after shaping terminates.
Hardness, which is chosen, as the technical program preferred embodiment, when grinding the resinite is not higher than hard flourescent sheet
Grinding agent.Grinding can obtain smoother surface.The material of grinding, chooses hardness and is higher than resinite, less than hard flourescent sheet
Material.
As the technical program preferred embodiment, resinite residual altitude is concordant with hard flourescent sheet or glimmering less than hard
Mating plate.
As the present invention preferably case, the distance range on resinite surface to hard flourescent sheet surface be 0um~
500um.0um situation is that hard flourescent sheet is not coated completely or partially by resinite.
As the present invention preferably case, as the technical program preferred embodiment, the metal framework is copper material,
Whole or local silver-plating or gold or NiPdAu alloy.
As the technical program preferred embodiment, the metal framework thickness is 150um~300um.
As the technical program preferred embodiment, the optoelectronic semiconductor chip is inverted structure chip.
As the technical program preferred embodiment, the optoelectronic semiconductor chip is thin-film LED, accordingly, institute
Perforate or breach should be provided with by stating on hard flourescent sheet, connecting line can be turned on by the perforate or breach the semiconductor chip with
Other structures.
As the technical program preferred embodiment, the optoelectronic semiconductor chip is fixed on the gold by eutectic method
Belong on framework.
As the technical program preferred embodiment, the resinite is white or black epoxy composite.
The method for packing that technical solution of the present invention is provided, can quickly be made sheet of high density semi-finished product, pass through cutting
Chip semi-finished product and the optoelectronic semiconductor chip of the invention provided encapsulating structure.
A kind of encapsulating structure for optoelectronic semiconductor chip that another technical scheme of the present invention is to provide, including it is following：
Metal framework；
At least one optoelectronic semiconductor chip；
At least one hard flourescent sheet, the hard flourescent sheet is above the optoelectronic semiconductor chip；
Resinite, the resinite fill the metal framework internal clearance and coat above and above the metal framework and
The optoelectronic semiconductor chip, the semiconductor chip surrounding；
Alternatively, other one or more semiconductor chips are further fixed on the metal framework, rise but not
It is limited to voltage stabilizing, the effect of current stabilization.
The resinite is not higher than the hard flourescent sheet.
There is the vestige of grinding or chemical attack on the top of the optoelectronic semiconductor component structure.
There is the vestige of cutting or grinding the side of the optoelectronic semiconductor component structure.
The encapsulating structure of the technical program, bottom metal framework provides the radiator structure of low thermal resistance, can be quickly by light
The heat derives that electric semiconductor is produced.
Optoelectronic semiconductor chip described in the technical program is light-emitting diode chip for backlight unit or laser diode chip.Luminous two
The radiation that pole pipe chip or laser diode chip are launched, can excite the fluorescent grain in hard flourescent sheet to light.
Hard flourescent sheet described in the technical program includes fluorescent grain, and fluorescent grain is swashed by the shorter blue ray radiation of wavelength
Longer wavelengths of gold-tinted radiation can be produced after hair, two kinds of light are mixed into white light.The base material of hard flourescent sheet is glass or ceramics.
There is preferable air-tightness for the hard flourescent sheet of base material with glass or ceramics, steam or oxidizing gas can be completely cut off
Enter package interior from top.
Material is met as packaging body using epoxy resin, has good adhesive force with metal framework, can completely cut off steam or
Oxidizing gas enters package interior from bottom.
As the technical program preferred embodiment, described other semiconductor chips have antistatic, anti-surge voltage
Function.
The encapsulating structure of above technical scheme realizes the highly reliable of optoelectronic semiconductor component high temperature resistant and adverse environment resistant
Property.
Brief description of the drawings
Fig. 1 is the semi-finished product structure schematic diagram after resinite is thinned in embodiment, wherein：1 is metal substrate；2 be photoelectricity
Semiconductor chip；3 be hard flourescent sheet；4 be other semiconductor chips；5 be resinite；6 be High temperature-resistanadhesive adhesive tape.
Fig. 2 is the product structure schematic diagram after optoelectronic semiconductor chip encapsulation cutting in embodiment.
Fig. 3 is the product structure signal after the photoelectron semiconductor assembly cutting with other semiconductor chips in embodiment
Figure.
Embodiment
The technique effect of the design of the present invention, concrete structure and generation is carried out below with reference to embodiment and accompanying drawing clear
Chu, complete description, to be completely understood by the purpose of the present invention, feature and effect.Obviously, described specific embodiment is
A part of embodiment of the present invention, rather than whole embodiments, based on embodiments of the invention, those skilled in the art is not
The other embodiment obtained on the premise of paying creative work, belongs to protection scope of the present invention.In the invention
Various technical characteristics, can be with combination of interactions on the premise of not conflicting conflict.
With reference to shown in Fig. 1-3, the present embodiment is a kind of method for packing of optoelectronic semiconductor chip, is lost on metal framework 1
The circuit that multiple chips are fixed is carved, multiple optoelectronic semiconductor chips 2 are fixed on metal framework, other can be alternatively fixed again
Semiconductor chip 4 plays such as antistatic effect；Fixed-area is not less than optoelectronic semiconductor on each optoelectronic semiconductor chip
The hard ceramic piece 3 of chip area, by mould above metal framework in moulding resin body 5, resinite filling metal framework
The gap in portion simultaneously coats all structures above metal framework；The effect resinite 5 is thinned to not higher than by grinding
The height of hard flourescent sheet 3；Resinite 2 described in the metal is cut to obtain comprising at least an optoelectronic semiconductor chip 2 and institute
State (101), (102) in the encapsulating structure of the optoelectronic semiconductor chip of hard flourescent sheet, such as Fig. 2.
Specific encapsulation process is as follows：
Step one：Optoelectronic semiconductor chip 2, antistatic semiconductor chip 4 are fixed on 1 on metal framework, eutectic is carried out
Welding.
Step 2：Hard flourescent sheet is bonded at transparent adhesive above optoelectronic semiconductor chip, then toasted.
Step 3：The pasted with high temperature-resistant adhesive tape 6 below metal framework, plays and flash is produced when preventing shaping resin body 4
Effect.
Step 4：With mould in metal framework above moulding resin body.
Step 5：High temperature gummed tape, cutting metal framework and resinite are removed, the structure in Fig. 2 is obtained.
Either：
Step one：Optoelectronic semiconductor chip 2 and other semiconductor chips 4 are fixed on 1 on metal framework, eutectic weldering is carried out
Connect.
Step 2：Hard flourescent sheet is bonded at transparent adhesive above optoelectronic semiconductor chip, then toasted.
Step 3：The pasted with high temperature-resistant adhesive tape 6 below metal framework, plays and excessive glue is produced when preventing shaping resin body 4
Effect.
Step 4：With mould in metal framework above moulding resin body.
Step 5：High temperature gummed tape, cutting metal framework and resinite are removed, Fig. 3 structure is obtained.
The metal framework 1 that the present embodiment is used is copper material, whole or local silver-plating or gold or NiPdAu alloy.
Metal framework thickness 1 in the present embodiment is 100um~300um.
Optoelectronic semiconductor chip 2 in the present embodiment is inverted structure chip.
In the present embodiment, the distance range on resinite surface to hard flourescent sheet surface is 500um.
The present embodiment realizes optoelectronic semiconductor chip high temperature resistant and the high reliability of adverse environment resistant.
The preferred embodiment to invention is illustrated above, but the invention is not limited to the embodiment,
Those skilled in the art can also make many kinds of equivalent modifications or replacement on the premise of without prejudice to spirit of the invention, this
Equivalent modification or replacement are all contained in the application claim limited range a bit.
Claims (10)
1. a kind of method for packing of optoelectronic semiconductor chip, comprises the following steps：
Metal framework (1) S1) is provided；
At least one optoelectronic semiconductor chip (2) S2) is provided, the optoelectronic semiconductor chip (2) is fixed on the metal frame
On frame (1)；
S3) above each optoelectronic semiconductor chip (2), fixed hard flourescent sheet (3)；
S4) by mould above the metal framework inside moulding resin body (5), resinite filling metal framework between
Gap simultaneously coats all structures above metal framework；
The resinite (5) S5) is thinned to the height of not higher than described hard flourescent sheet (3) by grinding or chemical attack；
S6 the metal framework (1)) is cut to obtain comprising at least an optoelectronic semiconductor chip with the resinite (2)
(2) and the hard flourescent sheet photoelectron semiconductor assembly structure (101), (102).
2. the method for packing of optoelectronic semiconductor chip according to claim 1, it is characterised in that the optoelectronic semiconductor core
The mode that piece is fixed is welded for eutectic or tin cream is welded or conductive silver glue is bonded or silicone adhesive agent is bonded；
The hard flourescent sheet (3) is the mixture or the mixture of ceramics and fluorescent material of glass and fluorescent material；The hard is glimmering
Mating plate is bonded in printing opacity binding agent above the optoelectronic semiconductor chip (2)；
Can also be fixed on the metal framework or it is unfixed be provided with other one or more semiconductor chips (4), it is described
Other semiconductor chips play voltage stabilizing, current stabilization；
The resinite (5) is epoxy resin composition or silicone compound, and wherein mixture comprises at least TiO2, SiO2,
One kind in BaSO4, ZnO filler particles.
3. the method for packing of optoelectronic semiconductor chip according to claim 1, it is characterised in that be molded the resinite
Before, High temperature-resistanadhesive adhesive tape (6) is posted below the metal framework, the High temperature-resistanadhesive adhesive tape can stop that the resin produced during shaping overflows
Material.
4. the method for packing of optoelectronic semiconductor chip according to claim 3, it is characterised in that by the High temperature-resistanadhesive adhesive tape
Peeled off after shaping terminates.
5. the method for packing of optoelectronic semiconductor chip according to claim 1, it is characterised in that when grinding the resinite
Choose the grinding agent that hardness is not higher than hard flourescent sheet.
6. the method for packing of optoelectronic semiconductor chip according to claim 1, it is characterised in that resinite residual altitude with
Hard flourescent sheet is concordant or less than hard flourescent sheet.
7. a kind of encapsulating structure of optoelectronic semiconductor chip (2.1,2.2), including：
Metal framework (1),
At least one optoelectronic semiconductor chip (2), is fixed on the metal framework (1)；
At least one hard flourescent sheet (3), the hard flourescent sheet is fixed on above the optoelectronic semiconductor chip；
Resinite (5), the resinite is filled above metal framework (1) internal clearance and cladding and the metal framework (1)
Top and the optoelectronic semiconductor chip surrounding.
8. the encapsulating structure of optoelectronic semiconductor chip according to claim 7, it is characterised in that the resinite is not higher than
The hard flourescent sheet.
9. the encapsulating structure of optoelectronic semiconductor chip according to claim 7, it is characterised in that the metal framework (1)
On can also be fixed with other one or more semiconductor chips, the resinite coats the semiconductor chip surrounding.
10. the encapsulating structure of optoelectronic semiconductor chip according to claim 7, it is characterised in that the optoelectronic semiconductor
There is the vestige of grinding or chemical attack on the top of device architecture, and there is the trace of cutting the side of the optoelectronic semiconductor component structure
Mark.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710223229.5A CN106981557A (en) | 2017-04-07 | 2017-04-07 | The method for packing and encapsulating structure of a kind of optoelectronic semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710223229.5A CN106981557A (en) | 2017-04-07 | 2017-04-07 | The method for packing and encapsulating structure of a kind of optoelectronic semiconductor chip |
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|---|---|
| CN106981557A true CN106981557A (en) | 2017-07-25 |
Family
ID=59344182
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710223229.5A Pending CN106981557A (en) | 2017-04-07 | 2017-04-07 | The method for packing and encapsulating structure of a kind of optoelectronic semiconductor chip |
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| US20160057833A1 (en) * | 2014-08-20 | 2016-02-25 | Lumens Co., Ltd. | Method for manufacturing light-emitting device packages, light-emitting device package strip, and light-emitting device package |
| CN105845809A (en) * | 2015-02-04 | 2016-08-10 | 亿光电子工业股份有限公司 | LED Packaging Structure And Method For Manufacturing The Same |
-
2017
- 2017-04-07 CN CN201710223229.5A patent/CN106981557A/en active Pending
Patent Citations (7)
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|---|---|---|---|---|
| CN1670973A (en) * | 2004-03-15 | 2005-09-21 | 三星电机株式会社 | High power LED package |
| CN102832327A (en) * | 2011-06-16 | 2012-12-19 | 日东电工株式会社 | Phosphor adhesive sheet, light emitting diode element, light emitting diode device, and producing method thereof |
| CN103165794A (en) * | 2011-12-14 | 2013-06-19 | 信越化学工业株式会社 | Base for optical semiconductor device and method for preparing the same, and optical semiconductor device |
| US20160057833A1 (en) * | 2014-08-20 | 2016-02-25 | Lumens Co., Ltd. | Method for manufacturing light-emitting device packages, light-emitting device package strip, and light-emitting device package |
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Application publication date: 20170725 |