CN106981486A - Low-work voltage phase inverter and preparation method thereof - Google Patents

Low-work voltage phase inverter and preparation method thereof Download PDF

Info

Publication number
CN106981486A
CN106981486A CN201610029456.XA CN201610029456A CN106981486A CN 106981486 A CN106981486 A CN 106981486A CN 201610029456 A CN201610029456 A CN 201610029456A CN 106981486 A CN106981486 A CN 106981486A
Authority
CN
China
Prior art keywords
phase inverter
film
layer
gate
channel layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610029456.XA
Other languages
Chinese (zh)
Inventor
竺立强
肖惠
万昌锦
刘阳辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ningbo Institute of Material Technology and Engineering of CAS
Original Assignee
Ningbo Institute of Material Technology and Engineering of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ningbo Institute of Material Technology and Engineering of CAS filed Critical Ningbo Institute of Material Technology and Engineering of CAS
Priority to CN201610029456.XA priority Critical patent/CN106981486A/en
Publication of CN106981486A publication Critical patent/CN106981486A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention discloses a kind of low-work voltage phase inverter and preparation method thereof.The phase inverter of the present invention includes the first transistor and second transistor formed on an insulating substrate, wherein, the first transistor is worked with depletion type pattern, the second transistor is worked with enhancement mode, also, the gate dielectric layer of the first transistor and second transistor is made up of the solid electrolyte with ionic conduction characteristic.Present invention also offers the method for preparing low-work voltage of the invention, the phase inverter of high-gain.The phase inverter of the present invention further reduces manufacturing cost while low-work voltage, high voltage gain is obtained.

Description

Low-work voltage phase inverter and preparation method thereof
Technical field
The present invention relates to microelectronics technology, and in particular to a kind of low-work voltage phase inverter and its making side Method.
Background technology
Phase inverter is the important composition unit of microelectronics system.
In recent years, people are continuously increased to portable, low power dissipation electron product demand, and electronic system Unite becoming increasingly abundant with function, its power consumption is also continuously increased, thus low power dissipation electron element design One of the important directions developed as microelectric technique from now on, using the electronic component with low-work voltage and Phase inverter is a kind of effective means for realizing low consumption circuit design.
Conventional complementary Metal-oxide-semicondutor (Complementary metal-oxide-semiconductor, CMOS) phase inverter, generally using the suitable n-type of performance and p-type MOS transistor (field-effect Transistors, FETs) composition, such as p-type silicon FET and n-type silicon FET.Oxide thin film transistor is current electricity Star's element of sub-information industry, in transparent flexible FPD of new generation or wearable, portable electronic production The fields such as product have extremely strong application prospect.The electronic conduction characteristic of oxide semiconductor thin-film is preferable, accordingly N-type metal oxide thin-film transistor (TFTs) electrology characteristic it is excellent, its field-effect electron mobility is up to 10~100cm2/Vs。
But it is worthy of note that, it is difficult that to find hole conduction comprehensive in metal-oxide semiconductor (MOS) family The excellent P-type metal oxide semiconductor material of energy, is difficult to effective on p-type metal-oxide film Ohmic contact, therefore the electrology characteristic of the p-type metal oxide thin-film transistor (TFTs) made is not good, it is empty Cave mobility is smaller, generally<1cm2/ Vs, so as to finally influence the electric property of whole inverter circuit.Have In consideration of it, people design inverter circuit using two n-type metal oxide TFTs, two be related to n-type TFTs threshold voltage is different.
However, the TFTs that is used of this kind of phase inverter generally using traditional gate dielectric membrane (such as SiNx, HfO2, Ta2O5 etc.), its unit-area capacitance is smaller, typically smaller than tens nF/cm2, the work electricity of device Pressure is larger, generally>5V, thus design inverter circuit operating voltage it is also relatively large, in order to obtain compared with Big voltage gain, it usually needs use larger supply voltage VDD(>5V), and phase inverter voltage transmit Voltage transition region scope on curve is also than larger, and typically larger than 1V, these performances significantly limit it Application in low-power consumption, portable type electronic product.
Patent CN201210057047.2, CN200880015916.7, CN200910175707.5, The preparation method that the patents such as CN200910130129.3, CN201310365628 disclose phase inverter, but They have respective limitation.For example, patent CN201210057047.2, CN200880015916.7, In CN200910175707.5, CN200910130129.3, the operating voltage of phase inverter is relatively high, reaches To more than 10V；And for example, in patent CN201310365628, it is necessary to be etched back to technique, process meanses phase To more complicated；And for example, in patent CN201210057047.2, a transistor of composition phase inverter is needed There is double-gate structure, similarly improve the complexity of manufacture craft；And for example, in patent , it is necessary to be heat-treated to transistor channel in CN200880015916.7 and CN201210057047.2, Similarly further improve process complexity and process costs.
In summary, it is necessary to develop a kind of phase inverter, it can be worked with low-work voltage, and with high voltage Gain, this phase inverter is in biochemistry sensing, Low Power Consumption Portable electronic product and bionic product neck Domain has broad application prospects.
The content of the invention
The purpose that the present invention is carried just is to provide a kind of phase inverter and preparation method thereof, with low-work voltage and height Voltage gain, and with lower manufacturing cost.
In the first aspect of the invention there is provided a kind of phase inverter, comprising：
Substrate；
The first deposition structure on the substrate；And
The second deposition structure on the substrate；
Wherein, the first deposition structure includes：On the substrate first gate electrode, positioned at described The first gate dielectric layer on one gate electrode, the first channel layer on first gate dielectric layer, positioned at institute State the first source electrode on the first channel layer and the first drain electrode；Also, the first deposition structure constitutes to exhaust The first transistor of pattern formula work；
The second deposition structure includes：On the substrate the second gate electrode, positioned at the second gate electricity The second gate dielectric layer on extremely, the second channel layer on second gate dielectric layer, positioned at described second The second source electrode and the second drain electrode on channel layer；Also, the second deposition structure is constituted with enhancement mode The second transistor of work；And
The first gate electrode, first source electrode and second drain electrode are electrically connected by conductive layer；And
In the phase inverter, the first grid is used as output end Vout, the second grid is used as input Hold Vin, second source ground, described first drains for applying supply voltage VDD；And
First gate dielectric layer and the second gate dielectric layer are ionic conduction type solid electrolyte.
In another preference, the ionic conduction type solid electrolyte is independently selected from the following group：Loose oxidation Thing deielectric-coating, sodium alginate film, chitosan film, Methyl Cellulose Hydrogel Films.
In another preference, the ionic conduction type solid electrolyte is independently selected from the following group：Loose SiO2 Film, loose phosphorus doping SiO2Film layer, loose aluminium oxide Al2O3Film, also, first gate medium Layer is 300nm~5 μm with second gate thickness of dielectric layers, and specific surface area is 1m2/ g~100m2/ g, membrane pores Gap size is 1nm~10nm, and proton conductivity is 1 × 10-5S/cm~1 × 10-3S/cm, unit-area capacitance For 0.05~100 μ F/cm2, it is preferred that 0.1~20 μ F/cm2。
In another preference, first channel layer is indium zinc oxide (InZnO) film, second raceway groove Layer is indium zinc oxide (InZnO) film or indium gallium zinc oxygen (InGaZnO) film, first channel layer and second The thickness of channel layer is 10nm~100nm.
In another preference, the first deposition structure and the second deposition structure are located at the same of the substrate Side, both sides or on different substrates.
In another preference, the first deposition structure and the second deposition structure are located at the same of same substrate Side.
In another preference, the phase inverter is integrated.
In another preference, first source electrode and second drain electrode are for same structure layer.
In another preference, the first gate electrode, first source electrode and second drain electrode are by leading Electric layer is connected.
In another preference, the phase inverter is low-work voltage, high voltage gain type phase inverter.
In another preference, the phase inverter be low-work voltage, high voltage gain type phase inverter, and " low-work voltage " refers to operating voltage not higher than 3V.
In another preference, " high-gain " refers under low supply voltage the output voltage (V of (0.5V~3V)out) To input voltage (Vin) local derviation absolute value be higher than 20.
In another preference (specific input voltage and operating voltage), the input voltage (V of the phase inverterin) Scope is -1V~1.5V, the supply voltage (V of applicationDD) when being between 0.5~3V scopes, corresponding output electricity Press (Vout) excursion be 0~VDD, work as VDDDuring=2V, voltage gain is more than 40.
In another preference, what the input voltage of the phase inverter can be independent is selected from the group：Sinusoidal waveform, Triangular waveform, noise waveform, or their any combination.
In another preference, the dielectric substrate is selected from the group：Deposition has thermal oxide SiO2Monocrystalline silicon lining Bottom, glass substrate, plastic supporting base, paper substrate, ceramic substrate.
In another preference, the first gate electrode and the second gate electrode are independently selected from the following group：Indium tin oxygen Compound (InSnO) film layer, Au film layers, Ag film layers, Al film layers and Cu film layers.
In another preference, first source electrode, the first drain electrode, the second source electrode, the second drain electrode, and The following group is selected independently in conductive layer：InSnO films, Au film layers, Ag film layers, Al film layers and Cu are thin Film layer.
In the second aspect of the invention there is provided a kind of low-work voltage phase inverter preparation method, comprising with Lower step：
(a) substrate is provided；
(b) the first deposition region over the substrate deposits to form the first deposition structure；And in the lining The second deposition region on bottom deposits to form the second deposition structure；
Wherein, the first deposition structure includes：On the substrate first gate electrode, positioned at described The first gate dielectric layer on one gate electrode, the first channel layer on first gate dielectric layer, positioned at institute State the first source electrode on the first channel layer and the first drain electrode；And the first deposition structure is constituted with depletion type The first transistor of pattern work；
The second deposition structure includes：On the substrate the second gate electrode, positioned at the second gate electricity The second gate dielectric layer on extremely, the second channel layer on second gate dielectric layer, positioned at described second The second source electrode and the second drain electrode on channel layer；And the second deposition structure is constituted with enhancement mode work The second transistor of work；With
(c) first gate electrode, first source electrode and second drain electrode are electrically connected, so that Form phase inverter described in first aspect present invention.
It is described to deposit to form the first deposition structure and described second in the first deposition region in another preference It is while carrying out or successively carrying out that deposition region, which deposits and to form the second deposition structure,.
In another preference, the step (b) and (c) include：
(i) the first deposition structure in the dielectric substrate deposits graphical first gate electrode, in the insulation The second deposition structure on substrate deposits graphical second gate electrode；
(ii) solid electrolyte membrane of the deposition with ionic conduction characteristic in the first gate electrode, is used as first Gate dielectric layer, solid electrolyte membrane of the deposition with ionic conduction characteristic on second gate electrode, as Second gate dielectric layer；
(iii) patterned first channel layer is deposited on first gate dielectric layer, in second gate medium Patterned second channel layer is deposited on layer；With
(iv) patterned conductive film is deposited on first channel layer and the second channel layer, is used as first Source electrode and the first drain electrode, the second source electrode and the second drain electrode, and conductive layer, wherein the conductive layer will be described Second drain electrode, the first source electrode and first gate electrode are electrically connected.
In another preference, in the step b), using plasma enhancing technology or collosol and gel The technology deposition solid electrolyte membrane with ionic conduction characteristic, also, it is described special with ionic conduction Property solid electrolyte membrane thickness be 300nm~5 μm, specific surface area is 1m2/ g~100m2/ g, film Pore-size is 1nm~10nm, and proton conductivity is 1 × 10-5S/cm~1 × 10-3S/cm, unit area electricity Hold for 0.1~100 μ F/cm2, it is preferred that 0.1~20 μ F/cm2.More, the thickness of the loose film For 1 μm.
In another preference, in the step b), using plasma enhancing technology or collosol and gel The technology deposition solid electrolyte membrane with ionic conduction characteristic, also, it is described special with ionic conduction Property solid electrolyte membrane thickness be 300nm~5 μm, proton conductivity be 1 × 10-5S/cm~1 × 10-3S/cm, unit-area capacitance is 0.1~100 μ F/cm2, it is preferred that 0.1~20 μ F/cm2。
In another preference, in the step b), first channel layer is deposited using magnetron sputtering technique With second channel layer.
In the third aspect of the invention there is provided a kind of electronic product, the electronic product contains above-mentioned anti- Phase device, the electronics applications are in biochemistry sensing, Low Power Consumption Portable electronic product and bionic Product scope.
It should be understood that within the scope of the present invention, above-mentioned each technical characteristic of the invention and (such as implementation below Example) in specifically describe each technical characteristic between can be combined with each other, so as to constitute new or preferred skill Art scheme.As space is limited, no longer tire out one by one herein and state.
Brief description of the drawings
Accompanying drawing 1 is the structural representation of the phase inverter according to the present invention；
Accompanying drawing 2 is the electrology characteristic test result of the phase inverter obtained according to present invention making.
In the drawings, 1：Dielectric substrate；2a and 2b：Bottom gate thin film；3a and 3b：Gate dielectric layer；4a And 4b：Channel layer；5a and 5c：Source electrode；5b and 5d：Drain electrode；5e：Conductive layer, for device interconnection.
Embodiment
The present inventor has found that the gate dielectric layer in the transistor of phase inverter is used by in-depth study extensively Ionic conduction type solid electrolyte, can significantly decrease the operating voltage of phase inverter and with high voltage gain Property, therefore propose a kind of new low-work voltage phase inverter and preparation method thereof, obtain low-work voltage, High voltage gain simultaneously, further reduces cost of manufacture, portable in biochemistry sensing, low-power consumption Formula electronic product and bionic product scope have broad application prospects.
Term
As used herein, term " of the invention low-work voltage, the phase inverter of high voltage gain type ", " this The low-work voltage phase inverter of invention " or " phase inverter of the invention " are used interchangeably, and refer to the present invention the The phase inverter of one side low-work voltage, high voltage gain type.
As used herein, term, " low-work voltage " refers to that operating voltage (or its absolute value) is not higher than (≤) 3V.
As used herein, term " high voltage gain " refers to the output voltage (V under low supply voltageout) to input electricity Press (Vin) local derviation (- dVout/dVin) absolute value be higher than (>=) 20, preferably >=30, more preferably >=40.Generally, Local derviation (dVout/dVin) absolute value be less than (≤100).For example, as the input voltage (V of phase inverterin) scope be -1V~ 1.5V, the supply voltage (V of applicationDD) for a certain value between 0.5~3V scopes, corresponding output voltage (Vout) Scope is 0~VDD, wherein, work as VDDDuring=2V, voltage gain is more than 40.
As used herein, the term solid electrolyte of ionic conduction characteristic " have ", " ionic conduction type is solid State electrolyte " is used interchangeably, and refers to the solid electrolyte with ionic conduction characteristic.
As used herein, the term solid electrolyte membrane of ionic conduction characteristic " have ", " loose film " can Used interchangeably.For example：Refer to loose oxide dielectric film, sodium alginate film, chitosan film, Methyl cellulose Plain film.Preferably loose SiO2Film and loose Al2O3Film.Ion-conductive solid electrolyte has with properties, In the presence of external electric field, ion present in solid electrolyte is to electrolyte/electrode interface or electrolyte/raceway groove circle Face is migrated, and then in one layer of electrode side or raceway groove side induction and the electrical opposite, quantity of electric charge identical current-carrying of ion Sub- Guinier-Preston zone, so as to produce interface electric double layer in interface induction, the thickness of this interface electric double layer it is minimum (~ 1nm), its unit-area capacitance greatly (0.1~20 μ F/cm2), therefore this solid electrolyte have it is extremely strong quiet Electric ability of regulation and control, it is minimum as the oxide TFTs of gate medium operating voltage using this solid electrolyte (<2V)。
Phase inverter
The invention provides a kind of phase inverter, first, second deposition structure being formed on substrate, first are included Deposit structure and constitute the first transistor worked with depletion type pattern, the second deposition structure is constituted with enhancement mode work The gate electrode and source electrode of the second transistor of work, wherein the first transistor, and second transistor drain electrode by leading Electric layer is electrically connected, and the grid of the first transistor is used as output end Vout, the grid of second transistor is used as input Vin, The source ground of second transistor, the drain electrode of the first transistor is used to apply supply voltage VDD；Also, first is brilliant The gate dielectric layer of body pipe and second transistor is ionic conduction type solid electrolyte.The phase inverter of the present invention has work Voltage is low and high-gain, simple for process, low manufacture cost, the advantages of suitable large area is continuously produced.
Referring to Fig. 1, phase inverter of the invention, comprising：
Substrate 1；
The first deposition structure on the substrate 1；And
The second deposition structure on the substrate 1；
Wherein, the first deposition structure includes：On the substrate 1 first gate electrode 2b, positioned at institute State the first gate dielectric layer 3b on first gate electrode 2b, the first raceway groove on the first gate dielectric layer 3b Layer 4b, the drain electrodes of the first source electrode 5c on the first channel layer 4b and first 5d；Also, described first Deposit structure and constitute the first transistor worked with depletion type pattern；
The second deposition structure includes：On the substrate 1 second gate electrode 2a, positioned at described second The second gate dielectric layer 3a on gate electrode 2a, the second channel layer 4a on the second gate dielectric layer 3a, The drain electrodes of the second source electrode 5a and second 5b on the second channel layer 4a；Also, the second deposition knot Structure constitutes the second transistor worked with enhancement mode；And
The first gate electrode 2b, the first source electrode 5c and the second drain electrode 5b are electrically connected by conductive layer 5e Connect；And
In the phase inverter, the first grid 2b is used as output end Vout, the second grid 2a conducts Input Vin, the second source electrode 5a ground connection, the first drain electrode 5d is for applying supply voltage VDD；And And
The first gate dielectric layer 3b and the second gate dielectric layer 3a is ionic conduction type solid electrolyte.
In another preference, the solid electrolyte with ionic conduction characteristic is independently selected from the following group： Loose oxide dielectric film, sodium alginate film, chitosan film, Methyl Cellulose Hydrogel Films.
In another preference, the solid electrolyte with ionic conduction characteristic is independently selected from the following group： Loose SiO2Film, loose phosphorus doping SiO2Film layer, loose aluminium oxide Al2O3Film, also, described One gate dielectric layer 3b and the second gate dielectric layer 3a thickness are 300nm~5 μm, and specific surface area is 1m2/ g~ 100m2/ g, film pore-size is 1nm~10nm, and proton conductivity is 1 × 10-5S/cm~1 × 10-3S/cm, unit-area capacitance is 0.1~20 μ F/cm2。
In another preference, the first deposition structure and the second deposition structure are located at the same of the substrate Side.
In another preference, the first channel layer 4b is indium zinc oxide (InZnO) film, second ditch Channel layer 4a is indium zinc oxide (InZnO) film or indium gallium zinc oxygen (InGaZnO) film, the first channel layer 4b Thickness with the second channel layer 4a is 10nm~100nm.
In another preference, the phase inverter is integrated.
In another preference, the first source electrode 5c and the second drain electrode 5b are for same structure layer.
In another preference, the first gate electrode 2b, the first source electrode 5c and the second drain electrode 5b Connected by conductive layer 5e.
In another preference, the phase inverter is low-work voltage, high voltage gain type phase inverter.
In another preference, the phase inverter be low-work voltage, high voltage gain type phase inverter, also, " low-work voltage " refers to operating voltage not higher than 3V, and " high-gain " refers under low supply voltage Output voltage (the V of (0.5V~3V)out) to input voltage (Vin) local derviation absolute value be higher than 20.
In another preference, the input voltage (V of the phase inverterin) scope be -1V~1.5V, application Supply voltage (VDD) for a certain value between 0.5~3V scopes, corresponding output voltage (Vout) excursion be 0~VDD, work as VDDDuring=2V, voltage gain is more than 40.
In another preference, the input voltage of the phase inverter has sinusoidal waveform, triangular waveform, noise The combination of waveform or wherein some waveforms.
In another preference, the dielectric substrate 1 is selected from the group：Deposition has thermal oxide SiO2Monocrystalline silicon lining Bottom, glass substrate, plastic supporting base, paper substrate, ceramic substrate.
In another preference, the first gate electrode 2b and the second gate electrode 2a are independently selected from the following group：Indium Tin-oxide (InSnO) film layer, Au film layers, Ag film layers, Al film layers and Cu film layers
In another preference, the first source electrode 5c, the first drain electrode 5d, the second source electrode 5a, the second drain electrode The following group is selected independently in 5b, and conductive layer 5e：InSnO films, Au film layers, Ag film layers, Al are thin Film layer and Cu film layers.
In another preference of the present invention, the solid electrolyte with ionic conduction characteristic is loose oxidation Thing deielectric-coating, sodium alginate film, chitosan film, Methyl Cellulose Hydrogel Films.Preferably loose silica (SiO2) thin Film and loose aluminum oxide (Al2O3) film.
In another preference of the present invention, the channel layer is selected from the group：Indium-zinc oxide laminated film (InZnO), indium gallium zinc oxide laminated film (InGaZnO), the indium-zinc oxide laminated film with different-thickness (InZnO) indium-zinc oxide laminated film (InZnO), with different oxygen or the indium gallium zinc with different-thickness Oxidate compound film (InGaZnO).
Operation principle
The present invention using electron conducting oxide semiconductive thin film as thin film transistor (TFT) (TFTs) raceway groove, using with The solid electrolyte of ionic conduction characteristic makes n-type oxide TFTs, mode of operation is depletion type as gate medium With it is enhanced, and the oxide TFTs connections under two kinds of mode of operations are obtained into full n-type inverter circuit.
Specifically, in the present invention, loose film has the effect of room temperature proton permeability, with room temperature proton conductive Characteristic, is room temperature proton conductor.During work, the moisture in the pore structure absorption air of film, in external electric field Under effect, water-molecule dissociation produces proton (H+), these protons are moved along dispatch from foreign news agency field direction, pore structure and its suction It is attached to H2O molecules or OH on pore structure-Key provide proton migration passage, these protons loose film/ Accumulated at electrode interface, so that induction produces substantial amounts of electronics in electrode side, due to the effect of this ion regulation, Using the loose film as gate medium, the operating voltage of the transistor of making it is extremely low (<2V).Or, in this hair In bright, possessing the organic matter of a large amount of carboxyls or hydroxyl has the effect of room temperature proton permeability, special with room temperature proton conductive Property, it is room temperature proton conductor.During work, the carboxyl or hydroxyl of film produce proton (H in the presence of external electric field+), These protons are moved along dispatch from foreign news agency field direction, and these protons are accumulated at proton conducting membranes/electrode interface, so that in electricity The induction of pole side produces substantial amounts of electronics, due to the effect of this ion regulation, is situated between using the proton conducting membranes as grid Matter, the operating voltage of the transistor of making is extremely low (＜ 2V).
Therefore, ion-conductive solid electrolyte of the present invention has with properties, in the presence of external electric field, Ion present in solid electrolyte is migrated to electrolyte/electrode interface or electrolyte/channel interface, and then in electrode Side or raceway groove side induce one layer and the electrical opposite, quantity of electric charge identical carrier Guinier-Preston zone of ion, so that on boundary Induction produces interface electric double layer at face, and the thickness of this interface electric double layer is minimum (~1nm), its unit area Electric capacity greatly (0.1~20 μ F/cm2), therefore this solid electrolyte has extremely strong electrostatic ability of regulation and control, uses This solid electrolyte is minimum (＜ 2V) as the oxide TFTs of gate medium operating voltage.
In view of this, the operating voltage using this oxide TFTs inverter circuits being formed by connecting is extremely low, fits Close biochemistry sensing, Low Power Consumption Portable electronic product and bionic finished product application.
The preparation method of phase inverter
Present invention also offers a kind of preparation method of low-work voltage phase inverter, comprise the steps of：
(a) substrate 1 is provided；
(b) the first deposition region on the substrate 1 deposits to form the first deposition structure；And in the lining The second deposition region on bottom 1 deposits to form the second deposition structure；
Wherein, the first deposition structure includes：On the substrate 1 first gate electrode 2b, positioned at institute State the first gate dielectric layer 3b on first gate electrode 2b, the first raceway groove on the first gate dielectric layer 3b Layer 4b, the drain electrodes of the first source electrode 5c on the first channel layer 4b and first 5d；And described first sinks Product structure constitutes the first transistor worked with depletion type pattern；
The second deposition structure includes：On the substrate 1 second gate electrode 2a, positioned at described second The second gate dielectric layer 3a on gate electrode 2a, the second channel layer 4a on the second gate dielectric layer 3a, The drain electrodes of the second source electrode 5a and second 5b on the second channel layer 4a；And the second deposition structure Constitute the second transistor worked with enhancement mode；With
(c) the first gate electrode 2b, the first source electrode 5c and the second drain electrode 5b are electrically connected, So as to form the phase inverter described in first aspect present invention.
It is described to deposit to form the first deposition structure and described second in the first deposition region in another preference It is while carrying out or successively carrying out that deposition region, which deposits and to form the second deposition structure,.
In another preference, the step (b) and (c) include：
(i) the first deposition structure in the dielectric substrate 1 deposits graphical first gate electrode 2b, described The second deposition structure in dielectric substrate 1 deposits graphical second gate electrode 2a；
(ii) solid electrolyte membrane of the deposition with ionic conduction characteristic on the first gate electrode 2b, is used as the One gate dielectric layer 3b, solid electrolyte membrane of the deposition with ionic conduction characteristic on the second gate electrode 2a, It is used as the second gate dielectric layer 3b；
(iii) patterned first channel layer 4b is deposited on the first gate dielectric layer 3b, in the second gate Patterned second channel layer 4a is deposited on dielectric layer 3a；With
(iv) patterned conductive film is deposited on the first channel layer 4b and the second channel layer 4a, as The drain electrodes of first source electrode 5c and first 5d, the drain electrode 5b of the second source electrode 5a and second, and conductive layer 5e, wherein institute Conductive layer 5e is stated to be electrically connected the described second drain electrode 5b, the first source electrode 5c and first gate electrode 2b.
In another preference, in the step b), using plasma enhancing technology or collosol and gel The technology deposition solid electrolyte membrane with ionic conduction characteristic, also, it is described special with ionic conduction Property solid electrolyte membrane thickness be 300nm~5 μm, specific surface area is 1m2/ g~100m2/ g, film Pore-size is 1nm~10nm, and proton conductivity is 1 × 10-5S/cm~1 × 10-3S/cm, unit area electricity Hold for 0.1~20 μ F/cm2.It is preferred that the thickness of the solid electrolyte membrane with ionic conduction characteristic For 1 μm.
In another preference, in the step b), using plasma enhancing technology or collosol and gel The technology deposition solid electrolyte membrane with ionic conduction characteristic, also, it is described special with ionic conduction Property solid electrolyte membrane thickness be 300nm~5 μm, proton conductivity be 1 × 10-5S/cm~1 × 10-3S/cm, unit-area capacitance is 0.1~20 μ F/cm2。
In another preference, in the step b), first channel layer is deposited using magnetron sputtering technique 4b and the second channel layer 4a.
Using and product
The phase inverter of the present invention can be used for biochemistry sensing, Low Power Consumption Portable electronic product and bionic Finished product, has broad application prospects.
Main advantages of the present invention include：
1) low-work voltage, high-gain.
The present invention uses the solid electrolyte with ionic conduction characteristic as gate medium, under gate electrode effect With unique interface electric double layer effect, its unit-area capacitance greatly, therefore is adjusted with extremely strong electrostatic Characteristic is controlled, oxide TFTs operating voltage can be greatly reduced.
Simultaneously as the operating voltage of the inverter circuit of the present invention is low, can be compared with being obtained under low supply voltage Larger phase inverter voltage gain is obtained, and the voltage transition region of voltage transmission curve characteristic is narrow, beneficial to improvement Phase inverter dynamic electrical characteristics, so as to reduce electronic product power consumption and improve electric property.
2) cost is reduced.
Due to the super-strong capacitance coupling effect of solid electrolyte, phase inverter of the invention make to alignment request It is low, device making technics cost can be greatly reduced, is continuously produced suitable for large area.Also, the present invention Phase inverter manufacture craft it is simple and easy to apply, repeatability and uniformity it is good, cost of manufacture can be greatly reduced.
In summary, phase inverter that the present invention is provided and preparation method thereof significantly reduces inverter circuit Operating voltage and possess high voltage gain, improve the electrology characteristic of phase inverter, and manufacture craft it is simple, It is with low cost, in the field such as biochemistry sensing, Low Power Consumption Portable electronic product and bionic finished product tool There is very wide application prospect.
With reference to specific embodiment, the present invention is expanded on further.It should be understood that these embodiments are only used for The bright present invention rather than limitation the scope of the present invention.The experiment side of unreceipted actual conditions in the following example Method, generally according to normal condition or according to the condition proposed by manufacturer.Unless otherwise indicated, otherwise hundred Divide than being percentage by weight and parts by weight with number.
Embodiment 1：Phase inverter No.1 and preparation method thereof
The physical arrangement of the phase inverter of the present embodiment is as shown in Figure 1.
Electricity structure：
Electricity structure in Fig. 1 is as follows：In the first deposition region I, first gate electrode 2b, the first gate dielectric layer 3b, First channel layer 4b, the first source electrode 5c and the first drain electrode 5d constitute the first transistor worked with depletion type pattern； In second deposition region II, the second gate electrode 2a, the second gate dielectric layer 3a, the second channel layer 4a, the second source electrode 5a The second transistor worked with enhancement mode is constituted with the second drain electrode 5b.First gate dielectric layer and second gate are situated between Matter layer is ionic conduction type solid electrolyte.
In the present embodiment, it regard first grid 2b as output end (Vout), it regard second grid 2a as input (Vin), the second source electrode 5a ground connection applies supply voltage (V on the first drain electrode 5dDD).Also, first gate electrode 2b, the first source electrode 5c, and the second drain electrode 5b are connected by conductive layer 5e, so as to constitute phase inverter.
Material：
In the present embodiment, the selection glass substrate of dielectric substrate 1；Conductive layer 2a and 2b selection indium tin as gate electrode Oxide (InSnO) film layer；Gate dielectric layer 3 selects loose SiO2Film；Channel layer 4a selects InGaZnO films, Channel layer 4b selects InZnO films；Source electrode 5a and 5c, drain electrode 5b and 5d and conductive layer 5e use InSnO films.
Preparation process：
Step 1：Glass substrate 1 is strictly cleaned, glass substrate is immersed into alcohol, deionized water successively surpasses Sound is cleaned 10 minutes, is then rinsed repeatedly using deionized water, is finally dried up with nitrogen gun stand-by.
Step 2：Using magnetron sputtering technique, in the surface of glass substrate 1 deposition, mutually disconnected graphical InSnO is conductive Film layer 2a and 2b, are used as the bottom gate thin film of thin film transistor (TFT)；
Step 3：Using PECVD, using silane and oxygen as reacting gas, One layer of loose SiO is deposited on InSnO conductive layers 2a and 2b2Film 3 is as gate dielectric layer, loose SiO2The thickness of film Spend for 1 μm；
Step 4：Using magnetron sputtering technique region I loose SiO2The InZnO of a layer pattern is deposited on film Film 4b as InZnO thin film transistor (TFT)s channel layer；The II loose SiO in region2A layer pattern is deposited on film The InGaZnO films 4a of change as InGaZnO thin film transistor (TFT)s channel layer；
Step 5：By magnetron sputtering membrane process, continuation deposits patterned InSnO on channel layer 4a and 4b Film is as source, drain electrode and conductive layer, while 5b, 5c are connected by InSnO conductive layers 5e with 2b.
Test result：
The InZnO thin film transistor (TFT) operating voltages obtained in the I of region<1.5V, in depletion type mode of operation；Region II The InGaZnO thin film transistor (TFT) operating voltages of interior acquisition<1.5V, in enhanced mode of operation, so as to be had Low-work voltage exhausts support type phase inverter.
Using the grid 2a of InGaZnO thin film transistor (TFT)s as input, and by the grid 2b of InZnO thin film transistor (TFT)s As output end, while applying supply voltage V at 5dDD, it is hereby achieved that phase inverter electric property.When VDDDuring=2V, voltage gain (- dVout/dVin) it is about 45.
Embodiment 2：Phase inverter No.2 and preparation method thereof
The physical arrangement of the phase inverter of the present embodiment is as shown in Figure 1.
Electricity structure：
Electricity structure in the present embodiment is same as Example 1, will not be described here.
Material：
In the present embodiment, the selection glass substrate of dielectric substrate 1；Conductive layer 2a and 2b selection indium tin as gate electrode Oxide (InSnO) film layer；Gate dielectric layer 3 selects loose phosphorus doping SiO2Film layer；Channel layer 4a selections are thin InZnO film layers, the thick InZnO film layers of channel layer 4b selections；Source electrode 5a and 5c, drain electrode and are led 5b and 5d Electric layer 5e uses Cu films.
Preparation process：
Step 1：Glass substrate 1 is strictly cleaned, glass substrate is immersed into alcohol, deionized water successively surpasses Sound is cleaned 10 minutes, is then rinsed repeatedly using deionized water, is finally dried up with nitrogen gun stand-by；
Step 2：Using magnetron sputtering technique, in the surface of glass substrate 1 deposition, mutually disconnected graphical InSnO is conductive Film layer 2a and 2b, are used as the bottom gate thin film of thin film transistor (TFT)；
Step 3：Using PECVD, it is anti-to use silane phosphine gaseous mixture and oxygen Should gas, one layer of loose phosphorus doping SiO of deposition on InSnO conductive layers 2a and 2b2Film 3 is as gate dielectric layer, and film is thick Spend for 1 μm；
Step 4：Using magnetron sputtering technique region I loose phosphorus doping SiO2A layer pattern is deposited on film 3 InZnO films 4b as InZnO thin film transistor (TFT)s channel layer；The II loose phosphorus doping SiO in region2Sunk on film 3 The InZnO films 4a for accumulating a layer pattern is used as the channel layer of InZnO thin film transistor (TFT)s；
Step 5：By thermal evaporation process, continuation deposited on channel layer 4a and 4b patterned Cu films as source, Drain electrode and conductive layer, while 5b, 5c are connected by Cu conductive layers 5e with 2b.
Test result：
The InZnO thin film transistor (TFT) operating voltages obtained in the I of region<1.5V, in depletion type mode of operation；Region II The InZnO thin film transistor (TFT) operating voltages of interior acquisition<1.5V, in enhanced mode of operation, so as to obtain with low Operating voltage exhausts support type phase inverter.
Using the grid 2a of the InZnO thin film transistor (TFT)s in the II of region as input, and the InZnO in the I of region is thin The grid 2b of film transistor is as output end, while applying supply voltage V at 5dDD, it is hereby achieved that anti-phase Device electric property.Work as VDDDuring=2V, voltage gain (- dVout/dVin) it is about 30.
Embodiment 3：Phase inverter No.3 and preparation method thereof
The physical arrangement of the phase inverter of the present embodiment is as shown in Figure 1.
Electricity structure：
Electricity structure in the present embodiment is same as Example 1, will not be described here.
Material：
In the present embodiment, dielectric substrate 1 is selected covered with thermal oxide SiO2Monocrystalline substrate；As gate electrode Conductive layer 2a and 2b select Au film layers；Gate dielectric layer 3 selects loose aluminum oxide film；Channel layer 4a selections are oxygen-enriched InZnO film layers, channel layer 4b selects oxygen debt InZnO film layers；Source electrode 5a and 5c, drain electrode 5b and 5d with And conductive layer 5e uses Ag films.
Preparation process：
Step 1：Substrate 1 is strictly cleaned, alcohol, deionized water are immersed the substrate in successively and is cleaned by ultrasonic 10 Minute, then rinsed, finally dried up with nitrogen gun stand-by repeatedly using deionized water；
Step 2：Using thermal evaporation techniques in the mutual disconnected graphical Au conductive membrane layers 2a of the surface of substrate 1 deposition And 2b, it is used as the bottom gate thin film of thin film transistor (TFT)；
Step 3：Using PECVD, using trimethyl aluminium and oxygen as reaction gas, The trimethylaluminum gas brings reaction cavity into using Ar as carrier gas, is deposited on Au conductive membrane layers 2a and 2b One layer of loose aluminum oxide film 3 is as gate dielectric layer, and film thickness is 1 μm；
Step 4：Owing for one layer pattern is deposited on region I loose aluminum oxide film 3 using magnetron sputtering technique Oxygen InZnO films 4b is not passed through oxygen as the channel layer of InZnO thin film transistor (TFT)s during deposition, Ar flows are 14sccm, sputtering power is 100W, and deposition pressure is 0.5Pa；Deposited on region II loose aluminum oxide film 3 The oxygen-enriched InZnO films 4a of one layer pattern is as the channel layer of InZnO thin film transistor (TFT)s, oxygen flow during deposition For 4sccm, Ar flows are 14sccm, and sputtering power is 100W, and deposition pressure is 0.5Pa；
Step 5：By thermal evaporation process, continuation deposited on channel layer 4a and 4b patterned Ag films as source, Drain electrode and conductive layer, while 5b, 5c are connected by Ag conductive layers 5e with 2b.
Test result：
The InZnO thin film transistor (TFT) operating voltages obtained in the I of region<1.5V, in depletion type mode of operation；Region II The InZnO thin film transistor (TFT) operating voltages of interior acquisition<1.5V, in enhanced mode of operation, so as to obtain with low Operating voltage exhausts support type phase inverter.
Using the grid 2a of the InZnO thin film transistor (TFT)s in the II of region as input, and the InZnO in the I of region is thin The grid 2b of film transistor is as output end, while applying supply voltage V at 5dDD, it is hereby achieved that anti-phase Device electric property.
Work as VDDDuring=2V, voltage gain (- dVout/dVin) it is about 35.
Comparative example 1：Phase inverter electrology characteristic test result
Fig. 2 shows the electrology characteristic test result of the phase inverter of the present invention, and wherein gate dielectric layer 3a and 3b is by dredging The solid electrolyte with ionic conduction characteristic of loose film formation.
In the comparative example 1, when one is the solid electrolyte with ionic conduction characteristic in gate dielectric layer 3a and 3b Loose film, and another is the gate dielectric membrane of high-compactness that (i.e. non-solid-state with ionic conduction characteristic is electric Solve matter) when, measurement result shows, using high-compactness gate dielectric membrane respective transistor in relatively low voltage Under scope (<The electric property of transistor can not 3V) be realized, under this voltage range, grid voltage is led to channel layer The regulation and control failure of electric energy power, i.e. under fixed channel source, drain electrode bias condition, channel current is not with grid electricity The change of pressure and change, therefore the phase inverter accordingly made can not be realized and exhaust support type inverter function.
The result of above-described embodiment 1-3 and comparative example 1 shows that the low-work voltage using specific structure of the present invention is anti-phase Device, due to its first gate dielectric layer and the second gate dielectric layer solid electrolyte of the use with ionic conduction characteristic (such as loose film with ionic conduction characteristic), therefore the transistor prepared can be under relatively low voltage range Work (<2V), and the support type phase inverter that exhausts for preparing has the very excellent properties such as high voltage gain.
All documents referred in the present invention are all incorporated as reference in this application, just as each document It is individually recited as with reference to such.In addition, it is to be understood that after the above-mentioned instruction content of the present invention has been read, Those skilled in the art can make various changes or modifications to the present invention, and these equivalent form of values equally fall within this Shen Please appended claims limited range.

Claims (10)

1. a kind of phase inverter, it is characterised in that include：
Substrate；
The first deposition structure on the substrate；And
The second deposition structure on the substrate；
Wherein, the first deposition structure includes：On the substrate first gate electrode, positioned at described first The first gate dielectric layer on gate electrode, the first channel layer on first gate dielectric layer, positioned at described first The first source electrode and the first drain electrode on channel layer；Also, the first deposition structure is constituted to be worked with depletion type pattern The first transistor；
The second deposition structure includes：On the substrate the second gate electrode, positioned at second gate electrode On the second gate dielectric layer, the second channel layer on second gate dielectric layer, positioned at second channel layer On the second source electrode and second drain electrode；Also, the second deposition structure constitutes second worked with enhancement mode Transistor；And
The first gate electrode, first source electrode and second drain electrode are electrically connected by conductive layer；And
In the phase inverter, the first grid is used as output end Vout, the second grid is used as input Vin, Second source ground, described first drains for applying supply voltage VDD；And
First gate dielectric layer and the second gate dielectric layer are ionic conduction type solid electrolyte.
2. phase inverter as claimed in claim 1, it is characterised in that the ionic conduction type solid electrolyte is independent Ground is selected from the group：Loose oxide dielectric film, sodium alginate film, chitosan film, Methyl Cellulose Hydrogel Films.
3. phase inverter as claimed in claim 1, it is characterised in that the ionic conduction type solid electrolyte is independent Ground is selected from the group：Loose SiO2Film, loose phosphorus doping SiO2Film layer, loose aluminium oxide Al2O3Film, and And,
First gate dielectric layer and second gate thickness of dielectric layers are 300nm~5 μm, and specific surface area is 1m2/ g~ 1000m2/ g, film pore-size is 1nm~10nm, and proton conductivity is 1 × 10-5S/cm~1 × 10-3S/cm, Unit-area capacitance is 0.1~100 μ F/cm2。
4. phase inverter as claimed in claim 1, it is characterised in that first channel layer is indium zinc oxide (InZnO) film, second channel layer be indium zinc oxide (InZnO) film or indium gallium zinc oxygen (InGaZnO) film, The thickness of first channel layer and the second channel layer is 10nm~100nm.
5. phase inverter as claimed in claim 1, it is characterised in that the choosing of the input voltage independence of the phase inverter From the following group：Sinusoidal waveform, triangular waveform, noise waveform or their any combination.
6. phase inverter as claimed in claim 1, it is characterised in that the phase inverter is low-work voltage, high electricity Gain-type phase inverter is pressed, " low-work voltage " refers to operating voltage not higher than 3V, and described " high voltage increases Benefit " refers to the output voltage (V under the low supply voltageout) to input voltage (Vin) local derviation absolute value be higher than 20.
7. phase inverter as claimed in claim 1, it is characterised in that the input voltage (V of the phase inverterin) scope For -1V~1.5V, the supply voltage (V of applicationDD) be in 0.5~3V scopes between when, corresponding output voltage (Vout) Scope is 0~VDD, wherein, work as VDDDuring=2V, voltage gain is more than 40.
8. a kind of preparation method of phase inverter, is comprised the steps of：
(a) substrate is provided；
(b) the first deposition region over the substrate deposits to form the first deposition structure；And over the substrate The second deposition region deposit to form the second deposition structure；
Wherein, the first deposition structure includes：On the substrate first gate electrode, positioned at described first The first gate dielectric layer on gate electrode, the first channel layer on first gate dielectric layer, positioned at described first The first source electrode and the first drain electrode on channel layer；And the first deposition structure constitutes what is worked with depletion type pattern The first transistor；
The second deposition structure includes：On the substrate the second gate electrode, positioned at second gate electrode On the second gate dielectric layer, the second channel layer on second gate dielectric layer, positioned at second channel layer On the second source electrode and second drain electrode；And the second deposition structure constitutes the second crystalline substance worked with enhancement mode Body pipe；With
(c) first gate electrode, first source electrode and second drain electrode are electrically connected, so as to be formed Phase inverter described in claim 1.
9. preparation method as claimed in claim 8, it is characterised in that the step (b) and (c) include：
(i) the first deposition structure in the dielectric substrate deposits graphical first gate electrode, in the insulation lining The second deposition structure on bottom deposits graphical second gate electrode；
(ii) solid electrolyte membrane of the deposition with ionic conduction characteristic in the first gate electrode, is used as the first grid Dielectric layer, solid electrolyte membrane of the deposition with ionic conduction characteristic, is used as second gate on second gate electrode Dielectric layer；
(iii) patterned first channel layer is deposited on first gate dielectric layer, on second gate dielectric layer Deposit patterned second channel layer；With
(iv) patterned conductive film is deposited on first channel layer and the second channel layer, is used as the first source electrode With the first drain electrode, the second source electrode and the second drain electrode, and conductive layer, wherein the conductive layer described second will drain, First source electrode and first gate electrode are electrically connected.
10. a kind of electronic product, it is characterised in that the electronic product contains any described in claim 1-7 Phase inverter.
CN201610029456.XA 2016-01-15 2016-01-15 Low-work voltage phase inverter and preparation method thereof Pending CN106981486A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610029456.XA CN106981486A (en) 2016-01-15 2016-01-15 Low-work voltage phase inverter and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610029456.XA CN106981486A (en) 2016-01-15 2016-01-15 Low-work voltage phase inverter and preparation method thereof

Publications (1)

Publication Number Publication Date
CN106981486A true CN106981486A (en) 2017-07-25

Family

ID=59340608

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610029456.XA Pending CN106981486A (en) 2016-01-15 2016-01-15 Low-work voltage phase inverter and preparation method thereof

Country Status (1)

Country Link
CN (1) CN106981486A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108389909A (en) * 2018-01-31 2018-08-10 京东方科技集团股份有限公司 Thin film transistor (TFT) and preparation method thereof, display device and detection ion concentration method
CN109360857A (en) * 2018-08-15 2019-02-19 南昌工程学院 A kind of degradable self-supporting film transistor device and preparation method thereof
CN113013253A (en) * 2021-02-24 2021-06-22 中国科学院宁波材料技术与工程研究所 P-type thin film transistor, preparation method thereof and phase inverter

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101681927A (en) * 2007-05-18 2010-03-24 佳能株式会社 Inverter manufacturing method and inverter
CN104835835A (en) * 2015-03-18 2015-08-12 南京华印半导体有限公司 Solid electrolyte film transistor and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101681927A (en) * 2007-05-18 2010-03-24 佳能株式会社 Inverter manufacturing method and inverter
CN104835835A (en) * 2015-03-18 2015-08-12 南京华印半导体有限公司 Solid electrolyte film transistor and manufacturing method thereof

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
张进: "《基于质子导体膜栅介质的薄膜晶体管研究》", 《中国博士学位论文全文数据库，信息科技辑》 *
朱德明等: "《基于P掺杂SiO2 为栅介质的超低压侧栅薄膜晶体管》", 《物理学报》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108389909A (en) * 2018-01-31 2018-08-10 京东方科技集团股份有限公司 Thin film transistor (TFT) and preparation method thereof, display device and detection ion concentration method
WO2019149004A1 (en) * 2018-01-31 2019-08-08 京东方科技集团股份有限公司 Thin-film transistor and preparation method therefor, display apparatus, and method for detecting ion concentration
CN109360857A (en) * 2018-08-15 2019-02-19 南昌工程学院 A kind of degradable self-supporting film transistor device and preparation method thereof
CN113013253A (en) * 2021-02-24 2021-06-22 中国科学院宁波材料技术与工程研究所 P-type thin film transistor, preparation method thereof and phase inverter
CN113013253B (en) * 2021-02-24 2022-06-28 中国科学院宁波材料技术与工程研究所 P-type thin film transistor, preparation method thereof and phase inverter

Similar Documents

Publication Publication Date Title
Jiang et al. Ultralow-voltage transparent electric-double-layer thin-film transistors processed at room-temperature
CN108807546A (en) Oxide thin film transistor and its manufacturing method
CN106128944A (en) The manufacture method of metal oxide thin-film transistor array base palte
CN105810746B (en) N-type TFT
CN104766888A (en) High-dielectric-constant gate dielectric composite channel field effect transistor and preparing method thereof
KR101694270B1 (en) Substrate for high mobility electronic sensor and manufacturing method thereof
CN102347368A (en) Transistor, method of manufacturing transistor, and electronic device including transistor
CN107644878B (en) Phase inverter and preparation method thereof
CN106981486A (en) Low-work voltage phase inverter and preparation method thereof
Zhou et al. Flexible transparent junctionless TFTs with oxygen-tuned indium-zinc-oxide channels
CN107611180A (en) A kind of vertical channel structure electric double layer thin film transistor (TFT) and preparation method thereof
CN110233156A (en) The production method and thin film transistor base plate of thin film transistor base plate
CN113363328A (en) Thin film transistor and preparation method thereof
CN107919396B (en) Based on WO3/Al2O3Zero-grid-source-spacing diamond field effect transistor with double-layer grid medium and manufacturing method
CN106298815A (en) Thin film transistor (TFT) and preparation method thereof, array base palte and display device
CN104766891B (en) A kind of source-drain electrode and preparation method, thin film transistor (TFT) and preparation method of thin film transistor (TFT)
CN107221563A (en) A kind of bottom gate self-alignment structure metal oxide thin-film transistor and preparation method thereof
CN101393966A (en) Dual dielectric layer organic field-effect transistors and preparation thereof
CN104051543A (en) Double-layer gate dielectric thin film transistor with electrochromism characteristic
CN102856494A (en) Organic bipolar field effect transistor and preparation method thereof
TWI426613B (en) Power-generating module with solar cell and method for fabricating the same
CN105304497B (en) Thin film transistor, array substrate and related manufacturing method
CN106601621A (en) Method for preparing thin-film transistor and thin-film transistor with conductive isolated island
CN108598096A (en) Tft array substrate and preparation method thereof
CN105355663B (en) A kind of hydrogen passive oxidation zinc-base double channel layer film transistor and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination