CN106973509A - PCB film filler increasing layer methods - Google Patents
PCB film filler increasing layer methods Download PDFInfo
- Publication number
- CN106973509A CN106973509A CN201710285951.1A CN201710285951A CN106973509A CN 106973509 A CN106973509 A CN 106973509A CN 201710285951 A CN201710285951 A CN 201710285951A CN 106973509 A CN106973509 A CN 106973509A
- Authority
- CN
- China
- Prior art keywords
- increasing layer
- pcb
- substrate
- copper
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
Abstract
The invention belongs to printed circuit board (PCB) manufacturing technology field, it is related to a kind of PCB films filler increasing layer method, step includes drilling, plating, image transfer and pressing successively.Of the invention directly melted with film produces consent effect, not only reduces and reduces technological process, reduce technology difficulty, also reduce time and cost, improve yield, with obvious market competition advantage.
Description
Technical field
The present invention relates to printed circuit board (PCB) manufacturing technology field, the high PCB films of more particularly to a kind of energy-efficient yield
Filler increasing layer method.
Background technology
Filling holes with resin technique is often used in the manufacture of multi-layer PCB, this technology utilization resin clogs via hole, so
Copper facing is carried out in hole surface afterwards, because this fabrication hole and pitch of holes are small, wiring density can be improved, reduce the face of plate
Product.
Traditional process flow for filling holes with resin includes:Plating → consent → grinding → circuit → pressing.This technique is present
Shortcoming it is as follows:
1. consent flow is complicated cumbersome, it is necessary to a special technique unit after copper facing, and the technique institute spent material bag
Include:Plug socket resin, ceramic brush wheel/abrasive band etc., management trouble;
2. baking needs baking box after consent, and power consumption is big, and the variation of material harmomegathus is also big, and abrasive wire largely uses water, the energy
Consumption is big, and cost is very high;
3. the technique consent needs consummate operating personnel to can be only achieved accurate contraposition, otherwise can produce hole inner product resin different
Often, grinding can produce aperture leakage base material, or even integral face copper shortfall risk again if control is bad.
Therefore, it is necessary to provide a kind of new method to solve the above problems.
The content of the invention
It is a primary object of the present invention to provide a kind of PCB film filler increasing layer methods that energy-efficient yield is high.
The present invention is achieved through the following technical solutions above-mentioned purpose:A kind of PCB films filler increasing layer method, step is wrapped successively
Include:
1. drill:Via hole is processed on substrate;
2. electroplate:The copper facing on substrate, carries out levels conducting;
3. image transfer:Circuit image is transferred on copper face using photoresists and circuit moulding process is completed;
4. press:Film and copper foil, Ran Houre are sticked into substrate both sides respectively.
Specifically, the via hole aperture is not less than 0.2mm.
Specifically, the film condensation material is polypropylene.
Using above-mentioned technical proposal, the beneficial effect of technical solution of the present invention is:
Of the invention directly melted with film produces consent effect, not only reduces and reduces technological process, reduces technique
Difficulty, also reduces time and cost, improves yield, with obvious market competition advantage.
Brief description of the drawings
Fig. 1 is the local section schematic diagram after electroplating substrate;
Fig. 2 is the local section schematic diagram of product after pressing.
Numeral is represented in figure:
1- substrates,
11- via holes;
2- copper coatings;
3- films;
4- copper foils.
Embodiment
A kind of PCB films filler increasing layer method, step includes successively:
1. drill:Via hole is processed on substrate;
2. electroplate:The copper facing on substrate, carries out levels conducting;
3. image transfer:Image on film is transferred on copper face and circuit moulding process is completed;
4. press:Film and copper foil are sticked into substrate both sides respectively, then hot pressing increasing layer.
The present invention is described in further detail with reference to specific embodiment.
Embodiment
1. some via holes 11 are processed on substrate 1, and via hole 11 will be used as the conducting position of the positive and negative circuit of substrate 1
Put.For the filler after realizing, require that the aperture of via hole 11 is not less than 0.2mm here.
2. copper coating 2 is plated in the whole surface of substrate 1, the copper face positioned at the surface of substrate 1 will be used to be molded circuit, lead
The copper of the inwall of through hole 11 make above and below layers of copper conducting, as shown in Figure 1.
3. photoresists are coated on copper-plated substrate 1, photoresists is exposed with the film of line map elephant, washed away not dry
Photoresists, the copper face exposed is etched away, formed circuit.
4. film 3 and copper foil 4 are sticked into the both sides of substrate 1 with circuit respectively, then hot pressing increasing layer, the material of film 3
It is that the portion of material of both sides film 3 is automatically filled in via hole 11 and produces buried via hole effect in polypropylene, hot pressing, as shown in Figure 2.
Because in hot pressing, the film 3 of both sides can melt generation mobility, then part is filled out into via hole 11
It is full, thus serve the effect of consent.There is following technical advantage compared with filling holes with resin technique:
1. two technological processes of consent and grinding are eliminated, technological process is reduced, reduces technology difficulty, when reducing
Between and cost, the market competitiveness is with the obvious advantage.
2. in filling holes with resin technique, material is that material is polypropylene outside resin, hole in hole, and both have obvious boundary
Layer, layering is easily produced by thermal shock;And the interior exterior materials of via hole 11 are consistent in this technique, so material in hot pressing metapore
It will not be layered, will not also have a negative impact even if by thermal shock.
3. grinding easily causes the exceptions such as aperture dew base material, face copper thickness deficiency;Grinding steps are not present in this technique, so
Above undesirable condition can thoroughly be avoided.
4. resin baking flow is reduced, is had very great help to improving harmomegathus difference after baking.
Above-described is only some embodiments of the present invention.For the person of ordinary skill of the art, not
On the premise of departing from the invention design, various modifications and improvements can be made, these belong to the protection model of the present invention
Enclose.
Claims (3)
1. a kind of PCB films filler increasing layer method, it is characterised in that step includes successively:
1. drill:Via hole is processed on substrate;
2. electroplate:The copper facing on substrate, carries out levels conducting;
3. image transfer:Circuit image is transferred on copper face using photoresists and circuit moulding process is completed;
4. press:Film and copper foil are sticked into substrate both sides respectively, then hot pressing increasing layer.
2. PCB films filler increasing layer method according to claim 1, it is characterised in that:The via hole aperture is not less than
0.2mm。
3. PCB films filler increasing layer method according to claim 1, it is characterised in that:The film condensation material is polypropylene.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710285951.1A CN106973509A (en) | 2017-04-27 | 2017-04-27 | PCB film filler increasing layer methods |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710285951.1A CN106973509A (en) | 2017-04-27 | 2017-04-27 | PCB film filler increasing layer methods |
Publications (1)
Publication Number | Publication Date |
---|---|
CN106973509A true CN106973509A (en) | 2017-07-21 |
Family
ID=59332793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710285951.1A Withdrawn CN106973509A (en) | 2017-04-27 | 2017-04-27 | PCB film filler increasing layer methods |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN106973509A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101336052A (en) * | 2008-07-30 | 2008-12-31 | 惠州中京电子科技有限公司 | Jack process of printed circuit board |
CN102143651A (en) * | 2010-01-28 | 2011-08-03 | 竞陆电子(昆山)有限公司 | Inner layer buried hole structure for multi-layer high density interconnected printed circuit board |
JP2016025307A (en) * | 2014-07-24 | 2016-02-08 | 日立化成株式会社 | Wiring board manufacturing method and wiring board |
CN105744766A (en) * | 2016-04-05 | 2016-07-06 | 苏州市惠利华电子有限公司 | Fabrication method of high density interconnector (HDI) plate |
-
2017
- 2017-04-27 CN CN201710285951.1A patent/CN106973509A/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101336052A (en) * | 2008-07-30 | 2008-12-31 | 惠州中京电子科技有限公司 | Jack process of printed circuit board |
CN102143651A (en) * | 2010-01-28 | 2011-08-03 | 竞陆电子(昆山)有限公司 | Inner layer buried hole structure for multi-layer high density interconnected printed circuit board |
JP2016025307A (en) * | 2014-07-24 | 2016-02-08 | 日立化成株式会社 | Wiring board manufacturing method and wiring board |
CN105744766A (en) * | 2016-04-05 | 2016-07-06 | 苏州市惠利华电子有限公司 | Fabrication method of high density interconnector (HDI) plate |
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Legal Events
Date | Code | Title | Description |
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PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WW01 | Invention patent application withdrawn after publication | ||
WW01 | Invention patent application withdrawn after publication |
Application publication date: 20170721 |