CN106972033A - Array base palte and its manufacture method, display panel and display device - Google Patents
Array base palte and its manufacture method, display panel and display device Download PDFInfo
- Publication number
- CN106972033A CN106972033A CN201710380566.5A CN201710380566A CN106972033A CN 106972033 A CN106972033 A CN 106972033A CN 201710380566 A CN201710380566 A CN 201710380566A CN 106972033 A CN106972033 A CN 106972033A
- Authority
- CN
- China
- Prior art keywords
- insulating barrier
- array base
- base palte
- layer
- protective layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 106
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 69
- 239000010410 layer Substances 0.000 claims abstract description 256
- 230000004888 barrier function Effects 0.000 claims abstract description 156
- 239000011241 protective layer Substances 0.000 claims abstract description 149
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 239000010408 film Substances 0.000 claims description 125
- 239000012212 insulator Substances 0.000 claims description 104
- 239000010409 thin film Substances 0.000 claims description 72
- 239000011229 interlayer Substances 0.000 claims description 58
- 238000005530 etching Methods 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 230000008021 deposition Effects 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000012216 screening Methods 0.000 claims description 2
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 claims 1
- 238000002834 transmittance Methods 0.000 abstract description 19
- 230000008569 process Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 18
- 230000001681 protective effect Effects 0.000 description 12
- 238000000151 deposition Methods 0.000 description 9
- 239000002362 mulch Substances 0.000 description 9
- 230000035515 penetration Effects 0.000 description 9
- MEYZYGMYMLNUHJ-UHFFFAOYSA-N tunicamycin Natural products CC(C)CCCCCCCCCC=CC(=O)NC1C(O)C(O)C(CC(O)C2OC(C(O)C2O)N3C=CC(=O)NC3=O)OC1OC4OC(CO)C(O)C(O)C4NC(=O)C MEYZYGMYMLNUHJ-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical group [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000012528 membrane Substances 0.000 description 5
- -1 wherein Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of array base palte and its manufacture method, display panel and display device.The array base palte includes substrate and the first insulating barrier and the second insulating barrier on substrate, and the manufacture method of the array base palte includes：Before the first insulating barrier is made, protective layer is made, wherein, protective layer is located at least in the picture element display area of array base palte；In picture element display area, to the first insulating barrier grooving, wherein, the bottom land of groove is located at protective layer；Remove the protective layer positioned at bottom land；Removing after the protective layer of bottom land, making the second insulating barrier.Pass through the present invention, reduce film layer number of interfaces in pixel display area in array base palte, film layer interface fiber-loss is reduced, light transmittance is high, the technical process does not destroy the homogeneity of remaining thicknesses of layers after the grooving of picture element display area simultaneously, and the brightness homogeneity that light is passed through after array base palte in pixel display area is good.
Description
Technical field
The present invention relates to array base palte technical field, more particularly, to a kind of array base palte and its manufacture method, display
Panel and display device.
Background technology
Nowadays with high pixel density (Pixels Per Inch, PPI) and the market demand of device is highlighted, compels
Be essential the light transmittance of display panel to be lifted.And conventional compression light shield layer and thin film transistor (TFT) (Thin Film
Transistor, TFT) layer size mode due to being limited by TFT device performance requirements, the lifting to light transmittance has
Limit, therefore simplified film layer structure gradually shows its advantage.
In conventional display panels, array base palte is needed through excessive by multiple film layer structure composition, light penetration array base palte
Individual film layer interface, and light can produce fiber-loss in film layer interface, influence the display effect of display panel.
In order to reduce the film layer number of interfaces of light penetration array base palte, the fiber-loss of film layer interface, lifting are reduced
In light transmittance, existing process processing procedure, channel design is done in picture element display area, namely in picture element display area by array base
Part film layer etching in plate, when making film layer above slot structure, the material of this top film layer is deposited in groove, so as to reach
Reduce the purpose of the film layer number of interfaces of light penetration array base palte.
But the etching technics processing procedure, which can be crossed, carves the film layer that part is located at bottom land, should be partially etched positioned at the film layer of bottom land
Afterwards, its residual film thickness homogeneity deteriorates, and necessarily causes the fluctuation of brightness in display surface plate, is constituted for many four pieces of display panels
Super large display, the fluctuation of brightness between each display surface plate is also resulted in, so as to influence the homogeneity of display panel brightness.And
And, the film layer that picture element display area is located at bottom land is thicker by the thickness of over etching, and the homogeneity deterioration of its residual film is more obvious.
Therefore it provides a kind of light transmittance height and the homogeneous array base palte of brightness and its manufacture method, display panel
And display device, it is this area urgent problem to be solved.
The content of the invention
In view of this, the invention provides a kind of array base palte and its manufacture method, display panel and display device, solve
Influence the homogeneous technical problem of panel luminance due to residual film in the prior art.
In order to solve the above-mentioned technical problem, the present invention proposes a kind of manufacture method of array base palte.
The array base palte includes substrate and the first insulating barrier and the second insulating barrier on substrate, the system of the array base palte
The method of making includes：Before the first insulating barrier is made, protective layer is made, wherein, protective layer is located at least in the pixel of array base palte
Viewing area；In picture element display area, to the first insulating barrier grooving, wherein, the bottom land of groove is located at protective layer；Remove and be located at bottom land
Protective layer；Removing after the protective layer of bottom land, making the second insulating barrier.
Alternatively, array base palte also includes the thin film transistor (TFT) being arranged on substrate；First insulating barrier is brilliant positioned at film
Cushion between the active layer and substrate of body pipe, the gate insulator between active layer and the grid of thin film transistor (TFT)
And/or the interlayer insulating film between the source-drain electrode and gate insulator of thin film transistor (TFT).
Alternatively, array base palte also includes light shield layer；Make protective layer the step of be specially：Before cushion is made,
In the overall protective mulch of the plate face of substrate；On substrate the step of protective mulch after, make array base palte cushion
The step of before, this method also includes：Light shield layer is integrally covered in protective layer；The overall light shield layer covered is performed etching to be formed
The pattern of light shield layer.
Alternatively, array base palte also includes light shield layer；Before the step of making protective layer, this method also includes：In base
The plate face of plate integrally covers light shield layer；The pattern to form light shield layer is performed etching to the overall light shield layer covered；Make protective layer
The step of be specially：After the step of forming the pattern of light shield layer, made and protected in the position of picture element display area by mould
Sheath.
Alternatively, make light shield layer and the step of protective layer after, the step of to the first insulating barrier grooving before, the party
Method also includes：Cushion, gate insulator and interlayer insulating film are made successively；The step of to the first insulating barrier grooving is specially：
After the interlayer insulating film that completes, in picture element display area, interlayer insulating film, gate insulator and cushion are dug
Groove；The step of making the second insulating barrier be specially：The planarization layer of array base palte is made, wherein, planarization layer filling slot.
Alternatively, make light shield layer and the step of protective layer after, the step of to the first insulating barrier grooving before, the party
Method also includes：Cushion and gate insulator are made successively；The step of to the first insulating barrier grooving is specially：In the grid that complete
After the insulating barrier of pole, in picture element display area, grooving is carried out to gate insulator and cushion；In the step to the first insulating barrier grooving
After rapid, remove before the protective layer of bottom land, method also includes：Interlayer insulating film is made on gate insulator, wherein,
Interlayer insulating film is deposited in groove；Remove the interlayer insulating film of deposition in groove；The step of making the second insulating barrier be specially：Make
The planarization layer of array base palte, wherein, planarization layer filling slot.
Alternatively, array base palte also includes the thin film transistor (TFT) being arranged on substrate；First insulating barrier is brilliant positioned at film
Cushion between the grid and substrate of body pipe, the gate insulator between grid and the active layer of thin film transistor (TFT) and/
Or the protection insulating barrier between active layer and the source-drain electrode of thin film transistor (TFT).
Alternatively, the step of making protective layer is specially：Before cushion is made, guarantor is integrally covered in the plate face of substrate
Sheath；After the step of making protective layer, the step of to the first insulating barrier grooving before, method also includes：Make successively slow
Rush layer, gate insulator and protection insulating barrier；The step of to the first insulating barrier grooving is specially：In the protection insulating barrier that completes
Afterwards, in picture element display area, grooving is carried out to protection insulating barrier, gate insulator and cushion；Make the step of the second insulating barrier
It is rapid to be specially：The planarization layer of array base palte is made, wherein, planarization layer filling slot.
Alternatively, after the step of making protective layer, the step of to the first insulating barrier grooving before, this method is also wrapped
Include：Cushion and gate insulator are made successively；The step of to the first insulating barrier grooving is specially：In the gate insulator that completes
After layer, in picture element display area, grooving is carried out to gate insulator and cushion；The step of to the first insulating barrier grooving it
Afterwards, remove before the protective layer of bottom land, method also includes：Protection insulating barrier is made on gate insulator, wherein, protection
Insulating layer deposition is in groove；Remove the protection insulating barrier of deposition in groove；The step of making the second insulating barrier be specially：Make array
The planarization layer of substrate, wherein, planarization layer filling slot.
Alternatively, protective layer is metal film.
Alternatively, to the first insulating barrier grooving the step of is specially：The first insulating barrier grooving by the way of dry etching；Remove
The step of positioned at the protective layer of bottom land is specially：The protective layer of bottom land is removed by the way of wet etching.
Alternatively, metal film is indium tin oxide transparent conductive semiconductor film.
In order to solve the above-mentioned technical problem, the present invention proposes a kind of array base palte.The array base palte is provided using the present invention
The manufacture method of any one array base palte be made.
In order to solve the above-mentioned technical problem, the present invention proposes a kind of display panel.The display panel includes the present invention and provided
Any one array base palte.
In order to solve the above-mentioned technical problem, the present invention proposes a kind of display device.The display device includes the present invention and provided
Any one display panel.
Compared with prior art, array base palte of the invention and its manufacture method, display panel and display device, are realized
Following beneficial effect：
The protective layer for the picture element display area for being located at least in array base palte is made before the first insulating barrier is made, to first
When insulating barrier carries out grooving technique, the bottom land of grooving is located at protective layer, and protective layer is as the terminal of grooving, and array substrate plays
Protective effect, then removes the protective layer of bottom land, it is ensured that the unprotected layer influence of picture element display area light penetration, then makes
The second insulating barrier fills up grooving when making the second insulating barrier of array base palte, and the manufacture method reduces pixel in array base palte and shown
Area's film layer number of interfaces, film layer interface fiber-loss is reduced, and light transmittance is high, is shown while the technical process does not destroy pixel
Show the homogeneity of remaining thicknesses of layers after the grooving of region, light passes through the brightness homogeneity in pixel display area after array base palte
It is good.
By referring to the drawings to the detailed description of the exemplary embodiment of the present invention, further feature of the invention and its
Advantage will be made apparent from.
Brief description of the drawings
The accompanying drawing for being combined in the description and constituting a part for specification shows embodiments of the invention, and even
It is used for the principle for explaining the present invention together with its explanation.
Fig. 1 provides the schematic flow sheet of the manufacture method of array base palte for the embodiment of the present invention；
Fig. 2 is a kind of film layer structure schematic diagram in array base palte picture element display area；
Fig. 3 shows for a kind of flow of optional embodiment of the manufacture method of array base palte provided in an embodiment of the present invention
It is intended to；
Fig. 4 is the film layer structure schematic diagram of the array base palte made by manufacture method in Fig. 3；
Fig. 5 shows for the flow of another optional embodiment of manufacture method of array base palte provided in an embodiment of the present invention
It is intended to；
Fig. 6 is the film layer structure schematic diagram of the array base palte made by manufacture method in Fig. 5；
Fig. 7 is the flow of another optional embodiment of the manufacture method of array base palte provided in an embodiment of the present invention
Schematic diagram；
Fig. 8 completes the section of array base palte after step S704 for the manufacture method of array base palte provided in an embodiment of the present invention
Schematic diagram；
Fig. 9 completes the section of array base palte after step S706 for the manufacture method of array base palte provided in an embodiment of the present invention
Schematic diagram；
Another optional embodiment schematic flow sheet of manufacture method for the array base palte that Figure 10 inventive embodiments are provided；
Another film layer structure schematic diagram in Figure 11 array base paltes picture element display area；
Another optional embodiment flow of the manufacture method of Figure 12 array base paltes provided in an embodiment of the present invention is shown
It is intended to；
The film layer structure schematic diagram for the array base palte that Figure 13 is made by Figure 12 manufacture methods；
Another optional embodiment flow of the manufacture method of Figure 14 array base paltes provided in an embodiment of the present invention is shown
It is intended to.
Embodiment
The various exemplary embodiments of the present invention are described in detail now with reference to accompanying drawing.It should be noted that：Unless had in addition
Body illustrates that the part and the positioned opposite of step, numerical expression and numerical value otherwise illustrated in these embodiments does not limit this
The scope of invention.
The description only actually at least one exemplary embodiment is illustrative below, never as to the present invention
And its any limitation applied or used.
It may be not discussed in detail for technology, method and apparatus known to person of ordinary skill in the relevant, but suitable
In the case of, the technology, method and apparatus should be considered as a part for specification.
In shown here and discussion all examples, any occurrence should be construed as merely exemplary, without
It is as limitation.Therefore, other examples of exemplary embodiment can have different values.
It should be noted that：Similar label and letter represents similar terms in following accompanying drawing, therefore, once a certain Xiang Yi
It is defined, then it need not be further discussed in subsequent accompanying drawing in individual accompanying drawing.
The embodiment of the present invention provides a kind of manufacture method of array base palte, and the array base palte includes substrate and on substrate
The first insulating barrier and the second insulating barrier, the flow chart of the manufacture method of the array base palte, as shown in figure 1, including：
S101, make the first insulating barrier before make protective layer, wherein, protective layer is located at least in the pixel of array base palte
Viewing area；
S102, in picture element display area, to the first insulating barrier grooving, wherein, the bottom land of groove is located at protective layer；
S103, removal are located at the protective layer of bottom land；
S104, remove positioned at bottom land protective layer after, make the second insulating barrier.
The protective layer made before the first insulating barrier is made, can only be produced on the picture element display area of array base palte,
Film layer to picture element display area is shielded, and saves material cost, or protective layer is produced on whole array base palte, is made
Region and the size of protective layer need not be considered when making, manufacturing process is simple.
In this embodiment, grooving is carried out by the first insulating barrier in picture element display area array substrate, makes battle array
During the second insulating barrier of row substrate, the second insulating barrier is deposited in groove in the position of groove, fills up grooving, eliminates pixel display area
The film layer interface that the first insulating barrier and the second insulating barrier are constituted in domain, reaches pixel display area film layer interface in reduction array base palte
The purpose of quantity.Meanwhile, before the first insulating barrier is made, protective layer at least is made in the picture element display area of array base palte,
When carrying out grooving technique to the first insulating barrier, the bottom land of grooving is located at protective layer, and then protective layer goes as the terminal of grooving
Except the protective layer of bottom land, the homogeneity of remaining thicknesses of layers after the grooving of picture element display area is not destroyed, and in pixel display area
Domain, the unprotected layer influence of light penetration.
Fiber-loss is reduced at the manufacture method of the array base palte provided using the embodiment, array films bed boundary, light
Penetrance is high, while the technical process does not destroy the homogeneity of remaining thicknesses of layers after the grooving of picture element display area, light is passed through
Brightness homogeneity after array base palte in pixel display area is good.
By taking liquid crystal display panel as an example, the thin film transistor (TFT) for controlling pixel switch is provided with array base palte, is led to
The signal crossed on thin film transistor (TFT) changes to control the steering of liquid crystal molecule with voltage, so as to control each pixel polarised light to go out
Whether penetrate to realize the display function of display panel, a kind of film layer structure of array base palte picture element display area is as shown in Fig. 2 thin
Film transistor is arranged on the substrate 201 of array base palte, is provided between the active layer 202 and substrate 201 of thin film transistor (TFT)
Cushion 203, is provided with gate insulator 205 between active layer 202 and grid 204, source-drain electrode and gate insulator 205 it
Between be provided with interlayer insulating film 206, source electrode 207 and drain electrode 208 are connected by way of via with active layer 202, layer insulation
It is provided with layer 206 on planarization layer 209, planarization layer 209 and is provided with public electrode 210, is provided with public electrode 210
Passivation layer 211, pixel electrode 212 is arranged on passivation layer 211, and is connected by the drain electrode 208 of via and thin film transistor (TFT).
Further, in some optional embodiments, the manufacture method of array base palte provided in an embodiment of the present invention,
First insulating barrier is for the cushion between the active layer and substrate of thin film transistor (TFT), positioned at active layer and thin film transistor (TFT)
Gate insulator between grid and/or the interlayer insulating film between the source-drain electrode and gate insulator of thin film transistor (TFT).
The manufacture method of array base palte provided in an embodiment of the present invention, in picture element display area, to the first insulating barrier grooving
Including a variety of situations, wherein,
The first situation, the first insulating barrier is the cushion 203 between the active layer and substrate of thin film transistor (TFT),
In such case, before cushion 203 is made, protective layer is made on substrate, protective layer is located at least in the picture of array base palte
Plain viewing area, in picture element display area, grooving is carried out to cushion 203, the bottom land of groove is located at protective layer, removes and be located at bottom land
Protective layer, then make the second insulating barrier, the second insulating barrier is gate insulator 205, and one is reduced in picture element display area
Tunic bed boundary, improves light transmittance, while ensure that the homogeneity of remaining thicknesses of layers in grooving technique, panel luminance
Homogeneity is good；
Second of situation, the first insulating barrier is the gate insulator between active layer and the grid of thin film transistor (TFT)
205, in this case, before gate insulator 205 is made, protective layer is made on cushion 203, protective layer is at least
Positioned at the picture element display area of array base palte, in picture element display area, grooving, the bottom land position of groove are carried out to gate insulator 205
In protective layer, the protective layer positioned at bottom land is removed, the second insulating barrier is then made, the second insulating barrier is interlayer insulating film 206,
Picture element display area reduces a tunic bed boundary, improves light transmittance, while ensure that remaining film layer in grooving technique
The homogeneity of thickness, panel luminance homogeneity is good；
The third situation, the first insulating barrier is exhausted for the interlayer between the source-drain electrode and gate insulator of thin film transistor (TFT)
Edge layer 206, in this case, before interlayer insulating film 206 is made, makes protective layer on gate insulator 205, protects
Sheath is located at least in the picture element display area of array base palte, and in picture element display area, grooving, groove are carried out to interlayer insulating film 206
Bottom land be located at protective layer, remove the protective layer positioned at bottom land, then make the second insulating barrier, the second insulating barrier is planarization layer
209, a tunic bed boundary is reduced in picture element display area, light transmittance is improved, remained while ensure that in grooving technique
The homogeneity of remaining thicknesses of layers, panel luminance homogeneity is good；
4th kind of situation, the first insulating barrier is the gate insulator between active layer and the grid of thin film transistor (TFT)
205 and the interlayer insulating film 206 between the source-drain electrode and gate insulator of thin film transistor (TFT), in this case, in system
Make before gate insulator 205 and interlayer insulating film 206, protective layer is made on cushion, protective layer is located at least in array
The picture element display area of substrate, in picture element display area, grooving is carried out to gate insulator 205 and interlayer insulating film 206, groove
Bottom land is located at protective layer, removes the protective layer positioned at bottom land, then makes the second insulating barrier, and the second insulating barrier is planarization layer
209, two membranes bed boundary is reduced in picture element display area, light transmittance is improved, remained while ensure that in grooving technique
The homogeneity of remaining thicknesses of layers, panel luminance homogeneity is good；
5th kind of situation, the first insulating barrier between the active layer and substrate of thin film transistor (TFT) cushion 203 and
Gate insulator 205 between active layer and the grid of thin film transistor (TFT), in this case, makes protection on substrate
Layer, protective layer is located at least in the picture element display area of array base palte, in picture element display area, to cushion 203 and gate insulator
Layer 205 carries out grooving, and the bottom land of groove is located at protective layer, removes the protective layer positioned at bottom land, then make the second insulating barrier, second
Insulating barrier is interlayer insulating film 206, and two membranes bed boundary is reduced in picture element display area, light transmittance is improved, simultaneously
The homogeneity of remaining thicknesses of layers in grooving technique is ensure that, panel luminance homogeneity is good；
6th kind of situation, i.e. the first insulating barrier between the active layer and substrate of thin film transistor (TFT) cushion 203,
Gate insulator 205 between active layer and the grid of thin film transistor (TFT) and the source-drain electrode and grid positioned at thin film transistor (TFT)
Interlayer insulating film 206 between insulating barrier, in this case, making, cushion 203, gate insulator 205 and interlayer are exhausted
Before edge layer 206, protective layer is made on substrate, protective layer is located at least in the picture element display area of array base palte, it is aobvious in pixel
Show region, grooving is carried out to cushion 203, gate insulator 205 and interlayer insulating film 206, the bottom land of groove is located at protective layer, gone
Except the protective layer positioned at bottom land, the second insulating barrier is then made, the second insulating barrier is planarization layer 209, in picture element display area
Trilamellar membrane bed boundary is reduced, light transmittance is improved, while the homogeneity of remaining thicknesses of layers in grooving technique is ensure that,
Panel luminance homogeneity is good.
Further, a kind of optional embodiment of the manufacture method of array base palte provided in an embodiment of the present invention, ginseng
Fig. 3 and Fig. 4 are examined, Fig. 3 is the schematic flow sheet of manufacture method provided in an embodiment of the present invention, and Fig. 4 is by manufacturer's legal system in Fig. 3
The film layer structure schematic diagram for the array base palte made.
Step S301：In the overall protective mulch of the plate face of substrate；
For example, first depositing one layer of ITO on the glass substrate, (Indium Tin Oxides, indium tin oxide semiconductor is transparent
Conducting film) film layer is used as protective layer.
Step S302：Light shield layer is integrally covered in protective layer, the light shield layer of overall covering is performed etching to form light shield layer
Pattern；
Step S303：Cushion, gate insulator and interlayer insulating film are made successively；
Specifically, cushion is made on light shield layer, the active layer of thin film transistor (TFT) is formed on the buffer layer, in active layer
Upper making gate insulator, lays the grid of the first metal layer formation thin film transistor (TFT), finally in grid on gate insulator
Upper formation interlayer insulating film.The part concrete technology can be completed using technique of the prior art, be no longer described in detail herein.
Step S304：After the interlayer insulating film that completes, in picture element display area, to interlayer insulating film, gate insulator
Layer and cushion carry out grooving；
Preferably, via can be made to interlayer insulating film and gate insulator simultaneously in the technique of grooving, to pass through this
Via makes the source-drain electrode of thin film transistor (TFT) be connected with active layer.
Step S305：Remove the protective layer positioned at bottom land；
Step S306：The planarization layer of array base palte is made, wherein, planarization layer filling slot.
Wherein, between planarization layer is made, second metal layer is first laid at the position of above-mentioned via, to make film
The source-drain electrode of transistor；In second metal layer complete planarization layer making after, successively make public electrode, passivation layer with
And pixel electrode.
Fig. 4 is the film layer structure schematic diagram of the array base palte manufactured by flow chart 3.
Matcoveredn 414 is set on the substrate 401 of array base palte, the light shield layer 413 of array base palte be located at protective layer 414 it
On, backlight at the raceway groove formed between the source-drain electrode for blocking thin film transistor (TFT) reduces photo-generated carrier, reduces leakage current, hides
Cushion 403 is provided between the active layer 402 of photosphere 413 and thin film transistor (TFT), is set between active layer 402 and grid 404
There is gate insulator 405, interlayer insulating film 406, source electrode 407 and drain electrode are provided between source-drain electrode and gate insulator 405
408 are connected by way of via with active layer 402, and interlayer insulating film 406, gate insulator 405 and cushion 403 are carried out
After grooving, the protective layer 414 positioned at bottom land is removed, then planarization layer 409, array base are set on interlayer insulating film 406
The filling slot of planarization layer 409 of plate.
The manufacturing method of array base plate of the embodiment, the first overall protective mulch of plate face in substrate, need not during making
Consider region and the size of protective layer making, manufacturing process is simple；After the making of interlayer insulating film is completed, to interlayer insulating film
Made with gate insulator when making the via that source-drain electrode is connected with active layer, while in picture element display area, to interlayer insulating film,
Gate insulator and cushion carry out grooving, protective layer are removed after grooving, so that the backlight light under substrate passes through pixel
During the array base palte of viewing area, the film layer interface of interlayer insulating film, gate insulator and cushion is reduced, light is improved
Penetrance, while ensure that the homogeneity of remaining thicknesses of layers in grooving technique, panel luminance homogeneity is good.
Further, in another embodiment, the difference with above-mentioned embodiment illustrated in fig. 3 is, the embodiment is provided
Array base palte can make protective layer before make light shield layer, the something in common with above-mentioned embodiment illustrated in fig. 3 can be mutual
With reference to difference asks comparison diagram 5 and Fig. 6, Fig. 5 to be the schematic flow sheet of manufacture method provided in an embodiment of the present invention, and Fig. 6 is
The film layer structure schematic diagram of the array base palte manufactured by manufacture method in Fig. 5.
Step S501：Light shield layer is integrally covered in the plate face of substrate, and the overall light shield layer covered is performed etching to be formed
The pattern of light shield layer；
Step S502：Protective layer is made in the position of picture element display area by mould；
Step S503：Cushion, gate insulator and interlayer insulating film are made successively；
Step S504：In picture element display area, grooving is carried out to interlayer insulating film, gate insulator and cushion；
Step S505：Remove the protective layer positioned at bottom land；
Step S506：The planarization layer of array base palte is made, wherein, planarization layer filling slot.
Fig. 6 is the film layer structure schematic diagram of the array base palte manufactured by flow chart 5.
Array base palte includes light shield layer 613, and light shield layer 613 is located on substrate 601, the source and drain for blocking thin film transistor (TFT)
Backlight at the raceway groove formed between pole, reduces photo-generated carrier, reduces leakage current, protective layer (protective layer is removed after grooving) position
Cushion 603, active layer are provided between the active layer 602 of thin film transistor (TFT) on pixel display area, light shield layer 613
Gate insulator 605 is provided between 602 and grid 604, layer insulation is provided between source-drain electrode and gate insulator 605
Layer 606, source electrode 607 and drain electrode 608 are connected by way of via with active layer 602, are provided with interlayer insulating film 606 flat
Smoothization layer 609, in picture element display area, is carried out after grooving to interlayer insulating film 606, gate insulator 605 and cushion 603,
The protective layer positioned at bottom land is removed, planarization layer 609, the filling slot of planarization layer 609 are then made on interlayer insulating film 606.
After the step of forming the pattern of light shield layer, protective layer is made in the position of picture element display area by mould,
Protective layer material consumption is saved, material cost is reduced；In picture element display area, to interlayer insulating film, gate insulator and buffering
Layer carries out grooving, then removes protective layer, and light reduces interlayer insulating film, grid when passing through the array base palte of picture element display area
The film layer interface of pole insulating barrier and cushion, improves light transmittance, while ensure that remaining thicknesses of layers in grooving technique
Homogeneity, panel luminance homogeneity is good.
Further, in another embodiment, the difference with above-mentioned embodiment illustrated in fig. 3 is, in the embodiment
Grooving step is arranged at after the gate insulator that completes, and can mutually be referred to the something in common of above-mentioned Fig. 3 embodiments, different
Part asks comparison diagram 7, wherein, the film layer structure schematic diagram of the array base palte manufactured using the embodiment refers to Fig. 4.
Step S701：In the overall protective mulch of the plate face of substrate；
Step S702：Light shield layer is integrally covered in protective layer, the light shield layer of overall covering is performed etching to form light shield layer
Pattern；
Before cushion is made, in the overall protective mulch of the plate face of substrate, it need not consider that protective layer makes during making
Region and size, manufacturing process is simple.Making light shield layer is used to block backlight at raceway groove, reduces photo-generated carrier, reduction leakage
Stream.
Step S703：Cushion and gate insulator are made successively；
Alternatively, after cushion is made, the source-drain electrode and raceway groove of film transistor device are made, and to film crystal
Raceway groove is doped, and the source-drain electrode of film crystal is doped to form N-type source-drain electrode, gate insulator and grid is then produced
Pole, forms complete film transistor device.
Step S704：In picture element display area, grooving is carried out to gate insulator and cushion；
Alternatively, while the technique for the through hole for snapping into light shield layer in setting second metal layer, dug in pixel display area
Fall gate insulator and cushion, after the completion of the manufacturing process, the schematic cross-section of array base palte is as shown in figure 8, wherein, substrate
Protective mulch 414 on 401, light shield layer 413 is made on protective layer 414, in picture element display area, etches cushion 403
With the formation grooving of gate insulator 405, grid 404 is located on gate insulator 405.
Step S705：Interlayer insulating film is made on gate insulator, wherein, interlayer insulating film is deposited in groove；
Interlayer insulating film is made, grid and drain electrode short circuit is prevented.
Step S706：Remove the interlayer insulating film of deposition in groove；
Alternatively, while perforate being set on source-drain electrode, interlayer insulating film grooving, the technique system are done in pixel display area
After the completion of journey, the schematic cross-section of array base palte on the grid 404 shown in Fig. 8 as shown in figure 9, form interlayer insulating film
406, meanwhile, the interlayer insulating film of deposition is removed in groove.
Step S707：Remove the protective layer positioned at bottom land；
Step S708：The planarization layer of array base palte is made, wherein, planarization layer filling slot.
Planarization layer and filling slot are made, plays planarization, the electric field of following thin film transistor (TFT) formation is shielded
Cover, it is to avoid the pixel capacitance of influence above, after the making for completing planarization layer, make the public electrode of pixel capacitance, make blunt
Change layer, isolation public electrode and pixel electrode formation pixel capacitance, finally make pixel electrode.
In a kind of array base palte manufacture craft, in order that light shield layer is provided simultaneously with heat conduction function, metal material can be used
Light shield layer is prepared, now, second metal layer can be set to snap into the through hole of light shield layer so that light shield layer connects with second metal layer
Connect, and then, on the one hand, make to form isobaric signal between light shield layer and second metal layer, it is to avoid therebetween because of voltage difference
In the presence of and produce coupling, on the other hand, be conducive to the heat of second metal layer being transmitted to light shield layer, realize heat dredge
Dissipate.Based on this, while the technique for the through hole that light shield layer can be snapped into setting second metal layer, make in advance in picture element display area
The grooving of gate insulator and cushion, then deposits interlayer insulating film in groove, and the technique for then doing perforate in source-drain electrode is same
When remove groove in deposition interlayer insulating film, then remove bottom land protective layer, last deposited planarization layer filling slot.The array
The manufacture method of substrate, pixel display area carry out grooving twice, but twice grooving technique all with thin film transistor (TFT) manufacture craft
Middle hole opening technology is carried out simultaneously, simplifies manufacturing process.
Further, in another embodiment, the difference with above-mentioned embodiment illustrated in fig. 7 is, in the embodiment
Light shield layer is made before making protective layer, can mutually be referred to the something in common of above-mentioned embodiment illustrated in fig. 7, difference please be right
Than Figure 10, the film layer structure schematic diagram of the array base palte of embodiment manufacture refers to Fig. 6,
Step S901：Light shield layer is integrally covered in the plate face of substrate；The light shield layer of overall covering is performed etching to form screening
The pattern of photosphere；
Step S902：Formed light shield layer pattern the step of after, by mould picture element display area position system
Make protective layer, after the step of forming the pattern of light shield layer, protective layer made in the position of picture element display area by mould,
Protective layer material consumption is saved, material cost is reduced；
Step S903：Cushion and gate insulator are made successively；
Step S904：After the gate insulator that completes, in picture element display area, gate insulator and cushion are entered
Row grooving；
Step S905：Interlayer insulating film is made on gate insulator, wherein, interlayer insulating film is deposited in groove；
Step S906：Remove the interlayer insulating film of deposition in groove；
Step S907：Remove the protective layer positioned at bottom land；
Step S908：The planarization layer of array base palte is made, wherein, planarization layer filling slot.
Thin film transistor (TFT) is provided with array base palte as the switch of control pixel, to realize the display of liquid crystal display panel
Function.Another film layer structure schematic diagram of array base palte picture element display area, such as Figure 11 shows, in the substrate 901 of array base palte
On be provided with thin film transistor (TFT), cushion 903 is provided between the grid 904 and substrate 901 of thin film transistor (TFT), in grid
Gate insulator 905, the source electrode of active layer 902 and thin film transistor (TFT) are provided between 904 and the active layer 902 of thin film transistor (TFT)
907 are turned on the directly contact of drain electrode 908, and planarization layer 909 is provided with active layer 902, source electrode 907 and drain electrode 908.
Or, in another case, it is provided between the source electrode 907 of active layer 902 and thin film transistor (TFT) and drain electrode 908
Insulating barrier is protected, active layer 902 is with source electrode 907 and drain electrode 908 by setting via to be connected on protection insulating barrier.
Further, in some optional embodiments, array base palte also includes the film crystal being arranged on substrate
Pipe；First insulating barrier is for the cushion between the grid and substrate of thin film transistor (TFT), positioned at grid and thin film transistor (TFT)
Gate insulator between active layer and/or the protection insulating barrier between active layer and the source-drain electrode of thin film transistor (TFT).
The manufacture method of array base palte provided in an embodiment of the present invention, in picture element display area, to the first insulating barrier grooving
Including a variety of situations, wherein,
The first situation, the first insulating barrier is the cushion 903 between the grid and substrate of thin film transistor (TFT), at this
In the situation of kind, before cushion 903 is made, protective layer is made on substrate 901, protective layer is located at least in the picture of array base palte
Plain viewing area, in picture element display area, grooving is carried out to cushion 903, the bottom land of groove is located at protective layer, removes and be located at bottom land
Protective layer, then make the second insulating barrier, the second insulating barrier is gate insulator 905, and one is reduced in picture element display area
Tunic bed boundary, improves light transmittance, while ensure that the homogeneity of remaining thicknesses of layers in grooving technique, panel luminance
Homogeneity is good；
Second of situation, the first insulating barrier is the gate insulator between grid and the active layer of thin film transistor (TFT),
905, in this case, before gate insulator 905 is made, protective layer is made on cushion 903, protective layer is at least
Positioned at the picture element display area of array base palte, in picture element display area, grooving, the bottom land position of groove are carried out to gate insulator 905
In protective layer, the protective layer positioned at bottom land is removed, the second insulating barrier is then made, the second insulating barrier is protection insulating barrier, in picture
Plain viewing area reduces a tunic bed boundary, improves light transmittance, while ensure that remaining film layer is thick in grooving technique
The homogeneity of degree, panel luminance homogeneity is good；
The third situation, only when active layer 902 and thin film transistor (TFT) source electrode 907 and drain electrode 908 between be provided with protection
During insulating barrier, the first insulating barrier is the protection insulating barrier between active layer and the source-drain electrode of thin film transistor (TFT), in this feelings
In condition, before protection insulating barrier is made, protective layer is made on gate insulator 905, protective layer is located at least in array base
The picture element display area of plate, in picture element display area, grooving is carried out to protection insulating barrier, the bottom land of groove is located at protective layer, removed
Positioned at the protective layer of bottom land, the second insulating barrier is then made, the second insulating barrier is planarization layer 909, is subtracted in picture element display area
A tunic bed boundary is lacked, has improved light transmittance, while ensure that the homogeneity of remaining thicknesses of layers in grooving technique, face
Plate brightness homogeneity is good；
4th kind of situation, only when active layer 902 and thin film transistor (TFT) source electrode 907 and drain electrode 908 between be provided with protection
During insulating barrier, the first insulating barrier is for the gate insulator 905 between grid and the active layer of thin film transistor (TFT) and positioned at having
Protection insulating barrier between active layer and the source-drain electrode of thin film transistor (TFT), in this case, is making gate insulator 905 and is protecting
Protect before insulating barrier, protective layer made on cushion 903, protective layer is located at least in the picture element display area of array base palte,
In picture element display area, grooving is carried out to gate insulator 905 and protection insulating barrier, the bottom land of groove is located at protective layer, removes position
In the protective layer of bottom land, the second insulating barrier is then made, the second insulating barrier is planarization layer 909, is reduced in picture element display area
Two membranes bed boundarys, improve light transmittance, while ensure that the homogeneity of remaining thicknesses of layers in grooving technique, panel
Brightness homogeneity is good；
5th kind of situation, the first insulating barrier is the cushion 903 between the grid and substrate of thin film transistor (TFT) and position
Gate insulator 905 between grid and the active layer of thin film transistor (TFT), in this case, makes protection on substrate
Layer, protective layer is located at least in the picture element display area of array base palte, and cushion 903 and gate insulator 905 are then made successively,
In picture element display area, grooving is carried out to cushion 903 and gate insulator 905, the bottom land of groove is located at protective layer, and removal is located at
The protective layer of bottom land, then makes the second insulating barrier, and the second insulating barrier is protection insulating barrier, and two are reduced in picture element display area
Tunic bed boundary, improves light transmittance, while ensure that the homogeneity of remaining thicknesses of layers in grooving technique, panel luminance
Homogeneity is good；
6th kind of situation, only when active layer 902 and thin film transistor (TFT) source electrode 907 and drain electrode 908 between be provided with protection
During insulating barrier, the first insulating barrier is for the cushion 903 between the grid and substrate of thin film transistor (TFT), positioned at grid and film
Gate insulator 905 between the active layer of transistor and the protection between active layer and the source-drain electrode of thin film transistor (TFT) are exhausted
Edge layer, in this case, is making between cushion 903, gate insulator 905 and protection insulating barrier, is being made on substrate
Protective layer, protective layer is located at least in the picture element display area of array base palte, in picture element display area, exhausted to cushion 903, grid
Edge layer 905 and protection insulating barrier carry out grooving, and the bottom land of groove is located at protective layer, removes the protective layer positioned at bottom land, then make
Second insulating barrier, the second insulating barrier is planarization layer 909, and trilamellar membrane bed boundary is reduced in picture element display area, light is improved
Line penetrance, while ensure that the homogeneity of remaining thicknesses of layers in grooving technique, panel luminance homogeneity is good.
Further, another optional embodiment of the manufacture method of array base palte provided in an embodiment of the present invention,
With reference to Figure 12 and Figure 13, the schematic flow sheet for the manufacturing method of array base plate that Figure 12 provides for the present embodiment, Figure 13 is by flow
The film layer schematic cross-section for the array base palte that Figure 12 makes,
Step S1101：In the overall protective mulch of the plate face of substrate,
Region and the size of protective layer making need not be considered during making, manufacturing process is simple；
Step S1102：Cushion and gate insulator are made successively；
Wherein, when being provided with protection insulating barrier between the source electrode 907 of active layer 902 and thin film transistor (TFT) and drain electrode 908,
In step S1102, make after gate insulator, in addition to make protection insulating barrier；
Step S1103：In picture element display area, grooving is carried out to gate insulator and cushion；
When being provided with protection insulating barrier between the source electrode 907 of active layer 902 and thin film transistor (TFT) and drain electrode 908, at this
In step S1103, in picture element display area, grooving is carried out to protection insulating barrier, gate insulator and cushion；
Step S1104：Remove the protective layer positioned at bottom land；
Step S1105：The planarization layer of array base palte is made, wherein, planarization layer filling slot.
Figure 13 is the film layer schematic cross-section of the array base palte manufactured by flow chart 12.Array base palte substrate 1201 it
On be provided with thin film transistor (TFT), cushion 1203 is provided between the grid 1204 and substrate 1201 of thin film transistor (TFT), wherein thin
Film transistor grid 1204 is located at trench bottom and serves the effect to back of the body raceway groove shading, in grid 1204 and thin film transistor (TFT)
Gate insulator 1205 is provided between active layer 1202, planarization layer 1209 is formed before pixel electrode is made.In pixel
Viewing area, carries out after grooving to gate insulator 1205 and cushion 1203, the protective layer 1214 positioned at bottom land is removed, in battle array
When making planarization layer 1209 on row substrate, the filling slot of planarization layer 1209.
Further, in another embodiment, the difference with above-mentioned embodiment illustrated in fig. 12 is, in the embodiment
Grooving step is arranged at after the gate insulator that completes, and can mutually be joined with the something in common of above-mentioned embodiment illustrated in fig. 12
Examine, difference asks comparison diagram 14, the film layer structure figure of the array base palte manufactured using the embodiment may be referred to Figure 13.
Step S1401：In the overall protective mulch of the plate face of substrate,
Region and the size of protective layer making need not be considered during making, manufacturing process is simple；
Step S1402：Cushion and gate insulator are made successively；
Step S1403：After the gate insulator that completes, in picture element display area, to gate insulator and cushion
Carry out grooving；
When being provided with protection insulating barrier between the source electrode and drain electrode of active layer and thin film transistor (TFT), what the present embodiment was provided
The manufacture method of array base palte also includes step S1404：Protection insulating barrier is made on gate insulator, wherein, protection insulation
Layer is deposited in groove；
Also include step S1405 after making protection insulating barrier step S1404：Remove the protection insulating barrier of deposition in groove；
Step S1406：Remove the protective layer positioned at bottom land；
Step S1407：The planarization layer of array base palte is made, wherein, planarization layer filling slot.
Grooving technique in the manufacture method can simultaneously be carried out with hole opening technology in thin film transistor (TFT) manufacture craft, simplify work
Skill processing procedure.
Further, in the manufacture method of the array base palte described in any of the above-described embodiment, protective layer is metal film, institute
Metal film is stated for indium tin oxide transparent conductive semiconductor film.
Protective layer is indium tin oxide transparent conductive semiconductor film, and grooving is being carried out to the first insulating barrier using etching technics
During processing, etch after the first insulating barrier, because the speed of etching indium tin oxide transparent conductive semiconductor film is obvious
Reduction, this layer can play a protective role to the film layer below protective layer, effectively prevent as the terminal of the first insulating barrier of etching
The homogeneity of remaining thicknesses of layers deteriorates after etching.
Further, it is specially in some optional embodiments, the step of to the first insulating barrier grooving：Using dry etching
Mode to the first insulating barrier grooving；
Further, in some optional embodiments, the step of removing positioned at the protective layer of bottom land is specially：Using
The mode of wet etching removes the protective layer of bottom land.
Further, the embodiment of the present invention provides a kind of array base palte, and the array base palte uses any of the above-described embodiment institute
The manufacturing method of array base plate stated is fabricated by.
Array base palte provided in an embodiment of the present invention, in picture element display area, film layer number of interfaces is few, and fiber-loss is few,
Therefore light penetration is high, while increasing the manufacture method of protective layer, it is ensured that the homogeneity at array base palte film layer interface, array
Substrate pixel viewing area brightness homogeneity is good.
Further, the embodiment of the present invention provides a kind of panel, and the panel includes the array base palte described in above-described embodiment.
Panel provided in an embodiment of the present invention, picture element display area light penetration is high and brightness homogeneity is good.
Further, the embodiment of the present invention provides a kind of display device, and the display device is included described in above-described embodiment
Panel.Display device provided in an embodiment of the present invention, panel pixel viewing area light penetration is high and brightness homogeneity is good.
By above-described embodiment, array base palte of the invention and its manufacture method, display panel and display device are real
Following beneficial effect is showed：
The protective layer for the picture element display area for being located at least in array base palte is made before the first insulating barrier is made, to first
When insulating barrier carries out grooving technique, the bottom land of grooving is located at protective layer, and protective layer is as the terminal of grooving, and array substrate plays
Protective effect, then removes the protective layer of bottom land, in picture element display area, the unprotected layer influence of light penetration, then makes
The second insulating barrier fills up grooving when making the second insulating barrier of array base palte, and the manufacture method reduces pixel in array base palte and shown
Area's film layer number of interfaces, film layer interface fiber-loss is reduced, and light transmittance is high, is shown while the technical process does not destroy pixel
Show the homogeneity of remaining thicknesses of layers after the grooving of region, light passes through the brightness homogeneity in pixel display area after array base palte
It is good.
Although some specific embodiments of the present invention are described in detail by example, the skill of this area
Art personnel are it should be understood that example above is merely to illustrate, the scope being not intended to be limiting of the invention.The skill of this area
Art personnel to above example it should be understood that can modify without departing from the scope and spirit of the present invention.This hair
Bright scope is defined by the following claims.
Claims (15)
1. a kind of manufacture method of array base palte, it is characterised in that
The array base palte includes substrate and the first insulating barrier and the second insulating barrier on the substrate,
Methods described includes：
Before first insulating barrier is made, protective layer is made, wherein, the protective layer is located at least in the array base palte
Picture element display area；
In the picture element display area, to the first insulating barrier grooving, wherein, the bottom land of the groove is located at the protective layer；
Remove the protective layer positioned at the bottom land；
Removing after the protective layer of the bottom land, making second insulating barrier.
2. the manufacture method of array base palte according to claim 1, it is characterised in that
The array base palte also includes the thin film transistor (TFT) being arranged on the substrate；
First insulating barrier is for the cushion between the active layer and the substrate of the thin film transistor (TFT), positioned at described
Gate insulator between the grid of active layer and the thin film transistor (TFT) and/or the source-drain electrode positioned at the thin film transistor (TFT) with
Interlayer insulating film between the gate insulator.
3. the manufacture method of array base palte according to claim 2, it is characterised in that
The array base palte also includes light shield layer；
The step of making the protective layer be specially：Before the cushion is made, integrally covered in the plate face of the substrate
The protective layer；
After the step of covering the protective layer on the substrate, before the step of making the cushion of the array base palte,
Methods described also includes：The light shield layer is integrally covered in the protective layer；The light shield layer of overall covering is performed etching
Form the pattern of the light shield layer.
4. the manufacture method of array base palte according to claim 2, it is characterised in that
The array base palte also includes light shield layer；
Before the step of making the protective layer, methods described also includes：The screening is integrally covered in the plate face of the substrate
Photosphere；The pattern to form the light shield layer is performed etching to the overall light shield layer covered；
The step of making the protective layer be specially：After the step of forming the pattern of the light shield layer, by mould in institute
The position for stating picture element display area makes the protective layer.
5. the manufacture method of the array base palte according to any one of claim 3 or 4, it is characterised in that
Make the light shield layer and the step of the protective layer after, the step of to the first insulating barrier grooving before, institute
Stating method also includes：The cushion, the gate insulator and the interlayer insulating film are made successively；
The step of to the first insulating barrier grooving is specially：It is aobvious in the pixel after the interlayer insulating film that completes
Show region, grooving is carried out to the interlayer insulating film, the gate insulator and the cushion；
The step of making second insulating barrier be specially：The planarization layer of the array base palte is made, wherein, the planarization
The layer filling groove.
6. the manufacture method of the array base palte according to any one of claim 3 or 4, it is characterised in that
Make the light shield layer and the step of the protective layer after, the step of to the first insulating barrier grooving before, institute
Stating method also includes：The cushion and the gate insulator are made successively；
The step of to the first insulating barrier grooving is specially：It is aobvious in the pixel after the gate insulator that completes
Show region, grooving is carried out to the gate insulator and the cushion；
After the step of to the first insulating barrier grooving, remove before the protective layer of the bottom land, methods described is also
Including：The interlayer insulating film is made on the gate insulator, wherein, the interlayer insulating film is deposited in the groove；
Remove the interlayer insulating film of deposition in the groove；
The step of making second insulating barrier be specially：The planarization layer of the array base palte is made, wherein, the planarization
The layer filling groove.
7. the manufacture method of array base palte according to claim 1, it is characterised in that
The array base palte also includes the thin film transistor (TFT) being arranged on the substrate；
First insulating barrier is for the cushion between the grid and the substrate of the thin film transistor (TFT), positioned at the grid
Gate insulator between the active layer of pole and the thin film transistor (TFT) and/or positioned at the active layer and the thin film transistor (TFT)
Source-drain electrode between protection insulating barrier.
8. the manufacture method of array base palte according to claim 7, it is characterised in that
The step of making the protective layer be specially：Before the cushion is made, integrally covered in the plate face of the substrate
The protective layer；
After the step of making the protective layer, the step of to the first insulating barrier grooving before, methods described also includes：
The cushion, the gate insulator and the protection insulating barrier are made successively；
The step of to the first insulating barrier grooving is specially：It is aobvious in the pixel after the protection insulating barrier that completes
Show region, grooving is carried out to the protection insulating barrier, the gate insulator and the cushion；
The step of making second insulating barrier be specially：The planarization layer of the array base palte is made, wherein, the planarization
The layer filling groove.
9. the manufacture method of array base palte according to claim 7, it is characterised in that
After the step of making the protective layer, the step of to the first insulating barrier grooving before, methods described also includes：
The cushion and the gate insulator are made successively；
The step of to the first insulating barrier grooving is specially：It is aobvious in the pixel after the gate insulator that completes
Show region, grooving is carried out to the gate insulator and the cushion；
After the step of to the first insulating barrier grooving, remove before the protective layer of the bottom land, methods described is also
Including：The protection insulating barrier is made on the gate insulator, wherein, the protection insulating layer deposition is in the groove；
Remove the protection insulating barrier of deposition in the groove；
The step of making second insulating barrier be specially：The planarization layer of the array base palte is made, wherein, the planarization
The layer filling groove.
10. the manufacture method of array base palte according to claim 1, it is characterised in that the protective layer is metal film.
11. the manufacture method of array base palte according to claim 10, it is characterised in that
The step of to the first insulating barrier grooving is specially：First insulating barrier grooving described in by the way of the dry etching；
Remove positioned at the bottom land protective layer the step of be specially：The protective layer of the bottom land is removed by the way of wet etching.
12. the manufacture method of array base palte according to claim 10, it is characterised in that the metal film aoxidizes for indium tin
Thing transparent conductive semiconductor film.
13. a kind of array base palte, it is characterised in that using the manufacture of the array base palte any one of claim 1 to 12
Method is made.
14. a kind of display panel, it is characterised in that including the array base palte described in claim 13.
15. a kind of display device, it is characterised in that including the display panel described in claim 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710380566.5A CN106972033B (en) | 2017-05-25 | 2017-05-25 | Array substrate, manufacturing method thereof, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710380566.5A CN106972033B (en) | 2017-05-25 | 2017-05-25 | Array substrate, manufacturing method thereof, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106972033A true CN106972033A (en) | 2017-07-21 |
| CN106972033B CN106972033B (en) | 2021-02-19 |
Family
ID=59327209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710380566.5A Active CN106972033B (en) | 2017-05-25 | 2017-05-25 | Array substrate, manufacturing method thereof, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106972033B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107910355A (en) * | 2017-11-27 | 2018-04-13 | 信利（惠州）智能显示有限公司 | Array base palte and preparation method thereof and organic electroluminescence display device and method of manufacturing same |
| CN109659319A (en) * | 2018-12-10 | 2019-04-19 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN109711229A (en) * | 2017-10-26 | 2019-05-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of fingerprint recognition chip and its manufacturing method and electronic device |
| CN112634757A (en) * | 2020-12-18 | 2021-04-09 | 合肥维信诺科技有限公司 | Preparation method of display panel |
| CN113113431A (en) * | 2021-04-13 | 2021-07-13 | 合肥鑫晟光电科技有限公司 | Array substrate, preparation method thereof and display device |
| CN114300488A (en) * | 2021-12-30 | 2022-04-08 | 厦门天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1641450A (en) * | 2004-01-17 | 2005-07-20 | 统宝光电股份有限公司 | Liquid crystal display device, and its manufacturing method anbd transistor array substrate and manufacturing method |
| CN104716091A (en) * | 2013-12-13 | 2015-06-17 | 昆山国显光电有限公司 | Array substrate preparation method, array substrate, and organic light-emitting display device |
| US20170005154A1 (en) * | 2015-07-03 | 2017-01-05 | Samsung Display Co., Ltd. | Transparent display apparatus |
| CN206057763U (en) * | 2016-08-31 | 2017-03-29 | 厦门天马微电子有限公司 | A kind of array base palte, display floater and display device |
-
2017
- 2017-05-25 CN CN201710380566.5A patent/CN106972033B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1641450A (en) * | 2004-01-17 | 2005-07-20 | 统宝光电股份有限公司 | Liquid crystal display device, and its manufacturing method anbd transistor array substrate and manufacturing method |
| CN104716091A (en) * | 2013-12-13 | 2015-06-17 | 昆山国显光电有限公司 | Array substrate preparation method, array substrate, and organic light-emitting display device |
| US20170005154A1 (en) * | 2015-07-03 | 2017-01-05 | Samsung Display Co., Ltd. | Transparent display apparatus |
| CN206057763U (en) * | 2016-08-31 | 2017-03-29 | 厦门天马微电子有限公司 | A kind of array base palte, display floater and display device |
Non-Patent Citations (1)
| Title |
|---|
| 王文博等: "LCoS平板微显示驱动技术研究 ", 《半导体光电》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109711229A (en) * | 2017-10-26 | 2019-05-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of fingerprint recognition chip and its manufacturing method and electronic device |
| CN109711229B (en) * | 2017-10-26 | 2021-12-21 | 中芯国际集成电路制造(上海)有限公司 | Fingerprint identification chip, manufacturing method thereof and electronic device |
| CN107910355A (en) * | 2017-11-27 | 2018-04-13 | 信利（惠州）智能显示有限公司 | Array base palte and preparation method thereof and organic electroluminescence display device and method of manufacturing same |
| CN109659319A (en) * | 2018-12-10 | 2019-04-19 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN109659319B (en) * | 2018-12-10 | 2021-01-01 | 武汉华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
| CN112634757A (en) * | 2020-12-18 | 2021-04-09 | 合肥维信诺科技有限公司 | Preparation method of display panel |
| CN113113431A (en) * | 2021-04-13 | 2021-07-13 | 合肥鑫晟光电科技有限公司 | Array substrate, preparation method thereof and display device |
| CN113113431B (en) * | 2021-04-13 | 2023-08-29 | 合肥鑫晟光电科技有限公司 | Array substrate, preparation method thereof and display device |
| CN114300488A (en) * | 2021-12-30 | 2022-04-08 | 厦门天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106972033B (en) | 2021-02-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106972033A (en) | Array base palte and its manufacture method, display panel and display device | |
| CN104571715B (en) | Array base palte and preparation method thereof and driving method, display device | |
| CN101393897B (en) | Method for manufacturing liquid crystal display device | |
| CN107293593B (en) | A kind of display panel and display device | |
| CN103293811B (en) | A kind of array base palte and preparation method thereof, display unit | |
| CN103354218B (en) | Array base palte and preparation method thereof and display device | |
| CN104269414B (en) | A kind of array base palte and preparation method thereof, display device | |
| TWI327239B (en) | Pixel and liquid crystal display and method for manufacturing the same | |
| CN104460163B (en) | A kind of array base palte and preparation method thereof and display device | |
| CN104218094B (en) | A kind of thin film transistor (TFT), display base plate and display device | |
| CN103149760A (en) | Thin film transistor array substrate, manufacturing method and display device | |
| CN104076551B (en) | A kind of color membrane substrates and preparation method thereof, display floater, display device | |
| CN107506076B (en) | A kind of touch display substrate, manufacturing method and display device | |
| CN105652541A (en) | Manufacturing method of array substrate and liquid crystal display panel | |
| CN104701302A (en) | Array substrate and manufacture method thereof and display device | |
| CN105655348A (en) | Array substrate and manufacturing method thereof, display panel and display device | |
| CN103927045A (en) | Touch substrate manufacturing method | |
| CN102081257A (en) | Liquid crystal grating and stereo display device | |
| CN104090401A (en) | Array substrate, preparation method thereof and display device | |
| JP2016525223A (en) | Array substrate, display device, and method of manufacturing array substrate | |
| CN105912167A (en) | Touch control module and manufacture method thereof, display panel and display device | |
| CN105158955A (en) | Display panel and manufacturing method thereof | |
| CN100590854C (en) | Pixel structure and its making method | |
| CN110178207A (en) | The manufacturing method of active-matrix substrate, liquid crystal display panel and liquid crystal display panel | |
| CN103278989A (en) | Display panel, manufacturing method thereof and liquid crystal display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |