CN114300488A

CN114300488A - Display panel, manufacturing method thereof and display device

Info

Publication number: CN114300488A
Application number: CN202111652370.XA
Authority: CN
Inventors: 何艳林; 陈宝玲; 周莉梅; 凌安恺; 沈柏平
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2021-12-30
Filing date: 2021-12-30
Publication date: 2022-04-08
Anticipated expiration: 2041-12-30
Also published as: CN114300488B

Abstract

The invention discloses a display panel, a manufacturing method thereof and a display device, belonging to the technical field of display, wherein the display panel comprises a display area and a non-display area arranged around the display area; the display panel includes: the thin film transistor array structure comprises a first substrate, and a thin film transistor array layer, a planarization layer, a first insulating layer and a third metal layer which are arranged on the first substrate, wherein the thin film transistor array layer at least comprises a first metal layer and a second metal layer which are mutually insulated; the first insulating layer is positioned on one side of the planarization layer, which is far away from the first substrate, and the third metal layer is positioned on one side of the first insulating layer, which is far away from the first substrate; the non-display region includes a trench region, and the trench region does not include the planarization layer. The manufacturing method of the display panel is used for manufacturing the display panel. The display device comprises the display panel. The invention is beneficial to reducing the risk of short circuit of the circuit in the non-display area, reducing the probability of occurrence of quality safety hidden trouble and improving the yield of the display panel product.

Description

Display panel, manufacturing method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a display panel, a manufacturing method of the display panel and a display device.

Background

At present, Display technologies mainly include two major categories, namely Organic Light-Emitting Diode (OLED) technology and Liquid Crystal Display (LCD) technology. The LCD display is a new display device that has been rapidly developed recently and occupies the mainstream display application market, has many advantages of light weight, high resolution, fast response speed, low power consumption, good display quality, and the like, and is widely applied to the common display device application fields such as televisions, electronic instruments, mobile phones, computers, and the like. An organic light emitting diode display, which is a current type light emitting device, is increasingly used in the field of high performance display due to its characteristics of self-luminescence, fast response, wide viewing angle, and the like.

After the traditional display panel is manufactured with a relatively uneven transistor array layer, in order to ensure the flatness of subsequent films, a relatively thick planarization layer is often required to be coated on the relatively uneven transistor array layer, but in a non-display area of the display panel, a flip chip film area is required to be reserved on the planarization layer.

In the prior art, because the planarization layer is thick, a residual conductive structure after exposure often appears in a reserved flip-chip film area of the planarization layer, and the residual conductive structure can easily cause a circuit short circuit or other quality safety hazards of a non-display area, so that the quality and production yield of the display panel are reduced, and the cost is increased.

Therefore, it is an urgent need to solve the technical problem of providing a display panel, a method for manufacturing the same, and a display device, which can solve the problem of conductive structure residue and is beneficial to improving the yield of products.

Disclosure of Invention

In view of the above, the present invention provides a display panel, a manufacturing method thereof and a display device, so as to solve the problems that in the prior art, a short circuit or other quality safety hazards of a non-display area are easily caused, and the quality and the production yield of the display panel are reduced.

The invention discloses a display panel, comprising: a display area and a non-display area disposed around the display area; the display panel includes: a first substrate; the thin film transistor array layer is positioned on one side of the first substrate; the thin film transistor array layer at least comprises a first metal layer and a second metal layer which are insulated from each other; the planarization layer is positioned on one side, far away from the first substrate, of the thin film transistor array layer; the first insulating layer is positioned on one side, far away from the first substrate, of the planarization layer; the third metal layer is positioned on one side, far away from the first substrate, of the first insulating layer; the non-display region includes a trench region, and the trench region does not include the planarization layer.

Based on the same inventive concept, the invention also discloses a manufacturing method of the display panel, which is used for manufacturing the display panel; the manufacturing method comprises the following steps: providing a first substrate; manufacturing a thin film transistor array layer on one side of a first substrate, wherein the thin film transistor array layer at least comprises a first metal layer and a second metal layer which are insulated from each other; manufacturing a planarization layer on one side of the thin film transistor array layer, which is far away from the first substrate; etching the planarization layer in the non-display area to form a groove area, so that the groove area does not comprise the planarization layer; manufacturing a first insulating layer on one side of the planarization layer, which is far away from the first substrate, so that the first insulating layer is positioned in the display area and the non-display area; and manufacturing a third metal layer on one side of the first insulating layer far away from the first substrate.

Based on the same inventive concept, the invention also discloses a display device, which comprises the display panel.

Compared with the prior art, the display panel, the manufacturing method thereof and the display device provided by the invention at least realize the following beneficial effects:

in the display panel of the invention, the side of the planarization layer away from the first substrate further comprises a first insulating layer, and the side of the first insulating layer away from the first substrate is provided with a third metal layer. The non-display area comprises a groove digging area, the groove digging area does not comprise a planarization layer, namely the groove digging area of the non-display area can be understood as that after the planarization structure of the whole layer is manufactured, etching treatment is carried out at the corresponding position of the groove digging area to form the groove digging area without the planarization layer, and then the subsequent film layer of the planarization layer is manufactured. The first insulating layer is arranged between the third metal layer and the planarization layer, so that after the non-display area of the display panel forms the groove-digging area, the groove-digging area is equivalent to heightening the film layer of the groove-digging area through the arrangement of the first insulating layer, and after the third metal layer is manufactured subsequently, because the film layer of the groove-digging area is heightened by the first insulating layer, the original section difference of the planarization layer is reduced, and further, the conductive structure possibly remained in the groove-digging area is enabled to be closer to an exposure light source, if the conductive structure possibly remained in the groove-digging area close to the side wall area of the planarization layer during manufacturing of the third metal layer is enabled to be closer to the exposure light source, so that the remained conductive structure is more easily exposed, the risk of circuit short circuit in the non-display area is facilitated to be reduced, the probability of occurrence of quality safety hazards is facilitated to be reduced, and the product yield of the display panel can be improved.

Of course, it is not necessary for any product in which the present invention is practiced to specifically achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention;

FIG. 2 is a schematic sectional view taken along line A-A' of FIG. 1;

FIG. 3 is a schematic cross-sectional view of a display panel in the vicinity of a trench area in the related art;

FIG. 4 is a schematic view of a film layer structure of the display panel in the non-display area according to the present embodiment;

FIG. 5 is a schematic view of another cross-sectional structure taken along line A-A' of FIG. 1;

FIG. 6 is a schematic view of another cross-sectional structure taken along line A-A' of FIG. 1;

FIG. 7 is a schematic diagram of another planar structure of a display panel according to an embodiment of the present invention;

FIG. 8 is a schematic view of an alternative cross-sectional configuration taken along line A-A' of FIG. 1;

FIG. 9 is a schematic view of an alternative cross-sectional configuration taken along line A-A' of FIG. 1;

FIG. 10 is a schematic view of an alternative cross-sectional configuration taken along line A-A' of FIG. 1;

FIG. 11 is a schematic view of an alternative cross-sectional configuration taken along line A-A' of FIG. 1;

FIG. 12 is a schematic view of an alternative cross-sectional configuration taken along line A-A' of FIG. 1;

FIG. 13 is a schematic view of an alternative cross-sectional configuration taken along line A-A' of FIG. 1;

FIG. 14 is a schematic view of an alternative cross-sectional configuration taken along line A-A' of FIG. 1;

fig. 15 is a schematic plan view of another display panel according to an embodiment of the present invention;

FIG. 16 is a schematic sectional view taken along line B-B' of FIG. 15;

FIG. 17 is a block diagram of a method for fabricating a display panel according to an embodiment of the present invention;

FIG. 18 is a schematic structural view of the first substrate provided in FIG. 17;

fig. 19 is a schematic diagram of the structure of fig. 17 after the thin film transistor array layer is fabricated;

FIG. 20 is a schematic diagram of the structure of FIG. 17 after a planarization layer has been formed;

FIG. 21 is a schematic view of the structure of FIG. 17 after forming a recessed area in the non-display area;

FIG. 22 is a schematic view of the structure of FIG. 17 after fabrication of the first insulating layer;

FIG. 23 is a schematic diagram of the structure of FIG. 17 after a third metal layer has been formed;

FIG. 24 is a block diagram of another flowchart of a method for fabricating a display panel according to an embodiment of the present invention;

FIG. 25 is a schematic view of the structure of FIG. 24 after etching the first insulating layer;

fig. 26 is another flowchart of a method for manufacturing a display panel according to an embodiment of the invention;

FIG. 27 is a schematic diagram of the structure of FIG. 26 after the third metal layer has been formed;

fig. 28 is another flowchart of a method for manufacturing a display panel according to an embodiment of the invention;

FIG. 29 is a schematic view of the structure of FIG. 28 after exposure of the third metal layer;

FIG. 30 is a block diagram of another process flow for fabricating a display panel according to an embodiment of the present invention;

FIG. 31 is a schematic view of the structure of FIG. 30 after forming a recessed area in the non-display area;

FIG. 32 is a schematic view of the structure of FIG. 30 after fabrication of a first insulating layer;

FIG. 33 is a schematic diagram of the structure of FIG. 30 after the third metal layer has been formed;

fig. 34 is another flowchart of a method for manufacturing a display panel according to an embodiment of the present invention;

FIG. 35 is a schematic view of the structure of FIG. 34 after fabrication of the first sub-layer;

FIG. 36 is a schematic view of the structure of FIG. 34 after etching of the first sub-layer;

FIG. 37 is a schematic view of the structure of FIG. 34 after fabrication of the second sub-layer;

FIG. 38 is a schematic view of the structure of FIG. 34 after etching of the second sub-layer;

FIG. 39 is a schematic view of the structure of FIG. 34 after fabrication of the first insulating layer;

FIG. 40 is a schematic diagram of the structure of FIG. 34 after the third metal layer has been formed;

FIG. 41 is a block diagram illustrating another process of a method for fabricating a display panel according to an embodiment of the present invention;

fig. 42 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Referring to fig. 1 and fig. 2 in combination, fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention, fig. 2 is a schematic cross-sectional view taken along a direction a-a' in fig. 1, and the display panel 000 according to the embodiment includes: a display area AA and a non-display area NA disposed around the display area AA;

the display panel 000 includes:

a first substrate 10;

a thin film transistor array layer 20, the thin film transistor array layer 20 being located at one side of the first substrate 10; the thin film transistor array layer 20 includes at least a first metal layer 201 and a second metal layer 202 insulated from each other;

a planarization layer 30, wherein the planarization layer 30 is positioned on one side of the thin film transistor array layer 20 away from the first substrate 10;

a first insulating layer 40, wherein the first insulating layer 40 is positioned on one side of the planarization layer 30 far away from the first substrate 10;

a third metal layer 50, wherein the third metal layer 50 is positioned on one side of the first insulating layer 40 far away from the first substrate 10;

the non-display area NA includes the grooved area NA1, and the grooved area NA1 does not include the planarization layer 30.

Specifically, the display panel 000 provided in this embodiment at least includes a display area AA and a non-display area NA disposed around the display area AA, where the display area AA may include a plurality of sub-pixels for implementing a display image, and the non-display area NA is configured to have some frame structures, peripheral signal lines, or bonding pads, etc. for transmitting an external driving signal to the sub-pixels within the display area AA of the display panel 000. As shown in fig. 2, the film structure of the display panel 000 may at least include a first substrate 10, and optionally, when the display panel 000 of this embodiment is a liquid crystal display panel, the first substrate 10 may be understood as a substrate structure on one side of the array substrate, and at this time, the display panel 000 may further include a second substrate (not shown), and the second substrate may be understood as another substrate structure on one side of the color film substrate. Alternatively, the display panel 000 may also be another type of display panel, such as an organic light emitting diode display panel or a submillimeter light emitting diode (Mini LED) or a Micro LED (Micro LED) display panel, in which case the first substrate 10 may be understood as a carrier substrate for disposing other film structures of the display panel. In this embodiment, a thin film transistor array layer 20 is disposed on one side of the first substrate 10, optionally, the thin film transistor array layer 20 may be understood as a plurality of film layers on which thin film transistors are disposed, the thin film transistor array layer 20 at least includes a first metal layer 201 and a second metal layer 202 that are insulated from each other, the first metal layer 201 and the second metal layer 202 may be used to fabricate a gate and a source/drain of the thin film transistor, and may also be used to fabricate signal lines (such as scan lines and data lines) included in the display panel 000, which are not described in detail in this embodiment, and may be understood with reference to a metal film layer structure of the display panel in the related art specifically. Since the surface of the side of the thin film transistor array layer 20 away from the first substrate 10 may be not flat due to the etching pattern of the film layer related to the thin film transistor array layer 20 after the thin film transistor array layer 20 is manufactured with a plurality of structures such as thin film transistors and signal lines, the planarization layer 30 is further disposed on the side of the thin film transistor array layer 20 away from the first substrate 10 in this embodiment, and the planarization layer 30 serves to protect the structures such as transistors and signal lines of the thin film transistor array layer 20, and also serves as a flat surface, which is beneficial to manufacturing the subsequent film layer of the planarization layer 30, and ensures that the subsequent film layer has higher flatness.

In the embodiment, a side of the planarization layer 30, which is away from the first substrate 10, further includes a first insulating layer 40, optionally, along a direction Z perpendicular to a plane of the first substrate 10, a thickness of the first insulating layer 40 may be smaller than a thickness of the planarization layer 30, and a third metal layer 50 is further disposed on a side of the first insulating layer 40, which is away from the first substrate 10, that is, in the display panel 000 of the embodiment, after the planarization layer 30 is manufactured, a first insulating layer 40 is first manufactured, and then other conductive layers are disposed, for example, the third metal layer 50, and the third metal layer 50 may be used for manufacturing structures such as a touch signal line or a capacitor conductive layer of the display panel, and in the embodiment, a conductive structure specifically included in the third metal layer 50 is not specifically limited, and only the third metal layer 50 needs to be disposed on a side of the first insulating layer 40, which is away from the first substrate 10. The non-display area NA of the embodiment includes the trench area NA1, and the trench area NA1 does not include the planarization layer 30, that is, the trench area NA1 of the non-display area NA is understood to be that after the planarization structure of the whole layer is manufactured, the etching process is performed at the position corresponding to the trench area NA1 to form the trench area NA1 that does not include the planarization layer 30, and then the subsequent film layers of the planarization layer 30 are manufactured, such as the first insulating layer 40 and the third metal layer 50 are manufactured. The slotted area NA1 of the non-display area NA may be understood as a binding area where the display panel 000 is subsequently used for binding a driver chip or a flexible circuit board, or may also be understood as an area where a fan-out lead is disposed, where the fan-out lead is disposed in a range where the fan-out lead transmits a signal on the bound driver chip to the display area AA, so as to achieve a display effect of the display panel.

In the embodiment, the first insulating layer 40 is further included between the third metal layer 50 and the planarization layer 30, so that after the non-display area NA of the display panel 000 forms the trench area NA1, the trench area NA1 is equivalent to a film layer that is higher than the trench area NA1 by the arrangement of the first insulating layer 40, and after the third metal layer 50 is manufactured subsequently, since the film layer of the trench area NA1 is higher than the first insulating layer 40, the original step difference formed by the planarization layer 30 is reduced.

As shown in fig. 3, fig. 3 is a schematic cross-sectional view of a display panel in the vicinity of a groove area in the related art, in which a third metal layer 50 ' is directly disposed after a planarization layer 30 ' is manufactured in the related art, and a step difference value H ' (i.e., a distance between an upper surface of an inner film layer of the groove area NA1 ' and an upper surface of the planarization layer 30 ' outside the groove area NA1 ') caused by the planarization layer 30 ' is equal to a thickness H0 of the planarization layer 30 ' before the third metal layer 50 ' is manufactured.

However, with the structure provided by this embodiment, after the first insulating layer 40 with a thickness of H1 is disposed between the planarization layer 30 and the third metal layer 50, if the thickness of the planarization layer 30 is still H0, before the third metal layer 50 is fabricated, the step difference H caused by the planarization layer 30 is H0-H1 (obviously smaller than H0), which is equivalent to reducing the step difference caused by the thickness of the planarization layer 30, so that the conductive structure possibly remaining in the trench area NA1 (for example, the conductive structure possibly remaining in the trench area NA1 near the sidewall area of the planarization layer 30 when the third metal layer 50 is fabricated) is closer to the exposure light source (for example, the UV light source for performing the exposure process), so that the remaining conductive structure is easier to be exposed, and further, the risk of the line short circuit in the non-display area is reduced, for example, after the planarization layer 30 is not included in the trench area NA1, the remaining conductive structure of the third metal layer 50 and the second metal layer 202 or the first metal layer 201 therebelow are likely to be exposed The structures (such as fan-out leads arranged on the first metal layer 201 and the second metal layer 202) are in contact with each other to form a short circuit, so that the probability of occurrence of quality safety hazards is favorably reduced, and the yield of the display panel 000 products can be improved.

It can be understood that, the exposure process in this embodiment can be generally understood as setting up the photosensitive resist on the surface of the third metal layer 50, after the UV (Ultraviolet ) light passes through the preset mask plate, irradiate the photosensitive resist surface of the third metal layer that needs to be exposed, the transparent part on the mask plate, the UV light can pass through and irradiate on the photosensitive resist, make the resist produce the reaction, the black opaque part on the mask plate, the UV light can not pass through, so the partial resist does not produce the reaction, thereby make the pattern of mask plate, project to the photosensitive resist of coating on the surface of the third metal layer, the photosensitive resist has formed the pattern corresponding to the mask plate. And then spraying a developing solution on the surface of the exposed third metal layer, wherein the developing solution can dissolve the photosensitive photoresist which is irradiated by UV light to react, remove the photosensitive photoresist from the surface of the third metal layer, leave the part which is not irradiated by the UV light to remain on the surface of the third metal layer, and etch the rest part of the third metal layer which is not covered by the photosensitive photoresist, so that the part which is covered and protected by the photosensitive photoresist can be left, and the required patterned structure of the third metal layer is formed.

It can be understood that the structure of the display panel 000 in the embodiment includes, but is not limited to, the above structure, and may also include other structures, such as a structure of the display area AA capable of implementing display, and further, for example, some other insulating layers and electrode layers in the film layer structure for implementing an insulating effect.

It should be noted that the display panel 000 in this embodiment may be a liquid crystal display panel, an organic light emitting diode display panel, or another type of display panel, and this embodiment is not limited in particular. For example, in order to ensure the flatness of the anode region in the display panel during the preparation of the organic light emitting diode display panel, a thicker planarization layer is often required to be coated under the anode layer (which can be understood as the third metal layer in this embodiment), and in the subsequent anode yellow light process, due to the large step difference of the groove of the peripheral planarization layer, problems such as insufficient exposure occur during exposure, and further a part of photoresist remains after development, in the subsequent anode etching process, the remaining photoresist protects the anode that needs to be etched away, so that a part of anode remains, and the remaining anode also causes a short circuit of the display panel. Therefore, in the oled display panel in the related art, a first insulating layer in the embodiment may be disposed between the planarization layer and the anode layer to solve the problem of low yield.

It should be further noted that, the film structure of the display panel 000 provided in this embodiment includes, but is not limited to, the structure shown in fig. 2, on the side of the third metal layer 50 away from the first substrate 10, as shown in fig. 4, fig. 4 is a schematic diagram of a film layer structure of the display panel provided in this embodiment in the non-display area, the range outside the trench area NA1 may include other structures such as the first electrode layer 01, the second electrode layer 02, the insulating layer 03 therebetween, and the like, the range of the trench area NA1 may also leave a portion of the second electrode layer 02 on the side away from the planarization layer 30, the present embodiment for achieving the electrical connection between the conductive pad 03 and the fan-out lead 04 (which may be made by using the first metal layer 201 and/or the second metal layer 202) of the slotted region NA11 is not described herein again, and may be understood by referring to the film layer structure of the display panel in the related art. Optionally, as shown in fig. 4, the fan-out lead 04 in the trench area NA of the present embodiment is manufactured by replacing the first metal layer 201 and the second metal layer 202, and the second metal layer 202 of the trench area NA1 has a hollow area, and the manufacturing materials of the first metal layer 201 and the second metal layer 202 are set to be different, so as to be beneficial to reducing the impedance of the fan-out lead 04.

In some alternative embodiments, referring to fig. 1 and fig. 5 in combination, fig. 5 is a schematic view of another cross-sectional structure along the direction a-a' in fig. 1, in the present embodiment, in the direction Y parallel to the plane of the first substrate 10, the slotted region NA1 includes a first region NA11 close to the display region AA;

the first area NA11 does not include the first insulating layer 40.

The present embodiment explains that the trench area NA1 includes the first area NA11, the first area NA11 refers to an area of the region closer to the display area AA in the direction Y parallel to the plane of the first substrate 10 than the region of the trench area NA1 other than the first area NA11, and optionally, the first area NA11 may include a smaller area, that is, the width W1 of the first area NA11 is narrower in the direction Y parallel to the plane of the first substrate 10, as shown in fig. 5, the first area NA11 may refer to a small partial area of the side 30A of the planarization layer 30 next to the trench area NA1, which is more likely to remain metal in the first area NA11 because the side wall of the planarization layer 30 forms an angle with the plane of the first substrate 10 is more perpendicular. In the embodiment, at least the first insulating layer 40 is not included in the range of the first area NA11 of the trench area NA1, that is, the first insulating layer 40 in the range of the first area NA11 is etched cleanly, and then it is assumed that after the third metal layer 50 is exposed, there is residual metal before the first insulating layer 40 of the first area NA11 is etched, that is, after the step difference is reduced, there may be a smaller residual structure of the third metal layer 50 remaining in the first area NA11 due to uneven exposure or process error during the manufacturing process, and the residual structure may also be etched cleanly in the etching process of the first insulating layer 40 in the subsequent manufacturing process, so that the risk of short circuit of the lines in the trench area NA1 may be further reduced, and the yield of the display panel 000 may be further effectively improved.

Optionally, the first area NA11 may also include a slightly larger range, as shown in fig. 6, fig. 6 is another schematic cross-sectional structure of a direction a-a' in fig. 1, and along a direction Y parallel to the plane of the first substrate 10, the width W2 of the first area NA11 is slightly wider than that illustrated in fig. 5, so that the first insulating layer 40 is not disposed in the first area NA11 of most of the area in the grooved area NA1, which is beneficial to better avoiding the residue of the third metal layer 50 in the grooved area NA1, and further better ensuring the product yield.

It is understood that, in this embodiment, a specific width range of the first area NA11 is not specifically limited, and the entire slotted area NA1 may also be the first area NA11, that is, the entire slotted area NA1 does not include the first insulating layer 40, and in a specific implementation, a size range of the first area NA11 that does not include the first insulating layer 40 may be set according to actual requirements.

In some alternative embodiments, please continue to refer to fig. 1-2 and fig. 4-6, in this embodiment, the slotted region NA1 does not include the third metal layer 50.

The embodiment explains that after the first insulating layer 40 is disposed between the planarization layer 30 and the third metal layer 50, the film layer corresponding to the trench area NA1 is raised by the first insulating layer 40, so that the step difference caused by the thickness of the planarization layer 30 is reduced, and further, the conductive structure possibly remaining in the trench area NA1, such as the region of the trench area NA1 close to the sidewall of the planarization layer 30 when the third metal layer 50 is fabricated, is closer to the exposure light source, so that the remaining third metal layer 50 is more easily exposed, and therefore, the trench area NA1 may not include the third metal layer 50, that is, the third metal layer 50 without any exposure residue is within the range of the trench area NA1, thereby reducing the risk of short circuit in the non-display area and improving the yield of the display panel 000.

Optionally, the planarization layer 30 in this embodiment may further perform a thinning process, that is, the planarization layer 30 may be made thinner than that in the prior art, that is, on the basis of ensuring that the effect of the planarization layer 30 in the display area AA and ensuring that the display effect is not affected, the planarization layer 30 may be further made thinner, so that the step difference at the position of the trench area NA1 caused by the planarization layer 30 is further reduced, as shown in fig. 3, if the thickness of the planarization layer 30 ' in the related art is 3.3 μm, the step difference H ' caused by the planarization layer 30 ' in fig. 3 is equal to 3.3 μm. However, in the present embodiment, the planarization layer 30 is thinned, for example, the planarization layer 30 is thinned to 3 μm on the premise of ensuring the display effect, and at this time, the first insulating layer 40 is assumed to be 0.3 μm, and then the step H caused by the planarization layer 30 in fig. 2 is equal to 2.7 μm, fig. 2 of the present embodiment is compared with the scheme of fig. 3 in the related art, after the planarization layer 30 is thinned and the first insulating layer 40 is disposed between the planarization layer 30 and the third metal layer 50, the step H can be greatly reduced, and further, when the third metal layer 50 is exposed, the metal possibly remaining in the range of the trench digging area NA1 is closer to the exposure light source and is exposed cleanly, thereby better solving the problem of line short circuit caused by the metal residue.

Optionally, referring to fig. 7, fig. 7 is another schematic plan view of a display panel according to an embodiment of the present invention, the display panel 000 of this embodiment may also be a special-shaped display panel, as shown in fig. 7, the display panel 000 has a part of a special-shaped region, such as a concave notch, in the non-display area NA, so that a width of a part of the region in the first direction X, which is used as a slotted area for binding a driving chip or a flexible circuit board, is also reduced, and then when the slotted area NA1 needs to be provided with fan-out leads 04 to connect signal lines (such as scanning lines or data lines) of the display area AA with the binding pads 03 of the slotted area NA1, a distance between two adjacent fan-out leads 04 is also correspondingly reduced. If the film structure of the display panel of the present embodiment still adopts the structure shown in fig. 3 in the related art, it is likely that two different fan-out leads 04 with a smaller pitch may be short-circuited by the metal residue of the third metal layer 50 at a point of the trench area NA1, which causes a problem of product yield. With the structure illustrated in fig. 2 of this embodiment, after the first insulating layer 40 is disposed between the planarization layer 30 and the third metal layer 50, the metal possibly remaining in the trench area NA1 can be better exposed to light. Therefore, the technical solution of the embodiment can also be applied to the special-shaped display panel shown in fig. 7, so as to better solve the problem of short circuit in the non-display area.

In some alternative embodiments, please refer to fig. 1 and fig. 8 in combination, fig. 8 is another schematic cross-sectional view along a-a' direction in fig. 1, in this embodiment, in a direction Z perpendicular to a plane of the first substrate 10, the planarization layer 30 includes a bottom surface 30B facing to a side of the first substrate 10; in a direction X parallel to the plane of the first substrate 10, the planarization layer 30 includes a side 30A facing the trench area NA 1; the bottom surface 30B intersects the side surface 30A at an angle a that is less than 90 degrees.

This embodiment explains that the side 30A of the planarization layer 30 facing the trench area NA1 may be a structure with a certain slope, specifically, in the direction Z perpendicular to the plane of the first substrate 10, the planarization layer 30 includes a bottom surface 30B facing the side of the first substrate 10; in a direction X parallel to the plane of the first substrate 10, the planarization layer 30 includes a side surface 30A facing the trench area NA1, an angle α formed by the intersection of the bottom surface 30B and the side surface 30A is less than 90 °, and an angle α formed by the intersection of the optional bottom surface 30B and the side surface 30A may be any slope angle smaller than 90 °, which is not specifically limited in this embodiment, and in a specific implementation, the angle may be set according to actual requirements, so that the planarization layer 30 may be obliquely disposed toward the side surface 30A of the trench area NA1, and is inclined toward a position where an exposure light source directly above the display panel is located as much as possible, so as to receive more light, which is beneficial to further enable metal that may remain to be exposed cleanly after a step difference caused by the planarization layer 30 is reduced, and further reduces a risk of short circuit.

In some alternative embodiments, please refer to fig. 1 and 9 in combination, fig. 9 is another schematic cross-sectional structure diagram along the direction of a-a' in fig. 1, in this embodiment, a black matrix layer 60, a color film layer 70, and a protection layer 80 are further included between the first insulating layer 40 and the third metal layer 50, the black matrix layer 60 is located on a side of the first insulating layer 40 away from the first substrate 10, the color film layer 70 is located on a side of the black matrix layer 60 away from the first substrate 10, and the protection layer 80 is located on a side of the color film layer 70 away from the first substrate 10;

the black matrix layer 60 includes a first black matrix portion 601 and a second black matrix portion 602, the color film layer 70 includes a first color film portion 701 and a second color film portion 702, the first black matrix portion 601 and the first color film portion 701 are located in the groove area NA1, and the second black matrix portion 602 and the second color film portion 702 are located outside the groove area NA 1;

the second black matrix portion 602 includes a plurality of first hollow holes 6021, the second color film portion 702 includes a plurality of first color resistors 7021, and the first color resistors 7021 are located in the first hollow holes 6021.

This embodiment explains that the display panel 000 further adopts a technology of integrating a Color filter On Array (COA), that is, the Color resistance is included while the thin film transistor Array layer 20 is disposed On the first substrate 10, and the COA structure can improve the aperture ratio of the panel and improve the display quality of the panel. The first insulating layer 40 and the third metal layer 50 of this embodiment further include a black matrix layer 60, a color film layer 70, and a protective layer 80 therebetween, where the black matrix layer 60 is used to provide a light shielding structure for shielding metal signal lines, and the black matrix layer 60 may also be used to provide a structure for preventing crosstalk between color resistors of different colors. The color film layer 70 is used for setting a plurality of color resistors with different colors, and the protective layer 80 covers the color film layer 70, so that the lower film layer of the third metal layer 50 can be as flat as possible while the structure of the color film layer 70 is protected. The black matrix layer 60 of the present embodiment includes a first black matrix portion 601 located within the range of the recessed area NA1 and a second black matrix portion 602 located outside the range of the recessed area NA1, the color film layer 70 includes a first color film portion 701 located within the range of the recessed area NA1 and a second color film portion 702 located outside the range of the recessed area NA1, and optionally, at least a portion of the second black matrix portion 602 and at least a portion of the second color film portion 702 are located within the range of the display area AA, and are used for forming sub-pixels of the display area AA, so as to achieve the effect. In the embodiment, the second black matrix portion 602 includes a plurality of first hollow holes 6021, the second color film portion 702 includes a plurality of first color resists 7021, the first color resists 7021 are located in the first hollow holes 6021, optionally, the first color resists 7021 are located in the first hollow holes 6021, which can be understood as being along a direction Y parallel to a plane of the first substrate 10, an outer diameter of the first color resists 7021 is the same as an aperture of the first hollow holes 6021 (as shown in fig. 9), and one first color resist 7021 is just embedded in the first hollow hole 6021; or the first color resist 7021 is located in the first hollow hole 6021, it can also be understood that along the direction Y parallel to the plane of the first substrate 10, the outer diameter of the first color resist 7021 is larger than the aperture of the first hollow hole 6021 (not shown in the drawings), so that one first color resist 7021 can well cover the first hollow hole 6021 and fill the pore formed by the first hollow hole 6021 of the second black matrix part 602. In the embodiment, the outer diameter of the first color resist 7021 and the aperture size of the first through hole 6021 are not specifically limited along the direction Y parallel to the plane of the first substrate 10, and at least a portion of the first color resist 7021 is located in the first through hole 6021.

The grooved area NA1 of the present embodiment includes the first black matrix portion 601 and the first color film portion 701, and the black matrix layer 60 and the color film layer 70, which are only disposed above the planarization layer 30 in the prior art, are extended into the range of the grooved area NA1, so that the first black matrix portion 601 and the first color film portion 701 of the grooved area NA1 also function to elevate the inner film layer of the grooved area NA1, and through cooperation with the first insulating layer 40, the step difference formed by the planarization layer 30 is further reduced, so that the conductive structure possibly remaining in the grooved area NA1 is closer to the exposure light source, and is more easily exposed, and further the risk of short circuit of the lines in the non-display area is reduced, and the product yield is improved.

It can be understood that, in this embodiment, specific structures of the first black matrix portion 601 and the first color film portion 701 in the grooved area NA1 are not limited, and the first black matrix portion 601 and the first color film portion 701 in the grooved area NA1 may be manufactured in the same process as the second black matrix portion 602 and the second color film portion 702 outside the grooved area NA1, or the first black matrix portion 601 and the first color film portion 701 in the grooved area NA1 may be manufactured in the same process as the second black matrix portion 602 and the second color film portion 702 outside the grooved area NA1, but in a different process, and it is only necessary that the grooved area NA1 has the first black matrix portion 601 and the first color film portion 701 functioning as a pad height. It should be noted that the first black matrix portion 601 and the first color film portion 701 in the grooved area NA1 in this embodiment can be understood as a virtual black matrix portion and a virtual color film portion, and their functions are not related to display, and therefore their shapes can be arbitrarily set, which is not limited in this embodiment.

Optionally, please refer to fig. 1 and fig. 10 in combination, fig. 10 is another schematic cross-sectional structure view along the direction of a-a' in fig. 1, in this embodiment, the first black matrix portion 601 includes a plurality of second hollow holes 6011, the first color film portion 701 includes a plurality of second color resists 7011, and the second color resists 7011 are located in the second hollow holes 6011; wherein, in the direction Z perpendicular to the plane of the first substrate 10, the thickness C1 of the second color resistor 7011 is greater than the thickness C2 of the first color resistor 7021.

The embodiment explains that the first black matrix 601 in the trench area NA1 may also include a plurality of second through holes 6011, and the first color film 701 includes a plurality of second color resists 7011, that is, the first black matrix 601 in the trench area NA1, the first color film 701, and the second black matrix 602 and the second color film 702 outside the trench area NA1 are manufactured in the same process, which may reduce the difficulty in manufacturing the black matrix layer 60 and the color film 70. The second color resists 7011 of the first color film part 701 are located in the second hollow holes 6011 of the first black matrix part 601, and it can be understood that along a direction Y parallel to the plane of the first substrate 10, the outer diameter of the second color resists 7011 is the same as the aperture of the second hollow holes 6011, and one second color resist 7011 is just embedded in the second hollow hole 6011; or the second color resist 7011 is located in the second hollow-out hole 6011, it can also be understood that along the direction Y parallel to the plane of the first substrate 10, the outer diameter of the second color resist 7011 is larger than the aperture of the second hollow-out hole 6011, so that one second color resist 7011 can well cover the second hollow-out hole 6011 and fill the void formed by the second hollow-out hole 6011 of the first black matrix 601. In this embodiment, the outer diameter of the second color resist 7011 and the aperture size of the second through hole 6011 are not specifically limited along the direction Y parallel to the plane of the first substrate 10, and only a portion of the second color resist 7011 needs to be located in the second through hole 6011.

In the direction Z perpendicular to the plane of the first substrate 10, the thickness C1 of the second color resistor 7011 is greater than the thickness C2 of the first color resistor 7021, that is, the thickness C1 of the second color resistor 7011 in the trench area NA1 is greater than the thickness C2 of the first color resistor 7021 outside the trench area NA1 by thickening the second color resistor 7011 in the trench area NA1, so that the inner film layer of the trench area NA1 can be further heightened, which is favorable for further reducing the step difference caused by the thickness of the planarization layer 30.

Optionally, as shown in fig. 11, fig. 11 is another schematic cross-sectional structure view along a-a' direction in fig. 1, in this embodiment, by increasing the thickness C1 of the second color resistor 7011 of the trench area NA1, the surface 80A of the protection layer 80 in the trench area NA1, which is away from the first substrate 10, may be flush with the surface 30C of the planarization layer 30 outside the trench area NA1, which is away from the first substrate 10, so as to better increase exposure light to which the possibly remaining metal is exposed, and to better solve the short circuit problem.

In some alternative embodiments, please refer to fig. 1 and 12 in combination, fig. 12 is another cross-sectional structure diagram along the direction of a-a' in fig. 1, in this embodiment, the first black matrix 601 in the recessed area NA1 is in a full-face structure in the recessed area NA1, the first color film portion 701 includes a plurality of third color resistors 7012, and in the direction Z perpendicular to the plane of the first substrate 10, the plurality of third color resistors 7012 are located on a side of the first black matrix 601 away from the first substrate 10.

This embodiment explains that the first black matrix 601 in the grooved area NA1 may be a whole-surface structure, that is, no hollow hole is provided for placing the first color film part 701, and the first black matrix 601 in the grooved area NA1 and the second black matrix 602 outside the grooved area NA1 may be manufactured in the same layer but by different processes. Since the first black matrix portion 601 and the first color film portion 701 of the grooved area NA1 can be understood as a virtual black matrix portion and a virtual color film portion, and their functions are independent of the display, the first black matrix portion 601 in the grooved area NA1 is configured as a whole structure, which has no influence on the display effect of the display area AA. In this embodiment, the first color film part 701 of the grooved area NA1 is still configured to include a plurality of third color resists 7012, and in the direction Z perpendicular to the plane of the first substrate 10, the plurality of third color resists 7012 are located on the side of the first black matrix part 601 of the entire structure away from the first substrate 10, so that the first color film part 701 in the grooved area NA1 and the second color film part 702 outside the grooved area NA1 can still be manufactured by the same process in the same layer, that is, even if the first color resist 7021 and the third color resist 7012 have the same deposition thickness, the first black matrix part 601 is not hollowed out, so that the film layer in the range of the grooved area NA1 can be further lifted, and the step difference can be reduced.

In some alternative embodiments, please refer to fig. 1 and 13 in combination, fig. 13 is another schematic cross-sectional structure diagram along the direction a-a' in fig. 1, in this embodiment, the first black matrix 601 and the first color film 701 are both in a full-face structure in the grooved area NA1, and in the direction Z perpendicular to the plane of the first substrate 10, the first color film 701 is located on a side of the first black matrix 601 away from the first substrate 10.

This embodiment explains that the first black matrix 601 and the first color film 701 in the trench area NA1 may both be of a full-face structure, the first black matrix 601 in the trench area NA1 and the second black matrix 602 outside the trench area NA1 may be fabricated in the same layer but by different processes, and the first color film 701 in the trench area NA1 and the second color film 702 outside the trench area NA1 may be fabricated in the same layer but by different processes. Since the first black matrix part 601 and the first color film part 701 of the grooved area NA1 can be understood as a virtual black matrix part and a virtual color film part, and their functions are independent of the display, the first black matrix part 601 and the first color film part 701 in the grooved area NA1 are configured as a whole structure, which has no influence on the display effect of the display area AA. In a direction Z perpendicular to a plane of the first substrate 10, the first color film portion 701 of the entire structure is located on a side of the first black matrix portion 601 of the entire structure away from the first substrate 10, that is, after the black matrix layer 60 is completely disposed on the entire surface, only the second black matrix portion 602 outside the trench area NA1 needs to be hollowed out, and then the color film layer 70 can be disposed, and only the second color film portion 702 outside the trench area NA1 needs to be patterned, so that the first color resist 7021 of the second color film portion 702 is located in the first hollowed hole 6021 of the second black matrix portion 602, and since the first black matrix portion 601 and the first color film portion 701 of the trench area NA1 are both of the entire structure, the film layer within the range of the trench area NA1 can be further padded, and the step difference can be reduced.

In some alternative embodiments, please refer to fig. 1 and fig. 14 in combination, fig. 14 is another schematic cross-sectional view along the direction a-a' in fig. 1, in this embodiment, in the direction Z perpendicular to the plane of the first substrate 10, the first color film portion 701 includes a plurality of color resist layers 701A of different colors stacked.

In this embodiment, it is explained that when the first color film portion 701 of the recessed area NA1 is of a full-face structure, the thickness of the first color film portion 701 formed by one color-resist layer in the direction Z perpendicular to the plane of the first substrate 10 is limited, so that in order to further increase the film layer of the recessed area NA1, the first color resist 7021 of different colors may be manufactured outside the recessed area NA1 of the display panel 000, the first color film portion 701 in the recessed area NA1 may also be set as a plurality of stacked color-resist layers 701A of different colors, the color-resist layers 701A of different colors may be matched with the colors of the first color resists 7021 of different colors outside the recessed area NA1, the first color resist 7021 and the color-resist layer 701A of the same color may be made of the same material, which is beneficial to reduce the step difference and simultaneously reduce the process steps.

In some alternative embodiments, please refer to fig. 15 and 16 in combination, fig. 15 is a schematic plan view illustrating a display panel according to an embodiment of the present invention, fig. 16 is a schematic cross-sectional view taken along the direction B-B' in fig. 15, in this embodiment, the trench NA1 includes a metal portion 90, and the metal portion 90 and the third metal layer 50 are made of the same material;

in the slotted region NA1, the display panel 000 includes a plurality of fan-out leads 100, one fan-out lead 100 at least includes a first subsection 100A, a second subsection 100B, and a third subsection 100C, and two ends of the second subsection 100B are electrically connected to the first subsection 100A and the third subsection 100C, respectively;

second sub-segment 100B is located in first metal layer 201, and first sub-segment 100A and third sub-segment 100C are located in second metal layer 202;

in the recessed area NA1, along the arrangement direction of the first sub-segments 100A (e.g. the first direction X in fig. 12), in the direction parallel to the plane of the first substrate 10, the width of the metal portion 90 is D1, and the distance between two adjacent first sub-segments 100A is D2, where D1 < D2.

This embodiment explains that the slotted area NA1 of the display panel 000 may be provided with a plurality of fan-out leads 100, and the fan-out leads 100 may be used to electrically connect signal lines within the display area AA of the display panel 000 with the bonding pads 03. One fan-out lead 100 may include at least a first subsegment 100A, a second subsegment 100B, and a third subsegment 100C, where two ends of the second subsegment 100B are electrically connected to the first subsegment 100A and the third subsegment 100C, respectively, where the first subsegment 100A, the second subsegment 100B, and the third subsegment 100C may be located at least at two different metal layers, that is, the second subsegment 100B is located at the first metal layer 201, and the first subsegment 100A and the third subsegment 100C are located at the second metal layer 202, because the first metal layer 201 and the second metal layer 202 may be made of different metal materials, impedance may be reduced, and at the same time, two different fan-out leads 100 of different metal film layers may have a partially overlapped region, which is beneficial to providing more wiring space for the fan-out leads 100, and avoiding short circuit caused by too close distance between each other. In this embodiment, no specific details are given to the effect of manufacturing the first subsegment 100A, the second subsegment 100B, and the third subsegment 100C in which different metal film layers are adopted for one fan-out lead 100, and the structure of the fan-out lead for line replacement design can be understood with specific reference to the display panel in the related art.

The recessed area NA1 of the present embodiment may also include a metal portion 90 that is made of the same material as the third metal layer 50, i.e., in the process of exposing the third metal layer 50, although the step difference is reduced by the first insulating layer 40, there may be a portion of the third metal layer 50 left, i.e., the metal portion 90, whose exposure intensity is not sufficient. The present embodiment is disposed in a direction parallel to the plane of the first substrate 10, along the arrangement direction of the first subsegments 100A (e.g., the first direction X in fig. 12), where the first subsegment 100A is a portion of one fan-out lead 100 closest to the side 30A of the planarization layer 30, and the width D1 of the metal part 90 is smaller than the distance D2 between two adjacent first subsegments 100A, so that even though the metal part 90 remains in the area of the slotted region NA1 close to the side 30A of the planarization layer 30, the width D1 of the metal part 90 in the first direction X is smaller and is not enough to connect two adjacent first subsegments 100A to short (even though the metal part 90 overlaps the first subsegment 100A of one fan-out lead 100, the two first subsegments 100A of two different fan-out leads 100 cannot be shorted due to the smaller width D1 in the first direction X), so that the display panel 000 of the present embodiment can still reduce the risk of short circuit in the slotted region NA1, the yield of the product is improved.

Optionally, please refer to fig. 15 and fig. 16 in combination, in the embodiment, in the display area AA of the display panel 000, the display panel 000 includes a plurality of signal lines S (in the embodiment, the signal lines S are taken as an example for an example of a data line), and the first sub-segment 100A is electrically connected to the signal lines S through the fanout lines 200; the fanout line 200 is located in the non-display area NA outside the grooved area NA 1;

in the slotted region NA1, the display panel 000 includes a plurality of conductive pads 03, and the third subsection 100C is electrically connected to the conductive pads 03.

The embodiment explains that the non-display area NA of the display panel 000 may further include a fan-out line 200 connecting the first sub-section 100A of the fan-out lead 100 and the signal line S in the display area AA together, one end of the fan-out line 200 is connected to one end of the signal line S close to the slotted area NA1, the other end of the fan-out line 200 is connected to the first sub-section 100A of the fan-out lead 100, the third sub-section 100C of the fan-out lead 100 may be electrically connected to a conductive pad 03 disposed on the display panel 000, and the conductive pad 03 may be disposed in an area farther from the display area AA in the range of the slotted area NA1 for subsequent bonding of a driver chip or a flexible circuit board. The fan-out line 200 of the embodiment is configured to transmit the external driving signal transmitted by the bonding pad 03 to the signal line S in the display area AA of the display panel 000 through the fan-out lead 100, so as to achieve the display effect of the display panel.

It can be understood that, in the present embodiment, details of the bending shape, the arrangement structure, and the like of the fan-out line 200 and the fan-out lead 100 are not described, and the details can be understood with reference to the structure of the display panel capable of reducing the frame width as much as possible in the related art.

In some optional embodiments, please refer to fig. 1-2, 15-16, 17, and 18-23 in combination (it is understood that a film structure of the display panel in the non-display region is only illustrated in a film structure diagram of the present embodiment, and the film structure of the display region can be understood by referring to a manufacturing process of the display panel in the related art, which is not repeated in the present embodiment), fig. 17 is a flowchart of a manufacturing method of the display panel provided in the embodiment of the present invention, fig. 18 is a structural diagram of the first substrate 10 provided in fig. 17, fig. 19 is a structural diagram after the thin film transistor array layer is manufactured in fig. 17, fig. 20 is a structural diagram after the planarization layer is manufactured in fig. 17, fig. 21 is a structural diagram after the trench digging region is formed in the non-display region in fig. 17, fig. 22 is a structural diagram after the first insulating layer is manufactured in fig. 17, fig. 23 is a schematic structural diagram after the third metal layer is manufactured in fig. 17, and the manufacturing method provided in this embodiment is used for manufacturing the display panel 000 in the foregoing embodiment, and the manufacturing method includes:

s10: providing a first substrate 10, as shown in fig. 18;

s11: fabricating a thin film transistor array layer 20 on one side of the first substrate 10, such that the thin film transistor array layer 20 includes at least a first metal layer 201 and a second metal layer 202 insulated from each other, as shown in fig. 19;

s12: forming a planarization layer 30 on the side of the thin film transistor array layer 20 away from the first substrate 10, as shown in fig. 20;

s13: etching the planarization layer 30 in the non-display area NA to form the trench area NA1 such that the trench area NA1 does not include the planarization layer 30, as shown in fig. 21; optionally, after the first metal layer 201 and the second metal layer 202 which are insulated from each other are manufactured, in the trench area NA1, the display panel 000 may include a plurality of fan-out leads 100, one fan-out lead 100 at least includes a first sub-section 100A, a second sub-section 100B, and a third sub-section 100C, and two ends of the second sub-section 100B are electrically connected to the first sub-section 100A and the third sub-section 100C, respectively; second sub-segment 100B is located in first metal layer 201, and first sub-segment 100A and third sub-segment 100C are located in second metal layer 202;

s14: forming a first insulating layer 40 on a side of the planarization layer 30 away from the first substrate 10, such that the first insulating layer 40 is located in the display area AA and the non-display area NA, as shown in fig. 22;

s15: a third metal layer 50 is formed on the side of the first insulating layer 40 remote from the first substrate 10, as shown in fig. 23.

In the manufacturing method provided in this embodiment, before the third metal layer 50 is manufactured, a first insulating layer 40 is manufactured on the planarization layer 30, so that the film layer in the trench area NA1 is lifted, optionally, as shown in fig. 22, after the first insulating layer 40 is manufactured, in the trench area NA1, a side of the first insulating layer 40 away from the first substrate 10 is a first surface 40A, and outside the trench area NA1, a surface of the planarization layer 30 away from the first substrate 10 is a second surface 30C; the distance H between the first surface 40A and the second surface 30C in the direction Z perpendicular to the plane of the first substrate 10 is in the range of 2.0 μm to 3.3 μm, and optionally, the distance H between the first surface 40A and the second surface 30C in the direction Z perpendicular to the plane of the first substrate 10 may be in the range of 2.2 μm to 2.7 μm, and the step difference of the planarization layer 30 before the third metal layer 50 is formed is reduced to 2.0 μm to 3.3 μm or 2.2 to 2.7 μm by the arrangement of the first insulating layer 40, which is beneficial for reducing the conductive structure possibly remaining on the sidewall area of the trench area NA1 close to the planarization layer 30 closer to the exposure light source during the exposure and patterning of the third metal layer 50 in the subsequent process, so that the remaining third metal layer 50 is more easily exposed to the clean, thereby reducing the risk of short circuit in the non-display area, thereby improving the yield of the display panel 000.

It can be understood that the display panel 000 manufactured by the manufacturing method of the embodiment has the beneficial effects of the display panel in the above embodiments, and the embodiment is not described herein again, and can be understood by specifically referring to the beneficial effects in the above embodiments.

It should be noted that the manufacturing method of the display panel of the present embodiment includes, but is not limited to, the above-mentioned process steps, and may also include other process steps such as patterning the individual film layers and disposing the insulating layer between the two metal film layers, and the specific implementation can be understood according to the process in the related art.

In some optional embodiments, please refer to fig. 1, fig. 5, fig. 6, fig. 24 and fig. 25 in combination, where fig. 24 is another flow chart of a manufacturing method of a display panel according to an embodiment of the present invention, fig. 25 is a schematic structural diagram after etching a first insulating layer in fig. 24, and in the manufacturing method according to the embodiment, after manufacturing a third metal layer 50 on a side of the first insulating layer 40 away from the first substrate 10, the method further includes:

s16: etching the first insulating layer 40 at least such that the first region NA11 of the grooved region NA1 does not include the first insulating layer 40; here, the first area NA11 is an area close to the display area AA in the slotted area NA1 in the direction Y parallel to the plane of the first substrate 10, as shown in fig. 25.

This embodiment illustrates that after the third metal layer 50 is formed on the side of the first insulating layer 40 away from the first substrate 10, including after the third metal layer 50 is subjected to exposure patterning, the etching of the first insulating layer 40 may be further included, so that at least the first region NA11 of the grooved region NA1 does not include the first insulating layer 40; the first area NA11 is an area of the slotted area NA1 close to the display area AA in the direction Y parallel to the plane of the first substrate 10, the first area NA11 is closer to an area of the display area AA than an area of the slotted area NA1 except for the first area NA11, optionally, the first area NA11 may include a smaller area (as shown in fig. 5), the first area NA11 may also include a larger area (as shown in fig. 6), or all the first insulating layers 40 of the slotted area NA1 may be etched (the slotted area NA1 is the first area NA11), which is not limited in this embodiment. The first region NA11 may refer to a small portion of the side 30A of the planarization layer 30 immediately outside the recessed region NA1, which is more likely to remain in the first region NA11 during the exposure of the third metal layer 50 because the side wall of the planarization layer 30 forms a relatively perpendicular angle with the plane of the first substrate 10. In the embodiment, at least the first insulating layer 40 is not included in the range of the first area NA11 of the trench area NA1, that is, the first insulating layer 40 in the range of the first area NA11 is etched cleanly, and then it is assumed that after the third metal layer 50 is exposed, there is residual metal before the first insulating layer 40 of the first area NA11 is etched, that is, there is still a smaller residual structure of the third metal layer 50 remaining in the first area NA11 due to uneven exposure or process error in the manufacturing process after the step difference is reduced, and the residual structure is also etched cleanly in the etching process of the first insulating layer 40 of the first area NA11, so that the risk of short circuit of the NA1 lines in the trench area can be further reduced, and the yield of the display panel 000 can be further effectively improved.

In some optional embodiments, please refer to fig. 1, fig. 5, fig. 6, fig. 18 to fig. 23, fig. 26, and fig. 27 in combination, where fig. 26 is another flow chart of a manufacturing method of a display panel according to an embodiment of the present invention, fig. 27 is a schematic structural diagram after a third metal layer is manufactured in fig. 26, and the manufacturing method according to the embodiment includes:

s20: providing a first substrate 10, as shown in fig. 18;

s21: fabricating a thin film transistor array layer 20 on one side of the first substrate 10, such that the thin film transistor array layer 20 includes at least a first metal layer 201 and a second metal layer 202 insulated from each other, as shown in fig. 19;

s22: forming a planarization layer 30 on the side of the thin film transistor array layer 20 away from the first substrate 10, as shown in fig. 20;

s23: etching the planarization layer 30 in the non-display area NA to form the trench area NA1 such that the trench area NA1 does not include the planarization layer 30, as shown in fig. 21;

s24: forming a first insulating layer 40 on a side of the planarization layer 30 away from the first substrate 10, such that the first insulating layer 40 is located in the display area AA and the non-display area NA, as shown in fig. 22;

s25: forming a third metal layer 50 on the side of the first insulating layer 40 away from the first substrate 10, as shown in fig. 27;

s26: the third metal layer 50 is exposed such that the slotted region NA1 does not include the third metal layer 50, as shown in fig. 23.

This embodiment explains that, because the first insulating layer 40 is disposed between the planarization layer 30 and the third metal layer 50 before the third metal layer 50 is patterned by exposure, and the film layer corresponding to the trench area NA1 is raised by the first insulating layer 40, the step difference caused by the thickness of the planarization layer 30 is reduced, so that when the third metal layer 50 is exposed, the metal possibly remaining in the trench area NA1 is closer to the exposure light source, so that the remaining third metal layer 50 is more easily exposed, and therefore, after the third metal layer 50 is exposed, the trench area NA1 may not include the third metal layer 50, that is, the third metal layer 50 without any exposure residue is within the range of the trench area NA1, thereby reducing the risk of line short circuit in the non-display area, and improving the yield of the display panel 000 products.

In some alternative embodiments, please refer to fig. 15-16, 18-22, 27, 28 and 29 in combination, where fig. 28 is another flow chart of a manufacturing method of a display panel according to an embodiment of the present invention, fig. 29 is a schematic structural diagram after exposing a third metal layer in fig. 28, and the manufacturing method according to the embodiment includes:

s30: providing a first substrate 10, as shown in fig. 18;

s31: fabricating a thin film transistor array layer 20 on one side of the first substrate 10, such that the thin film transistor array layer 20 includes at least a first metal layer 201 and a second metal layer 202 insulated from each other, as shown in fig. 19;

s32: forming a planarization layer 30 on the side of the thin film transistor array layer 20 away from the first substrate 10, as shown in fig. 20;

s33: etching the planarization layer 30 in the non-display area NA to form the trench area NA1 such that the trench area NA1 does not include the planarization layer 30, as shown in fig. 21;

s34: forming a first insulating layer 40 on a side of the planarization layer 30 away from the first substrate 10, such that the first insulating layer 40 is located in the display area AA and the non-display area NA, as shown in fig. 22;

s35: forming a third metal layer 50 on the side of the first insulating layer 40 away from the first substrate 10, as shown in fig. 27;

s36: the third metal layer 50 is exposed, so that in the trench area NA1, the third metal layer 50 includes a metal portion 90, and in a direction Y parallel to the plane of the first substrate 10, along the arrangement direction (the first direction X) of the first sub-segments 100A, the width of the metal portion 90 is D1, and the distance between two adjacent first sub-segments 100A is D2, and D1 < D2 (as shown in fig. 15).

In the manufacturing method provided in this embodiment, in the process of exposing the third metal layer 50, although the step is reduced by the first insulating layer 40, there may be a small portion of the third metal layer 50 remaining due to insufficient exposure intensity, that is, the metal portion 90. However, since the residual metal portion 90 in the trench area NA1 is relatively close to the exposure light source during exposure, it can be exposed as small as possible, so that finally, in a direction parallel to the plane of the first substrate 10 and along the arrangement direction of the first subsegments 100A (as the first direction X in fig. 12), the width D1 of the residual metal portion 90 is smaller than the distance D2 between two adjacent first subsegments 100A, so that even if the metal portion 90 remains in the area of the trench area NA1 close to the side surface of the planarization layer 30, the width D1 of the metal portion 90 in the first direction X is smaller and is not enough to connect and short-circuit two adjacent first subsegments 100A, which can still reduce the risk of short circuit in the trench area NA1 and improve the yield of products.

In some alternative embodiments, please refer to fig. 1-2 and fig. 18-20, and fig. 30-33 in combination, where fig. 30 is another flow chart of a manufacturing method of a display panel according to an embodiment of the present invention, fig. 31 is a schematic view of a structure after forming a trench in a non-display region in fig. 30, fig. 32 is a schematic view of a structure after a first insulating layer is manufactured in fig. 30, and fig. 33 is a schematic view of a structure after a third metal layer is manufactured in fig. 30, and the manufacturing method according to the embodiment includes:

s40: providing a first substrate 10, as shown in fig. 18;

s41: fabricating a thin film transistor array layer 20 on one side of the first substrate 10, such that the thin film transistor array layer 20 includes at least a first metal layer 201 and a second metal layer 202 insulated from each other, as shown in fig. 19;

s42: forming a planarization layer 30 on the side of the thin film transistor array layer 20 away from the first substrate 10, as shown in fig. 20;

s43: etching the planarization layer 30 in the non-display area NA to form a trench area NA1 such that the trench area NA1 does not include the planarization layer 30; so that, in a direction Z perpendicular to the plane of the first substrate 10, the etched planarization layer 30 includes a bottom surface 30B facing the first substrate 10 side; in a direction Y parallel to the plane of the first substrate 10, the etched planarization layer 30 includes a side 30A facing the trench area NA 1; the bottom surface 30B intersects the side surface 30A at an angle a of less than 90 degrees, as shown in fig. 30.

S44: forming a first insulating layer 40 on a side of the planarization layer 30 away from the first substrate 10, such that the first insulating layer 40 is located in the display area AA and the non-display area NA, as shown in fig. 31;

s45: a third metal layer 50 is formed on the side of the first insulating layer 40 remote from the first substrate 10, as shown in fig. 32.

In the process of fabricating the planarization layer 30, when the planarization layer 30 in the non-display area NA is etched, a side surface 30A of the final planarization layer 30 facing the trench area NA1 may have a certain slope, specifically, the planarization layer 30 is etched in the non-display area NA to form a trench area NA1, so that the trench area NA1 does not include the planarization layer 30, and the etched planarization layer 30 includes a bottom surface 30B facing one side of the first substrate 10 in a direction Z perpendicular to a plane of the first substrate 10; in a direction Y parallel to the plane of the first substrate 10, the etched planarization layer 30 includes a side 30A facing the trench area NA 1; an included angle α formed by the intersection of the bottom surface 30B and the side surface 30A is smaller than 90 degrees, and an included angle α formed by the intersection of the optional bottom surface 30B and the side surface 30A may be any slope angle smaller than 90 degrees, such as 45 °, 60 °, 65 °, 70 °, 75 °, 80 °, and the like.

In some alternative embodiments, please refer to fig. 18, fig. 19, and fig. 34 to fig. 40 in combination, where fig. 34 is another flow chart of the method for manufacturing a display panel according to the embodiment of the present invention, fig. 35 is a schematic view of a structure after the first sub-layer is manufactured in fig. 34, fig. 36 is a schematic view of a structure after the first sub-layer is etched in fig. 34, fig. 37 is a schematic view of a structure after the second sub-layer is manufactured in fig. 34, fig. 38 is a schematic view of a structure after the second sub-layer is etched in fig. 34, fig. 39 is a schematic view of a structure after the first insulating layer is manufactured in fig. 34, and fig. 40 is a schematic view of a structure after the third metal layer is manufactured in fig. 34, where the manufacturing method provided in this embodiment is used for manufacturing the display panel 000 in the above embodiment, and includes:

s50: providing a first substrate 10, as shown in fig. 18;

s51: fabricating a thin film transistor array layer 20 on one side of the first substrate 10, such that the thin film transistor array layer 20 includes at least a first metal layer 201 and a second metal layer 202 insulated from each other, as shown in fig. 19;

s52: fabricating a first sub-layer 301 on a side of the thin film transistor array layer 20 away from the first substrate 10, as shown in fig. 35;

s53: etching the first sub-layer 301 in the non-display area NA to form a trench area NA1, wherein the trench area NA1 does not include the first sub-layer 301, and in a direction Z perpendicular to the plane of the first substrate 10, the etched first sub-layer 301 includes a first bottom surface 301B facing the first substrate 10; in a direction Y parallel to the plane of the first substrate 10, the etched first sublayer 301 comprises a first side 301A facing the trench area NA 1; the first bottom surface 301B intersects the first side surface 301A to form an included angle α 1, as shown in fig. 36;

s54: fabricating the second sub-layer 302 on the side of the first sub-layer 301 remote from the first substrate 10, such that the second sub-layer 302 covers the first sub-layer 301, as shown in fig. 37;

s55: etching the second sub-layer 302 in the non-display area NA such that the grooved area NA1 does not include the second sub-layer 302, and in a direction Z perpendicular to the plane of the first substrate 10, such that the etched second sub-layer 302 includes a second bottom surface 302B facing the first substrate 10; in a direction Y parallel to the plane of the first substrate 10, the etched second sublayer 302 comprises a second side 302A facing the trench area NA 1; the second bottom surface 302B intersects the second side surface 302A to form an included angle α 2; where α 1 > α 2, α 2 < 90 °, as shown in fig. 38, the first sub-layer 301 and the second sub-layer 302 form the planarization layer 30;

s56: forming a first insulating layer 40 on a side of the second sub-layer 302 away from the first substrate 10, such that the first insulating layer 40 is located in the display area AA and the non-display area NA, as shown in fig. 39;

s57: a third metal layer 50 is formed on the side of the first insulating layer 40 remote from the first substrate 10, as shown in fig. 40.

This embodiment explains that in order to make the side 30A of the planarization layer 30 facing the trench area NA1 have a slope, the planarization layer 30 can be manufactured by dividing into at least two sub-layers, and the slope can be easily formed by dividing the two sub-layers to manufacture the side of the finally manufactured planarization layer 30. That is, the first sub-layer 301 is firstly formed on the side of the thin film transistor array layer 20 away from the first substrate 10, and then the first sub-layer 301 is etched in the non-display region NA to form the trench area NA1, so that the trench area NA1 does not include the first sub-layer 301, and an included angle α 1 formed by the intersection of the first bottom surface 301B of the first sub-layer 301 and the first side surface 301A may be smaller than 90 degrees or equal to 90 degrees. Then, the second sublayer 302 of the planarization layer 30 is formed on the side of the first sublayer 301 away from the first substrate 10, so that the second sublayer 302 covers the first sublayer 301, and then etching is performed, so that an included angle α 2 formed by the intersection of the second bottom surface 302B and the second side surface 302A of the second sublayer 302 is smaller than 90 °, optionally α 1 > α 2, and optionally α 2 may be any slope angle smaller than 90 degrees, such as 45 °, 60 °, 65 °, 70 °, 75 °, 80 °, and the like, which is not particularly limited in this embodiment, in a specific implementation, the second sublayer 302 of the planarization layer 30 may be inclined toward the second side surface 302A of the trench area NA1, and inclined as much as possible toward a position direction of an exposure light source directly above the display panel, so as to receive more light, which is favorable for further enabling a possibly remaining metal to be exposed cleanly after a step difference caused by the planarization layer 30 is reduced, the risk of short circuits is further reduced.

It is understood that, in this embodiment, the first sub-layer 301 and the second sub-layer 302 may be made of a transparent insulating material with the same material, or may be made of a transparent insulating material with a different material.

In some optional embodiments, please refer to fig. 1, 9-14, and 41 in combination, where fig. 41 is another flow chart of the manufacturing method of the display panel according to the embodiment of the present invention, in the manufacturing method according to the embodiment, before the manufacturing of the third metal layer 50, the method further includes:

s140: manufacturing the black matrix layer 60 on a side of the first insulating layer 40 away from the first substrate 10, such that the black matrix layer 60 includes a first black matrix portion 601 and a second black matrix portion 602, the first black matrix portion 601 is located in the groove area NA1, the second black matrix portion 602 is located outside the groove area NA1, and the second black matrix portion 602 includes a plurality of first hollow holes 6021;

s141: manufacturing a color film layer 70 on a side of the black matrix layer 60 away from the first substrate 10, so that the color film layer 70 includes a first color film portion 701 and a second color film portion 702, the first color film portion 701 is located in the groove area NA1, the second color film portion 702 is located outside the groove area NA1, the second color film portion 702 includes a plurality of first color resistors 7021, and the first color resistors 7021 are located in the first hollow holes 6021;

s142: the protection layer 80 is formed on the side of the color film layer 70 away from the first substrate 10, such that the protection layer 80 covers the color film layer 70.

In the manufacturing method provided in this embodiment, before the third metal layer 50 is manufactured, the black matrix layer 60 and the color film layer 70 may be further manufactured on the first insulating layer 40, and covered and protected by the protection layer 80. That is, the display panel 000 manufactured in this embodiment may be a display panel adopting a technology of integrating a Color filter into an Array substrate (COA), that is, the first substrate 10 is provided with the thin film transistor Array layer 20 and also includes a Color resistor, and the COA structure can improve the aperture ratio of the panel and improve the display quality of the panel. The first black matrix part 601 and the first color film part 701 are also manufactured in the grooving area NA1 of the present embodiment, the black matrix layer 60 and the color film layer 70 which are only arranged above the planarization layer 30 in the prior art can be extended into the range of the grooving area NA1, so that the first black matrix part 601 and the first color film part 701 of the grooving area NA1 also play a role of raising the inner film layer of the grooving area NA1, and through the common cooperation with the first insulating layer 40, the step difference formed by the planarization layer 30 is further reduced, so that the conductive structure which may remain in the grooving area NA1 is closer to the exposure light source, and is more easily exposed, thereby further reducing the risk of short circuit of the line in the non-display area, and improving the product yield.

It can be understood that, in this embodiment, detailed structures of the first black matrix portion 601 and the second black matrix portion 602 of the black matrix layer 60 and the first color film portion 701 and the second color film portion 702 of the color film layer 70 are not repeated, and can be understood with reference to the embodiments corresponding to fig. 9 to fig. 14.

In some optional embodiments, please refer to fig. 42, where fig. 42 is a schematic structural diagram of a display device according to an embodiment of the present invention, and the display device 111 according to this embodiment includes the flexible display panel 000 according to the above embodiment of the present invention. The embodiment of fig. 42 only takes a mobile phone as an example to describe the display device 111, and it should be understood that the display device 111 provided in the embodiment of the present invention may be another display device 111 having a display function, such as a computer, a television, and a vehicle-mounted display device, and the present invention is not limited thereto. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention, and specific reference may be made to the specific description of the display panel 000 in the above embodiments, which is not described herein again.

As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, comprising: a display area and a non-display area disposed around the display area;

the display panel includes:

a first substrate;

a thin film transistor array layer on one side of the first substrate; the thin film transistor array layer at least comprises a first metal layer and a second metal layer which are insulated from each other;

the planarization layer is positioned on one side of the thin film transistor array layer, which is far away from the first substrate;

a first insulating layer located on one side of the planarization layer away from the first substrate;

the third metal layer is positioned on one side, far away from the first substrate, of the first insulating layer;

the non-display region includes a grooved region that does not include the planarization layer.

2. The display panel according to claim 1,

in a direction parallel to the plane of the first substrate, the groove area comprises a first area close to the display area;

the first region does not include the first insulating layer.

3. The display panel of claim 1, wherein the trenched region does not include a third metal layer.

4. The display panel according to claim 1, wherein the planarization layer includes a bottom surface facing a side of the first substrate in a direction perpendicular to a plane of the first substrate; in a direction parallel to the plane of the first substrate, the planarization layer comprises a side face facing the groove area; the bottom surface intersects the side surface and forms an included angle less than 90 degrees.

5. The display panel according to claim 1,

a black matrix layer, a color film layer and a protective layer are further arranged between the first insulating layer and the third metal layer, the black matrix layer is positioned on one side, far away from the first substrate, of the first insulating layer, the color film layer is positioned on one side, far away from the first substrate, of the black matrix layer, and the protective layer is positioned on one side, far away from the first substrate, of the color film layer;

the black matrix layer comprises a first black matrix part and a second black matrix part, the color film layer comprises a first color film part and a second color film part, the first black matrix part and the first color film part are positioned in the groove-digging area, and the second black matrix part and the second color film part are positioned outside the groove-digging area;

the second black matrix portion comprises a plurality of first hollowed holes, the second color film portion comprises a plurality of first color resistors, and the first color resistors are located in the first hollowed holes.

6. The display panel according to claim 5,

the first black matrix part comprises a plurality of second hollowed holes, the first color film part comprises a plurality of second color resistors, and the second color resistors are positioned in the second hollowed holes; and in the direction perpendicular to the plane of the first substrate, the thickness of the second color resistor is larger than that of the first color resistor.

7. The display panel according to claim 5,

the first black matrix portion is of a whole-surface structure in the groove digging area, the first color film portion comprises a plurality of third color resistors, and the third color resistors are located on one side, away from the first substrate, of the first black matrix portion in the direction perpendicular to the plane of the first substrate.

8. The display panel according to claim 5,

the first black matrix part and the first color film part are both of a whole-surface structure in the groove area, and the first color film part is positioned on one side of the first black matrix part, which is far away from the first substrate, in the direction perpendicular to the plane of the first substrate.

9. The display panel according to claim 8, wherein the first color film portion includes a plurality of color resist layers of different colors stacked in a direction perpendicular to a plane of the first substrate.

10. The display panel according to claim 1,

the grooving region comprises a metal part, and the metal part and the third metal layer are made of the same layer and the same material;

in the groove digging region, the display panel comprises a plurality of fan-out leads, one fan-out lead at least comprises a first subsegment, a second subsegment and a third subsegment, and two ends of the second subsegment are respectively and electrically connected with the first subsegment and the third subsegment;

the second subsegment is located in the first metal layer, and the first subsegment and the third subsegment are located in the second metal layer;

in the groove-digging area, in the direction parallel to the plane of the first substrate and along the arrangement direction of the first subsegments, the width of the metal part is D1, the distance between every two adjacent first subsegments is D2, and D1 is less than D2.

11. The display panel according to claim 10,

in the display area, the display panel comprises a plurality of signal lines, and the first subsegment is electrically connected with the signal lines through fanout lines; the fanout line is positioned in the non-display area outside the groove digging area;

in the groove area, the display panel comprises a plurality of conductive bonding pads, and the third subsection is electrically connected with the conductive bonding pads.

12. A method for manufacturing a display panel, the method being used for manufacturing the display panel according to any one of claims 1 to 11; the manufacturing method comprises the following steps:

providing a first substrate;

manufacturing a thin film transistor array layer on one side of the first substrate, so that the thin film transistor array layer at least comprises a first metal layer and a second metal layer which are insulated from each other;

manufacturing a planarization layer on one side of the thin film transistor array layer, which is far away from the first substrate;

etching the planarization layer in the non-display area to form a groove area, so that the groove area does not comprise the planarization layer;

manufacturing a first insulating layer on one side of the planarization layer, which is far away from the first substrate, so that the first insulating layer is located in the display area and the non-display area;

and manufacturing a third metal layer on one side of the first insulating layer far away from the first substrate.

13. The method according to claim 12, further comprising, after forming a third metal layer on a side of the first insulating layer remote from the first substrate:

etching the first insulating layer at least to ensure that the first region of the groove digging region does not comprise the first insulating layer; the first area is an area close to the display area in the groove area in a direction parallel to the plane of the first substrate.

14. The method according to claim 12, further comprising, after forming a third metal layer on a side of the first insulating layer remote from the first substrate:

exposing the third metal layer such that the trenched region does not include the third metal layer.

15. The method of manufacturing according to claim 12, wherein manufacturing a thin film transistor array layer on one side of the first substrate includes:

manufacturing the first metal layer and the second metal layer which are insulated from each other on one side of the first substrate, so that in the groove digging region, the display panel comprises a plurality of fan-out leads, one fan-out lead at least comprises a first subsection, a second subsection and a third subsection, and two ends of the second subsection are respectively and electrically connected with the first subsection and the third subsection; the second subsegment is located in the first metal layer, and the first subsegment and the third subsegment are located in the second metal layer.

16. The method according to claim 15, further comprising, after forming a third metal layer on a side of the first insulating layer remote from the first substrate:

exposing the third metal layer to enable the third metal layer to comprise a metal part in the groove digging region, wherein the width of the metal part is D1 along the arrangement direction of the first subsegments in the direction parallel to the plane of the first substrate, and the distance between every two adjacent first subsegments is D2, and D1 is less than D2.

17. The method of claim 12, wherein etching the planarization layer in the non-display area to form a trench area such that the trench area does not include the planarization layer comprises:

in the direction vertical to the plane of the first substrate, the etched planarization layer comprises a bottom surface facing one side of the first substrate; in a direction parallel to the plane of the first substrate, the etched planarization layer comprises a side face facing the groove area; the bottom surface intersects the side surface and forms an included angle less than 90 degrees.

18. The method of manufacturing according to claim 17,

manufacturing a planarization layer on one side of the thin film transistor array layer far away from the first substrate, wherein the planarization layer comprises:

manufacturing a first sublayer on one side, far away from the first substrate, of the thin film transistor array layer, etching the first sublayer in the non-display area, and enabling the etched first sublayer to comprise a first bottom surface facing one side of the first substrate in a direction perpendicular to the plane of the first substrate; in a direction parallel to the plane of the first substrate, enabling the etched first sublayer to comprise a first side face facing the groove area; the first bottom surface and the first side surface are intersected to form an included angle alpha 1;

manufacturing a second sub-layer on the side of the first sub-layer far away from the first substrate, so that the second sub-layer covers the first sub-layer;

etching the second sub-layer in the non-display area, wherein the second sub-layer after etching comprises a second bottom surface facing one side of the first substrate in a direction perpendicular to the plane of the first substrate; in a direction parallel to the plane of the first substrate, the etched second sublayer comprises a second side surface facing the groove area; the second bottom surface and the second side surface are intersected to form an included angle alpha 2;

wherein alpha 1 is more than alpha 2, and alpha 2 is less than 90 degrees.

19. The method of claim 12, further comprising, prior to forming the third metal layer:

manufacturing a black matrix layer on one side, far away from the first substrate, of the first insulating layer, so that the black matrix layer comprises a first black matrix part and a second black matrix part, the first black matrix part is located in the groove area, the second black matrix part is located outside the groove area, and the second black matrix part comprises a plurality of first hollow holes;

manufacturing a color film layer on one side of the black matrix layer, which is far away from the first substrate, so that the color film layer comprises a first color film part and a second color film part, the first color film part is positioned in the groove digging area, the second color film part is positioned outside the groove digging area, the second color film part comprises a plurality of first color resistors, and the first color resistors are positioned in the first hollow holes;

and manufacturing a protective layer on one side of the color film layer, which is far away from the first substrate, so that the protective layer covers the color film layer.

20. A display device characterized by comprising the display panel according to any one of claims 1 to 11.