CN106952835A - 半导体芯片与衬底连接的方法以及制造电子组件的方法 - Google Patents

半导体芯片与衬底连接的方法以及制造电子组件的方法 Download PDF

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CN106952835A
CN106952835A CN201610900489.7A CN201610900489A CN106952835A CN 106952835 A CN106952835 A CN 106952835A CN 201610900489 A CN201610900489 A CN 201610900489A CN 106952835 A CN106952835 A CN 106952835A
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metallization layer
contact metallization
substrate
layer
chip
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CN106952835B (zh
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G·特里奇伦加拉简
C·施塔尔胡特
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明一方面涉及一种用于使半导体芯片(1)与衬底(2)连接的方法。半导体芯片(1)具有带下侧(10b)的半导体本体(10)，在所述下侧上施加有下部的芯片金属化层(12)。衬底(2)具有金属表面(2t)。在下部的芯片金属化层(12)上生成第一接触金属化层(31)，并且在衬底(2)的金属表面(2t)上生成第二接触金属化层(32)。在压紧持续时间内将半导体芯片(1)和衬底(2)彼此压合，以使得第一接触金属化层(31)和第二接触金属化层(32)直接地并且平面地彼此贴靠。将第一接触金属化层(31)在压紧持续时间期间持续地保持在小于第一接触金属化层(31)的熔化温度的温度上。相应地将第二接触金属化层(32)在压紧持续时间期间持续地保持在小于第二接触金属化层(32)的熔化温度的温度上。在彼此压合之后，第一接触金属化层(31)和第二接触金属化层(32)具有小于1000nm的总层厚度(d3132)。

Description

半导体芯片与衬底连接的方法以及制造电子组件的方法
技术领域
本发明涉及半导体芯片与衬底的材料配合的连接。
背景技术
通常这种连接借助于焊料、已烧结的金属粉末或胶粘剂来建立。然而建立这种公知的材料配合的连接是耗费的，因为必须将连接介质、即焊料、金属粉末或胶粘剂施加到半导体芯片或衬底上。为此，需要多个单个步骤。此外存在下述的危害，连接介质污染环境。不期望地喷溅、散失或脱落的导电连接介质可以例如导致待制造的电子组件短路。
发明内容
本发明的目的在于，提供一种简单的和成本低廉的用于使半导体芯片与衬底材料配合地连接的方法，以及一种用于改善的用于制造电子组件的方法。该目的通过一种根据权利要求1所述的用于使半导体芯片与衬底连接的方法以及通过一种根据权利要求17所述的用于制造电子组件的方法实现。本发明的构型和扩展方案是从属权利要求的内容。
第一方面涉及半导体芯片与衬底的连接。半导体芯片具有带下侧的半导体本体，在所述下侧上施加有下部的芯片金属化层。衬底具有金属表面。在下部的芯片金属化层上生成第一接触金属化层，并且在衬底的金属表面上生成第二接触金属化层。在压紧持续时间内这样将半导体芯片和衬底彼此压合，以使得第一接触金属化层和第二接触金属化层直接地并且平面地彼此贴靠。将第一接触金属化层在压紧持续时间期间持续地保持在小于第一接触金属化层的熔化温度的温度上。相应地将第二接触金属化层在压紧持续时间期间持续地保持在小于第二接触金属化层的熔化温度的温度上。在彼此压合之后，第一接触金属化层和第二接触金属化层具有小于1000nm的总层厚度。
第二方面涉及电子组件的制造。在此，通过根据第一方面的方法使下述的半导体芯片与衬底的金属表面连接，所述半导体芯片具有半导体本体，所述半导体具有下侧和上侧，在所述下侧上施加有下部的芯片金属化层，在所述上侧上施加有上部的芯片金属化层。此外，将导电的连接元件直接键合在上部的芯片金属化层处。
附图说明
下面根据实施例参考附图说明本发明。附图中的图示不是按比例的。附图中：
图1示出部分完成的电子组件的横截面。
图2A至2D示出用于制造一个电子组件的方法的不同的步骤。
图3A至3D示出用于制造一个另外的电子组件的方法的不同的步骤。
图4A至4B示出用于在晶片复合体中的多个半导体芯片中生成第一接触金属化层的方法的不同的步骤。
图5示出半导体芯片和衬底表面的放大图，所述衬底表面分别相应于图2B和3B设置有一个接触金属化层。
附图中的图示不是按比例的。如果没有他说明，则根据不同的实施例所述的特征和/或方法步骤可以彼此组合。
具体实施方式
图1示出部分完成的具有半导体芯片1的电子组件的横截面，所述半导体芯片材料配合地与衬底2的导电的金属表面2t连接。图2A示出在建立其材料配合的连接之前所提供的半导体芯片1和所提供的衬底2。
如同在图2A中所示的那样，半导体芯片1具有带上侧10t和下侧10b的半导体本体10。上侧10t和下侧10b形成半导体本体10的彼此相对的侧。在下侧10b上施加一个下部的芯片金属化层12。此外，可以在上侧10t上可选地施加一个上部的芯片金属化层11。下部的芯片金属化层12和上部的芯片金属化层11(如存在)用于半导体芯片1的外部电接触。
半导体芯片1可以例如是二极管或可控的半导体开关例如IGBT(Insulated GateBipolar Transistor，绝缘栅双极型晶体管)、MOSFET(Metal Oxide Semiconductor FieldEffect Transistor，金属氧化物半导体场效应晶体管)、晶闸管(例如GTO晶闸管；GTO＝Gate Turn Off，栅极关断)、结型场效应晶体管(JEFT＝Junction Field EffectTransistor)、例如也作为HEMT(High Electron Mobility Transistor，高电子迁移率晶体管)。
半导体芯片1能够可选地构造为所谓的垂直的半导体芯片，所述垂直的半导体芯片在其朝向衬底2的侧上材料配合地并且导电地与衬底2的金属表面2t连接，从而在电子组件工作时负载电流可以通过半导体芯片1从上部的芯片金属化层11通过半导体本体10和下部的芯片金属化层12流到金属表面2t。
上部的和下部的芯片金属化层11，12可以根据元件的类型例如是源极和漏极金属化层，或者是漏极和源极金属化层，或者是集电极和发射极金属化层，或者是发射极和集电极金属化层，或者是阳极和阴极金属化层，或者是阴极和阳极金属化层。
衬底2具有至少一个金属表面2t。如同在本实例中所示的那样，衬底2能够可选地具有一个介电的绝缘载体20，所述绝缘载体构造为平面的板，并且所述介电绝缘载体具有上部的主面和与其相对的下部的主面。在绝缘载体20的上部的主面上施加一个上部的衬底金属化层21，所述上部的衬底金属化层能够可选地相对于彼此隔开间距的印制导线和/或导电面211，212结构化。此外，在绝缘载体20的下部的主面上施加一个可选的下部的衬底金属化层22。下部的衬底金属化层22是微结构化的，然而替代地其也可以是结构化的。衬底2的导电的金属表面2t由上部的衬底金属化层21、在此例如由印制导线和/或导电面211，212形成。
衬底金属化层21和22与绝缘载体20固定地、平面地并且材料配合地连接。上部的衬底金属化层21特别是可以在其整个的朝向绝缘载体20的侧上固定地并且材料配合地与绝缘载体20连接。相应地，下部的衬底金属化层22也可以在其整个的朝向绝缘载体20的侧上固定地并且材料配合地与绝缘载体20连接。
绝缘载体20是电绝缘的。所述绝缘载体例如具有陶瓷或者由陶瓷构成。适合的陶瓷例如是氮化铝(AlN)、氧化铝(Al2O3)，氮化硅(Si3N4)、碳化硅(SiC)或氧化铍(BeO)或者其他介电陶瓷。上部的衬底金属化层21和下部的衬底金属化层22(如存在)可以例如由铜、铜合金、铝或铝合金构成或者具有这些金属中的一种。然而其他包含良好地导电的金属的合金同样可以被使用。此外，上部的衬底金属化层21和下部的衬底金属化层22(如存在)分别具有两个或更多的子层，其中每个子层由一种金属或一种金属合金构成。
根据一个实施方案，衬底2可以是DCB衬底(DCB＝direct copper bonded，直接铜键合)，其中，上部的衬底金属化层21和下部的衬底金属化层22(如存在)被制造，其方式是，预制成的表面被氧化的铜箔通过DCB过程与例如由氧化铝构成的陶瓷绝缘载体20连接。
为了如同在图1中的结果中所示的那样使半导体芯片1材料配合地并且导电地与衬底2连接，在下部的芯片金属化层12上、即在其背离半导体本体10的侧上生成第一接触金属化层31。此外，在衬底2的金属表面2t上生成第二接触金属化层32。如果衬底2具有介电绝缘载体20，则第二接触金属化层32在上部的衬底金属化层21的背离介电绝缘载体20的侧上被生成。图2B示出具有第一接触金属化层31的半导体芯片1和具有第二接触金属化层32的衬底2。
接着如同在图2C中所示的那样将半导体芯片1和衬底2这样按压和在一起，使得第一接触金属化层31和第二接触金属化层32直接地并且平面地彼此贴靠在一个共同的界面30上。界面30的尺寸原则上是任意的。然而所述界面在构造为功率半导体元件的半导体芯片1的情况下是极大面积的、例如为至少1mm2或者甚至至少10mm2。界面30可以特别是构造为闭合的连续的面。
所述彼此压合可以借助于压力机进行，所述压力机具有上压件51和下压件52，在所述上压件和下压件之间将设置有第一接触金属化层31的半导体芯片1和设置有第二接触金属化层32的衬底2以其接触金属化层31和32直接贴靠地压紧。
通过彼此压合在界面30的区域中生成第一接触金属化层31和第二接触金属化层32之间并且由此也在半导体芯片1和衬底2之间的材料配合的和导电的连接。当不再存在半导体芯片1和衬底2之间的压力p时，所述材料配合的和导电的连接也存在。
可选地也可以进一步加工半导体芯片1和衬底2之间的如此形成的材料配合的复合体。为此，图2D示出一个实例。正如在此示意性所示的那样，导电的连接元件4、例如粘合线或平坦的细带在形成第一粘合连接41的情况下直接粘接到上部的芯片金属化层11上。可选地，导电的连接元件4在形成不同于第一粘合连接41的第二粘合连接42的情况下直接与要制造的电子组件的一个任意其他的不同于上部的芯片金属化层11的元件连接。根据所示的实例，第二粘合连接42在连接元件4和构造在上部的衬底金属化层21中的印制导线或导电面212之间形成。印制导线或导电面212与同样构造在上部的衬底金属化层21中的导电面211隔开间距，在该导电面上施加第二接触金属化层32。
在根据图2A至2D的实例中，衬底2构造为绝缘衬底，所述绝缘衬底具有绝缘载体20和至少一个上部的衬底金属化层21。与此不同地，衬底2也可以例如构造为金属引线框架(“Leadframe”)，这根据图3A至3D示出。除了衬底2的其他结构外，以如同在根据图2A至2D所述的方法那样相同的方式实现所述方法。
所提供的半导体芯片1可以是如同前面参考图1和2A至2D已述的那样的半导体芯片1(图3A)。所提供的衬底2(图3A)是具有金属表面2t的金属引线框架(“Leadframe”)。
如同参考图2B所述的那样，在下部的芯片金属化层12上、即在其背离半导体本体10的侧上生成第一接触金属化层31(图3B)。此外，同样如同参考图2B所述的那样，在衬底2的金属表面2t上生成第二接触金属化层32(图3B)。
接着如同在图3C中所示的那样将半导体芯片1和衬底2这样压和在一起，使得第一接触金属化层31和第二接触金属化层32直接地并且平面地彼此贴靠在一个共同的界面30上。所述压和在一起能够以如同参考图2C所述的那样相同的方式进行。
可选地可以进一步加工半导体芯片1和衬底2之间的在压紧之后形成的材料配合的复合体。如同在图3D中示意性所示的那样，导电的连接元件4、例如粘合线或平坦的细带在形成第一粘合连接41的情况下直接粘接到上部的芯片金属化层11上。可选地，导电的连接元件4在形成不同于第一粘合连接41的第二粘合连接42的情况下直接与要制造的电子组件的一个任意其他的不同于上部的芯片金属化层11的导电元件5(例如主动或被动电子元件、或者电连接导体)连接。与在根据图2D的实例中类似地，第二粘合连接42也可以在连接元件4和所述不同于上部的芯片金属化层11的导电元件5之间被建立，也就是说，导电元件5不必必需如同在图2D中所示的那样是上部的衬底金属化层21的印制导线或导电面。
如同根据前述附图(参见图2A和2B以及3A和3B)所示的那样，在单个的半导体芯片1中，第一接触金属化层31的生成能在半导体芯片1上实现。然而同样可能的是，第一接触金属化层31通过以下方式生成，当该半导体芯片还与其他结构相同的或结构不相同的半导体芯片1一起处于晶片复合体中时，所述第一接触金属化层被施加在该半导体芯片1上。下面这根据图4A和4B来说明。如同在图4A中示意性所示的那样，半导体晶片100具有用于多个结构相同的或结构不相同的半导体芯片1的半导体本体10。接着可以在半导体晶片100上施加一个上部的晶片金属化层110和一个下部的晶片金属化层120。此外，将一个另外的金属化层310施加到下部的晶片金属化层120的背离半导体晶片100的侧上，这结果在图4A中示出。虚线示出之后从哪里将还处于晶片复合体中的半导体芯片1分开。在图4B中右边示出两个分开的半导体芯片1，并且右边示出剩余的包含还未分开的半导体芯片1的晶片复合体。
所述分开的半导体芯片1中的每个半导体芯片可以用于根据图1，2A至2D和3A至3D所述的方法。
在所述分开的半导体芯片1中，上部的芯片金属化层11的材料和厚度相应于上部的晶片金属化层110的材料和厚度，下部的芯片金属化层12的材料和厚度相应于下部的晶片金属化层120的材料和厚度，并且另外的晶片金属化层310的材料和厚度相应于第一接触金属化层31的材料和厚度。
与此类似地，在衬底2的金属表面2t上生成第二接触金属化层32在一个单个的衬底2中进行，然而或者在下述状态中进行，衬底2在使用(即连接)两个或更多个结构相同的或结构不相同的基层的情况下处于所述状态中。对使用的衬底2的分开可以在将第二接触金属化层32施加到衬底2上之后进行。
图5再次示出根据图2B或3B的布置的放大的区段。在此示出下部的芯片金属化层12的层厚度d12、第一接触金属化层31的层厚度d31以及第二接触金属化层32的层厚度d32。
第一接触金属化层31的层厚度d31可以选择为非常小的，该层厚度可以例如选择为小于或等于1000nm或者甚至小于或等于500nm。
与此无关地，第二接触金属化层32的层厚度d32可以选择为非常小的，该层厚度可以例如选择为小于或等于1000nm或者甚至小于或等于500nm。
同样与此无关地，下部的芯片金属化层12的层厚度d12可以例如选择为大于或等于400nm。
在将半导体芯片1和衬底2彼此压合之后(即在半导体芯片1和衬底2之间完成的材料配合的连接的情况下)具有第一接触金属化层31和第二接触金属化层32的总厚度d3132可以是非常小的，例如小于1000nm或者甚至小于400nm。
此外，在第一和第二接触金属化层31，32在其生成之后并且在彼此压合之前所具有的厚度d31，d32的总和d31+d32与其在彼此压合之后所具有的总层厚度d3132之间的差值d31+d32-d3132小于200nm。在此，所述差值可以大于零，这意味着接触金属化层31，32通过彼此压合而塑性变形。然而所述变形仅仅是非常微小的。
将半导体芯片1和衬底2彼此压合(图2c和图3C)可以这样进行，使得半导体芯片1和衬底2在压紧持续时间期间不间断地以大于至少35Mpa或者甚至至少50Mpa的最小压力的压力被彼此压合。所述方法已经可以在非常短的压紧持续时间、例如小于2分钟内应用。
在压紧期间，特别是在压紧持续时间期间，第一接触金属化层31和第二接触金属化层32持续地保持在至少300℃的温度上。此外，第一接触金属化层31和第二接触金属化层32在压紧持续时间期间持续地保持在至少250℃的温度上。
此外，第一接触金属化层31在压紧持续时间期间持续地保持在小于第一接触金属化层31的熔化温度的温度上，并且第二接触金属化层32在压紧持续时间期间持续地保持在小于第二接触金属化层32的熔化温度的温度上。
例如恰好一种金属或者一种均匀的合金适合作为用于第一接触金属化层31的材料。第一接触金属化层31特别是由贵金属构成或者具有一种贵金属(例如金、银、铂、钌、锇、铑、铱)。然而原则上也可以使用呈纯粹形式的或呈合金形式的半贵金属或非贵金属(例如铝或铝合金)。
与用于第一接触金属化层31的材料无关地，例如恰好一种金属或者一种均匀的合金适合作为用于第二接触金属化层32的材料。第二接触金属化层32特别是由贵金属构成或者具有一种贵金属(例如金、银、铂、钌、锇、铑、铱)。然而原则上也可以使用呈纯粹形式的或呈合金形式的半贵金属或非贵金属(例如铝或铝合金)。
可选地，第一接触金属化层31和第二接触金属化层32由相同的材料构成或者相同的均匀的合金构成。
在下部的芯片金属化层12上生成第一接触金属化层31并且在衬底2的导电表面2t上生成第二接触金属化层32可以分别借助于一种下述的沉积方法进行，在所述沉积方法中，第一接触金属化层31和第二接触金属化层32不是作为预制的层被施加到下部的芯片金属化层12或衬底2的导电表面2t上，而是通过使接触金属化层31，32首先在切割过程期间形成(即连续地或接连地构造)。适合的沉积方法例如是喷镀、物理气相沉积(PVD＝physicalvapor deposition)、化学气相沉积(CVD＝chemical vapor deposition)、无电流沉积或电镀沉积。相应地也适用于在晶片100上生成另外的金属化层310(图4A)。通过沉积生成的金属化层31，32，310是非多孔的，正如例如在传统的烧结连接方法中所使用的银粉末层中那样是这种情况。因此，金属化层31，32，310构造为均匀的层，所述均匀的层不由被挤压的粉末构成。金属化层31，32，310构造为连续的不间断的层。
在所有情况中，所述沉积在使用掩模的情况下掩盖地进行，在所述掩模的开口中已沉积的材料直接在下部的芯片金属化层12(或下部的晶片金属化层120)上或者在衬底2的导电表面2t上增长。
然而同样可能的是不设置掩模地进行，从而已沉积的材料形成闭合的连续的层，所述层随后以公知的方式在使用掩模的情况下(例如摄影平板地)结构化。
可理解的是，一方面在下部的芯片金属化层12上生成第一接触金属化层31或者在下部的晶片金属化层120上生成另外的金属化层310并且另一方面在衬底2的导电表面2t上生成第二接触金属化层32可以根据相同的或不同的沉积方法以任意组合的形式进行。
在试验中实现了半导体芯片1和构造为DCB衬底的衬底2之间材料配合的连接的突出的稳定性。分别将黄金用作第一接触金属化层31和第二接触金属化层32的材料。接触金属化层31和32的生成分别通过喷镀(喷镀持续时间：4分钟；喷镀气体：氩气)。实现的层厚度d31和d32分别为400nm。压紧持续时间为2分钟，压力为55Mpa，并且总界面30为50mm2。在随后实施的弯曲试验中表明在半导体芯片1和构造为DCB衬底2之间无分层。

Claims (17)

1.一种用于使半导体芯片(1)与衬底(2)连接的方法，所述半导体芯片具有带下侧(10b)的半导体本体(10)，在所述下侧上施加有下部的芯片金属化层(12)，所述衬底(2)具有金属表面(2t)，其中，所述方法包括：
在所述下部的芯片金属化层(12)上生成第一接触金属化层(31)；
在所述衬底(2)的金属表面(2t)上生成第二接触金属化层(32)；
将所述半导体芯片(1)和所述衬底(2)彼此压合压紧持续时间内，以使得所述第一接触金属化层(31)和所述第二接触金属化层(32)直接地并且平面地彼此贴靠，其中，
在所述压紧持续时间期间将所述第一接触金属化层(31)持续地保持在小于所述第一接触金属化层(31)的熔化温度的温度；
在所述压紧持续时间期间将所述第二接触金属化层(32)持续地保持在小于所述第二接触金属化层(32)的熔化温度的温度；以及
所述第一接触金属化层(31)和所述第二接触金属化层(32)在彼此压合之后所具有的总层厚度(d3132)小于1000nm。
2.根据权利要求1所述的方法，其中，所生成的第一接触金属化层(31)在彼此压合之前具有小于400nm的层厚度(d31)。
3.根据权利要求1或2所述的方法，其中，所述第一接触金属化层(31)由恰好一种金属或一种均质的合金构成。
4.根据前述权利要求中任一项所述的方法，其中，所述第一接触金属化层(31)由不锈钢构成或者具有不锈钢。
5.根据前述权利要求中任一项所述的方法，其中，在生成所述第一接触金属化层(31)时借助于沉积方法实现。
6.根据前述权利要求中任一项所述的方法，其中，所生成的第二接触金属化层(32)在彼此压合之前具有小于400nm的层厚度(d32)。
7.根据前述权利要求中任一项所述的方法，其中，所述第二接触金属化层(32)由恰好一种金属或一种均质的合金构成。
8.根据前述权利要求中任一项所述的方法，其中，所述第二接触金属化层(32)由不锈钢构成或者具有不锈钢。
9.根据前述权利要求中任一项所述的方法，其中，在生成所述第二接触金属化层(32)时借助于沉积方法实现。
10.根据前述权利要求中任一项所述的方法，其中，在所述压紧持续时间期间所述半导体芯片(1)和所述衬底(2)不间断地以至少35Mpa或至少50Mpa的压力(p)被彼此压合。
11.根据权利要求10所述的方法，其中，在所述压紧持续时间期间所述第一接触金属化层(31)和所述第二接触金属化层(32)具有至少250℃的温度。
12.根据前述权利要求中任一项所述的方法，其中，在所述压紧持续时间期间所述第一接触金属化层(31)和所述第二接触金属化层(32)具有至少1mm2或至少10mm2的共同的界面(30)。
13.根据前述权利要求中任一项所述的方法，其中，所述第一接触金属化层(31)和所述第二接触金属化层(32)在彼此压合之后所具有的总层厚度(d3132)小于400nm。
14.根据前述权利要求中任一项所述的方法，其中，在所述第一接触金属化层(31)和所述第二接触金属化层(32)生成之后并且在彼此压合之前所具有的厚度(d31，d32)的总和(d31+d32)与它们在彼此压合之后所具有的总层厚度(d3132)之间的差值(d31+d32-d3132)小于200nm。
15.根据前述权利要求中任一项所述的方法，其中，
所述衬底(2)具有介电绝缘载体(10)，所述介电绝缘载体具有上部的衬底金属化层(21)；以及
所述衬底(2)的金属表面(2t)由所述衬底金属化层(21)形成。
16.根据权利要求1至14中任一项所述的方法，其中，
所述衬底(2)构造为金属引线框架；以及
所述衬底(2)的金属表面(2t)由金属引线框架形成。
17.一种用于制造电子组件的方法，该方法具有：
根据前述权利要求中任一项所述的方法使半导体芯片(1)与衬底(2)的金属表面(2t)连接，所述半导体芯片具有半导体本体(10)，所述半导体具有下侧(10b)以及上侧(10t)，在所述下侧上施加有下部的芯片金属化层(12)，在所述上侧上施加有上部的芯片金属化层(11)；并且
将导电的连接元件(4)直接键合在所述上部的芯片金属化层(11)处。
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