CN106952662B - The memory device of memory device method for refreshing and adjustable refresh operation frequency - Google Patents
The memory device of memory device method for refreshing and adjustable refresh operation frequency Download PDFInfo
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- CN106952662B CN106952662B CN201610009723.7A CN201610009723A CN106952662B CN 106952662 B CN106952662 B CN 106952662B CN 201610009723 A CN201610009723 A CN 201610009723A CN 106952662 B CN106952662 B CN 106952662B
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
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Abstract
The memory device of a kind of memory device method for refreshing and adjustable refresh operation frequency, a memory array of one of semiconductor well region suitable for memory device.Method for refreshing of the invention includes the following steps.Record the erasing pulse number and/or erasing voltage level in each erasing instruction.Judge non-selected multiple sectors.Judge whether any erasing pulse number or any erasing voltage level are more than or equal to a predetermined value.When erasing pulse number or erasing voltage level are more than or equal to predetermined value, refresh non-selected sector using the second refresh operation frequency.When erasing pulse number or erasing voltage level are less than predetermined value, refresh non-selected sector using the first refresh operation frequency.First refresh operation frequency is less than the second refresh operation frequency.
Description
Technical field
The invention relates to memory device method for refreshing and the memory devices of adjustable refresh operation frequency, especially
Relate to a kind of method for refreshing of the memory device of adjustable refresh operation frequency.
Background technique
In general, flash memory (such as NOR flash memory) includes multiple storage members, these storage members are divided into multiple sectors
(sectors).By sequence instead or for type flash memory (SPI NOR flash), a sector can have 4096 bytes (4Kbyte)
Storage member.In order to reduce the area of flash memory, multiple sectors can share a semiconductor well region.Flash memory can receive erasing instruction with
Programming instruction.Erasing instruction is so that the storage member selected is in lower critical voltage to wipe the storage selected member
State；Programming instruction is so that the storage member selected is in higher threshold voltage state to program the storage selected member.
Wherein, erasing instruction includes pre-programmed (pre-program), erasing and rear programming (post-program) operation, and is wiped
Minimum unit be sector.In practice, according to the unit of erasing, erasing instruction can be divided into sector erasing instruction, memory block erasing
Instruction and chip erasing instruction, respectively to wipe a sector, a memory block (block) and entire chip
(chip).For example, when flash memory receives sector erasing instruction, one of sector can be selected for erasing behaviour
Make.At this point, a negative voltage those of can be applied in the sector selected the control grid of the transistor of storage member, and a positive electricity
Pressure is then applied to shared semiconductor well region.Whereby, the electronics for being stored in floating gate (floating gate) is driven to shift to semiconductor
Well region those of makes in the sector selected storage member in lower critical voltage shape to reduce the critical voltage of transistor
State.
The manufacturer of flash memory must assure that the erase-write cycle characteristics of flash memory, also that is, even if executing repeatedly to memory
Problem such as changing electrical characteristic will not occur for erasing and write instruction.Wherein, an erase-write circulation is to quilt
The storage member of selection executes primary erasing instruction and primary programming instruction.However, with the increasing of erase-write cycle-index
Add, trap area will be generated in the oxide layer of channel, electronics will be easier to be trapped in the oxide layer of channel, cause to reach set by storage member
Fixed critical voltage becomes more difficult, needs to increase erasing pulse and the time needed for completing erasing is made to become longer, this
A phenomenon is known as storing the aging of member.It, can be by the time required to increasing erasing voltage to reduce erasing in order to up to specification.
However, the semiconductor well region due to being applied positive voltage includes the fan selected when executing multiple erasing operation
Area and non-selected sector are stored up so that those of non-selected sector programming stores first (programmed cell)
The electronics deposited is influenced by the positive voltage applied and is lost, and leads to those of non-selected sector programming storage member
The critical voltage of transistor declines.In this way, be the storage member for being programmed (storage " 0 ") originally in non-selected sector
It will be identified that the storage member for being wiped free of (storage " 1 ").In addition, these are non-selected in during executing erasing instruction
Storage member may also suffer from executing Drain Disturbance caused by pre-programmed and rear programming.
Therefore, flash memory needs execute refresh operation after erasing instruction is finished, by non-selected sector Central Plains
This critical voltage value for being disturbed storage member in programming state, which is drawn high, is restored back to original higher critical voltage value.So
And it executes refresh operation and then increases the sector erasing time of flash memory, and will cause Drain Disturbance.
For example, non-selected all memory blocks are divided into multiple groups by a kind of existing refresh operation, and are wrapped
Include following steps.In step 1, sector erasing instruction at least once is executed.In step 2, refresh first group not by
The memory block of selection, and return to step 1.In step 3, refresh second group of non-selected memory block, and returns to
Step 1.And so on, the non-selected memory block until refreshing last group.In another existing refresh operation
In, it is to refresh all non-selected memory blocks after executing sector erasing instruction at least once.
However, existing method for refreshing bulk is all to refresh operating frequency operation with fixed, refresh operation frequency is defined as
The inverse of primary corresponding erasing instruction number is refreshed in all sectors, can be represented mathematically as: 1/ (X*N/N '),
In it is every to execute X erasing instruction be refresh operation of implementation, N is the number of sectors of common semiconductor well region, and N ' is to select every time
Do the number of sectors refreshed.This fixes refreshing operating frequency and must take into account with depositing after erase-write cycle-index increase
The aging phenomenon of Chu Yuan, thus using high refresh operation frequency, such as one erasing instruction of every execution it is necessary to refresh it is all not
The sector selected, to smoothly complete the erasing of aging storage member.However, higher refresh operation frequency may cause more seriously
Drain Disturbance, and required time will be more.Furthermore for not aged storage member, it will make to brush using high refreshing frequency
It is new less efficient.Control needs to propose the new memory device of one kind in the range of setting the time required in order to wipe
Method for refreshing.
Summary of the invention
Therefore, the present invention provides a kind of method for refreshing of memory device, can be according to the storage member of memory device
Degree of aging executes the frequency of refresh operation to adjust.Whereby, the present invention can improve refresh operation efficiency, and it is dry to reduce drain electrode
It disturbs.
One embodiment of the invention provides a kind of method for refreshing of memory device, wherein one suitable for memory device
One memory array of a semiconductor well region.This method for refreshing is the following steps are included: record the erasing arteries and veins in each erasing instruction
Jig frequency number and/or erasing voltage level；Judge non-selected multiple sectors；Judge any erasing pulse number or any erasing
Whether voltage level is more than or equal to a predetermined value；When any erasing pulse number or erasing voltage level are more than or equal to predetermined value
When, refresh non-selected sector using the second refresh operation frequency；And when erasing pulse number or erasing voltage level are small
When predetermined value, refresh non-selected sector using the first refresh operation frequency.First refresh operation frequency is less than the second brush
New operating frequency.
One embodiment of the invention provides the memory device of adjustable refresh operation frequency comprising memory array,
Decoder, erased conditions logger and buffer.Memory array includes multiple sectors, is set to semiconductor well region.Solution
Code device receives an address signal.Decoder provides at least one erasing according to the one of them of the multiple sectors of address signal behavior
The sector that pulse and its corresponding erasing voltage level are extremely selected.Erased conditions logger records the wiping in each erasing instruction
Except pulse number and/or erasing voltage level.Buffer stores one first refresh operation frequency and one second refresh operation frequency.
First refresh operation frequency is less than the second refresh operation frequency.When erasing pulse number or erasing voltage level are more than or equal to one in advance
When definite value, refresh the non-selected sector using the second refresh operation frequency.When erasing pulse number or erasing voltage position
When standard is less than predetermined value, refresh non-selected sector using the first refresh operation frequency.
The present invention adjusts refreshing frequency according to erasing pulse number used in each erasing instruction and/or erasing voltage level
Rate, when erasing pulse number and/or erasing voltage level are more than or equal to predetermined value, i.e. quickening refresh operation frequency.Refresh behaviour
Working frequency can record in buffer.Whereby, the present invention can be by control the time required to erasing in the range of setting, to promote storage
The operational paradigm of device device.
Detailed description of the invention
Fig. 1 shows memory devices according to an embodiment of the invention.
Fig. 2 indicates the step flow diagram of the method for refreshing of memory device according to an embodiment of the invention.
Fig. 3 indicates the step flow diagram of the method for refreshing of memory device according to another embodiment of the present invention.
Fig. 4 indicates the step flow diagram of the method for refreshing of the memory device of another embodiment according to the present invention.
Fig. 5 indicates the step flow diagram of the method for refreshing of memory device according to yet another embodiment of the invention.
Drawing reference numeral:
1~memory device；
10~memory array；
11~decoder；
12~write-in-reading circuit；
13~erased conditions logger；
14~buffer；
100~storage member；
ADD~address signal；
NERASE~erasing pulse number；
S0~SN~sector；
S20 ... S24~method and step；
S30 ... S35~method and step；
S40 ... S45~method and step；
S50 ... S57~method and step；
VERASE~erasing voltage level.
Specific embodiment
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, a preferred embodiment is cited below particularly, and match
Institute's accompanying drawings are closed, are described in detail below.
Fig. 1 shows memory devices according to an embodiment of the invention.Refering to fig. 1, memory device 1 includes memory array
Column 10, decoder 11, write-in-reading circuit 12, erased conditions logger 13 and buffer 14.Memory array 10 includes
It is configured to multiple storage members 100 of multiple rows Yu multiple column, and the first 100 common semiconductor well regions of these multiple storages.These are deposited
Storage member 100 is divided into multiple sectors (sector) S0~SN.Each sector S0~SN may include at least one storage member column.Decoding
Device 11 receives address signal ADD, according to address signal ADD it can be seen which storage member 100 will be read out, be written or
Erasing operation.Write-in-reading circuit 12 cooperates decoder 11 to operate, according to the knot of 11 decoded address signals ADD of decoder
Fruit is written or is read to the storage member 100 selected.Erased conditions logger 13 is to record in each erasing instruction
Erasing pulse times NERASEAnd/or erasing voltage level VERASE.Buffer 14 is to store at least two refresh operation frequencies.
Refresh operation frequency is the inverse that primary corresponding erasing instruction number is refreshed in all sectors, can be indicated with mathematical expression
Are as follows: 1/ (X*N/N '), wherein every to execute an X erasing instruction i.e. refresh operation of implementation, N is the fan of common semiconductor well region
Area's number, N ' are that the number of sectors refreshed is done in each choosing.In embodiments of the present invention, memory device 1 can be a flash memory.It needs
It is noted that memory device can have multiple semiconductor well regions, and each is partly in the other embodiments that Yu Yiwei is painted
Conductor well region corresponds to a memory array.
The method for refreshing of memory device 1 of the invention is suitable for one of semiconductor well region of memory device 1
Memory array 10 executes after erasing instruction at least once.Specifically, refer to whenever memory device 1 executes an erasing
When enabling, decoder 11 selects the one of them of sector S0~SN according to corresponding address signal ADD.At this point, decoder 11 mentions
For the control of the transistor of all storage members 100 of an at least erasing pulse and its corresponding voltage level into the sector selected
Grid processed wipes the sector selected whereby.After each erasing instruction is finished, remembered by erased conditions logger 13
Record erasing pulse number and/or erasing voltage level.It should be noted that being chosen as erasing instruction executes the increase of number
The storage member selected can gradually aging, need by the time required to increasing erasing pulse or erasing voltage to reduce erasing, therefore wipe
Except pulse number can react the ageing state of the storage member selected with the increase of erasing voltage level.
Fig. 2 indicates the step flow diagram of the method for refreshing of memory device according to an embodiment of the invention.Yu Bu
In rapid S20, the erasing pulse number and/or erasing voltage level in each erasing instruction are recorded.Decoder 11 is wiped according to one
Except the corresponding address signal ADD of instruction, those of unselected sector (step S21) is judged.Due to sector S0~SN's
These storage members 100 share a semiconductor well region, and when executing erasing operation, it is applied to the positive electricity of common semiconductor well region
Pressure may be such that the electronics stored by the storage member of non-selected sector is lost, and result in the number in non-selected sector
According to being interfered.Therefore, after sector of the memory device 1 to corresponding address signal ADD executes erasing instruction, memory device
1 pair of those of unselected sector executes method for refreshing of the invention, to restore to be stored in data in non-selected sector.It lifts
For example, the address signal ADD corresponding to the erasing instruction is sector S0, and sector S0 is selected to execute erasing, and not
The method for refreshing of memory device 1 of the invention is performed in the sector S1-SN selected, to refresh depositing in the S1-SN of sector
Data stored by Chu Yuan.
Then, the erasing pulse number or erasing voltage position that memory device 1 is recorded according to erased conditions logger 13
Standard, judges whether any erasing pulse number or erasing voltage level are more than or equal to a predetermined value (step S22).As step S22
Result be it is yes, i.e., when any erasing pulse number or erasing voltage level are more than or equal to above-mentioned predetermined value, use second
Refresh operation frequency refreshes those of non-selected sector and stores first (step S23).When the result of step S22 be it is no, that is, work as
All erasing pulse numbers or erasing voltage level be less than above-mentioned predetermined value when, using the first refresh operation frequency refresh not by
Those of sector of selection storage member, and the first refresh operation frequency is less than the second refresh operation frequency (step S24).
Fig. 3 indicates the step flow diagram of the method for refreshing of memory device according to another embodiment of the present invention.?
In the present embodiment, after the sector erasing instruction of Yu Zhihang fixed quantity, primary refresh is executed.Refresh operation frequency is proportional to one
The quantity for the non-selected sector refreshed in secondary refresh operation.For example, memory device 1 is to corresponding address signal
The sector of ADD executes erasing instruction, and erasing instruction executes a refresh operation twice for fixed every execution.Wherein, in each
After booting, memory device 1 can obtain a default refresh operation frequency from buffer.Default refresh operation frequency can be the first brush
New operating frequency will refresh those of a non-selected sector N ' storage member.Address signal ADD is for example corresponded to sector
S0.Specifically, firstly, the sector to selection executes erasing instruction twice, and the erasing pulse time of each erasing instruction is recorded
Several and/or erasing voltage level (step S30).Next, it is determined that those of unselected sector (step S31) out.The present embodiment
In, those of unselected sector is sector S1-SN.Then, memory device 1 is according to the erasing pulse number recorded or wiping
Except voltage level, judge whether the erasing pulse number of any erasing instruction or erasing voltage level are more than or equal to a predetermined value
(step S32).When the result of step S32 is no, i.e., when all erasing pulse number or erasing voltage level are less than above-mentioned
When predetermined value, refresh a non-selected sector N ' using the first refresh operation frequency in the final stage of second of erasing instruction
Those of store first (step S34).For example, if a total of 64 sectors of a semiconductor well region, and N ' is 16, then first refreshes
Operating frequency is 1/8.Then, then to the sector of corresponding address signal ADD erasing instruction twice is executed.Then, step S30 is repeated
To S32, to record erasing pulse number and/or erasing voltage level and the wiping for judging any erasing instruction of each erasing instruction
Except whether pulse number or erasing voltage level are more than or equal to a predetermined value.When the result of step S32 is no, i.e., when all
When erasing pulse number or erasing voltage level are less than above-mentioned predetermined value, first is used in the final stage of second of erasing instruction
Refresh operation frequency refreshes those of a non-selected sector N ' and stores first (step S34).And so on, until step S32
Judging result be "Yes", for example, the erasing pulse number or erasing voltage of any erasing instruction are judged in step S32
Level is more than or equal to a predetermined value, refreshes the storage of those of a non-selected sector N " using the second refresh operation frequency at this time
Member, and the second refresh operation frequency is greater than the first refresh operation frequency, i.e. N " is greater than N ' (step S33).N " is, for example, 32, i.e., and
Two refresh operation frequencies are 1/4.
In a preferred embodiment, the address (step S35) of non-selected sector that record has refreshed is further included, and in
In step S33 and step S34, refresh the non-selected sector that do not refreshed.
Fig. 4 indicates the step flow diagram of the method for refreshing of the memory device of another embodiment according to the present invention.?
In the present embodiment, refresh operation frequency is proportional to the inverse of the quantity of sector erasing instruction corresponding in a refresh operation.
After executing the sector erasing instruction of variable number, primary refresh is executed to the non-selected sector of fixed quantity.Storage
Device device 1 executes erasing instruction to the sector of corresponding address signal ADD, and before determining refresh operation according to refresh operation frequency
Erasing instruction quantity.Wherein, after each booting, memory device 1 can obtain a default refresh operation frequency from buffer.In advance
If refresh operation frequency can be the first refresh operation frequency.According to the first refresh operation frequency, memory device 1 will be grasped refreshing
The secondary erasing instruction of X ' is executed to address signal ADD before making.Each refresh operation is to execute to all non-selected sectors.
Specifically, firstly, obtaining the first refresh operation frequency and referring to the secondary erasing of the sector of corresponding address signal ADD execution X '
It enables, and records each erasing pulse number and/or erasing voltage level (step S40).Address signal ADD is for example corresponded to sector
S0.Next, it is determined that those of unselected sector (step S41) out.In the present embodiment, those of unselected sector is sector
S1-SN.Then, memory device 1 judges any erasing pulse according to the erasing pulse number or erasing voltage level that are recorded
Whether number or erasing voltage level are more than or equal to a predetermined value (step S42).When all erasing pulse numbers or erasing electricity
When pressure level is respectively less than above-mentioned predetermined value, the first refresh operation frequency (step S44) is maintained.First refresh operation frequency is, for example,
1/8, i.e. X ' are equal to 8.Then, step S40 to S42 is repeated, with the erasing for executing the secondary erasing instruction of X ', recording each erasing instruction
Pulse number and/or erasing voltage level, and judge whether any erasing pulse number or erasing voltage level are more than or equal to one
Predetermined value.When all erasing pulse numbers or erasing voltage level are less than above-mentioned predetermined value, the first refresh operation frequency is maintained
And those of refreshes all non-selected sectors and store first (step S44).And so on, until the judgement knot of step S42
Fruit is "Yes", i.e., judges that any erasing pulse number or erasing voltage level are more than or equal to a predetermined value in step S42, at this time
Use the second refresh operation frequency (step S43).Wherein, the second refresh operation frequency is greater than the first refresh operation frequency.Second
Refresh operation frequency is, for example, and after Yu Zhihang X " secondary erasing instruction, executes primary brush to all non-selected sectors
Newly, and X " is less than X '.Further, the second refresh operation frequency is, for example, 1/4, i.e. X " is 4.Then, the secondary erasing of X " is executed
The erasing pulse number and/or erasing voltage level (step S45) of each erasing instruction are instructed and recorded, and judges any erasing arteries and veins
Whether jig frequency number or erasing voltage level are more than or equal to a predetermined value (step S42).Judging result according to step S42 is
"Yes" then using the second refresh operation frequency and those of refreshes all non-selected sectors and stores first (step
S43)。
Fig. 5 indicates the step flow diagram of the method for refreshing of memory device according to yet another embodiment of the invention.?
In the present embodiment, after the sector erasing of Yu Zhihang variable number instructs, primary refreshing is executed, and selected in primary refreshing
The quantity of non-selected sector is also variable.Whereby, refresh operation frequency is adjusted.Specifically, 1 basis of memory device
The control instruction that receives and erasing instruction is executed to the cognitive domains of corresponding address signal ADD, wherein after each booting, deposit
Reservoir device 1 can obtain a default refresh operation frequency from buffer.Default refresh operation frequency can be the first refresh operation frequency
Rate, according to the first refresh operation frequency, every execution X ' secondary erasing instruction is non-selected fan a to N ' by memory device 1
Area executes primary refresh.It is, for example, 16 that X ', which is, for example, 4, N ',.Address signal ADD is for example corresponded to sector S0.Specifically, first
First, the first refresh operation frequency is obtained to execute the secondary erasing instruction of X ' to the sector of selection, and is recorded under each erasing instruction
Erasing pulse number and/or erasing voltage level (step S50).Next, it is determined that those of unselected sector (step out
S51).In the present embodiment, those of unselected sector is sector S1-SN.Then, memory device 1 is according to the wiping recorded
Except pulse number or erasing voltage level, it is predetermined to judge whether any erasing pulse number or erasing voltage level are more than or equal to one
It is worth (step S52).When the result of step S52 be it is no, i.e., when all erasing pulse number or erasing voltage level be less than it is above-mentioned
When predetermined value, in X ' final stage of secondary erasing instruction refreshes a non-selected sector N ' using the first refresh operation frequency
Those of store first (step S54).First refresh operation frequency is, for example, 1/16.Then it is secondary, then to address signal ADD to execute X '
Erasing instruction.Then, step S50 to S52 is repeated, to record the erasing pulse number and/or erasing voltage of each erasing instruction
Level simultaneously judges whether any erasing pulse number or erasing voltage level are more than or equal to a predetermined value.When all erasing pulses
When number or erasing voltage level are less than above-mentioned predetermined value, in X ' final stage of secondary erasing instruction uses the first refresh operation
Frequency refreshes those of a non-selected sector N ' and stores first (step S54).And so on, until the judgement knot of step S52
Fruit is "Yes", for example, it is predetermined to judge that any erasing pulse number or erasing voltage level are more than or equal to one in step S52
Value uses the second refresh operation frequency at this time, and the second refresh operation frequency is greater than the first refresh operation frequency, i.e. N " is greater than N '
And X " is less than X ' (step S53).Second refresh operation frequency is, for example, 1/4, and corresponding erasing instruction to X " equal to 2 times and
The primary non-selected sector refreshed N " and be equal to 32.Then, execution X " accumulative to the sector of selection secondary erasing instruction, and
Record the erasing pulse number and/or erasing voltage level (S55) of each erasing instruction.Judging result according to step S52 is
"Yes" then using the second refresh operation frequency and those of refreshes a non-selected sector N " and stores first (step S53).
In a preferred embodiment, more respectively include after the step S53 and step S54 record refreshed it is unselected
Sector address (step S56 and S57), and in step S53 and step S54, refreshing had not been refreshed non-selected
Sector.
Above-described embodiment, which is only illustrated, sets two kinds of refresh operation frequencies, however, the invention is not limited thereto.According to user's
Demand also can define more than two predetermined values, to set three or more refresh operation frequencies.
When erasing pulse number and/or erasing voltage level are greater than or equal to predetermined value, for the aging for improving storage member
It the problem of critical voltage decline of the transistor of those of brought non-selected sector programming storage member, is brushed increasing
New operating frequency.Relatively, first degree of aging lower stage is being stored, using lesser refresh operation frequency, to avoid leakage
It interferes and promotes refreshing efficiency in pole.Whereby, the present invention can be by control the time required to erasing in the range of setting.According to above-mentioned reality
Example is applied, by recording erasing pulse number and/or erasing voltage level under each erasing instruction, is dynamically adjusted refresh operation
Frequency thus can allow memory device 1 efficiently to operate.
Though the present invention is disclosed above in the preferred embodiment, the range that however, it is not to limit the invention, any affiliated sheet
Field related personnel, without departing from the spirit and scope of the present invention, when can do a little change and retouching, thus it is of the invention
Protection scope is subject to view those as defined in claim.
Claims (14)
1. a kind of method for refreshing of memory device, a storage of one of semiconductor well region suitable for a memory device
Device array characterized by comprising
Record the erasing pulse number and/or erasing voltage level in each erasing instruction；
Judge non-selected multiple sectors；
Judge whether any erasing pulse number or the erasing voltage level are more than or equal to a predetermined value；
When any erasing pulse number or the erasing voltage level are more than or equal to the predetermined value, one second brush is used
New operating frequency refreshes the non-selected sector；And
When the erasing pulse number or the erasing voltage level are less than the predetermined value, one first refresh operation frequency is used
Rate refreshes the non-selected sector, and the first refresh operation frequency is less than the second refresh operation frequency.
2. method for refreshing as described in claim 1, which is characterized in that the memory device is set to a flash memory.
3. method for refreshing as described in claim 1, which is characterized in that after the erasing instruction of Yu Zhihang fixed quantity, execute
The method for refreshing, and the number of the non-selected sector of the second refresh operation frequency refreshing is greater than first brush
The number for the non-selected sector that new operating frequency refreshes.
4. method for refreshing as claimed in claim 3, which is characterized in that further include the non-selected sector that record has refreshed
Address, and using the first refresh operation frequency or the second refresh operation frequency refresh not described in refreshing not by
The sector of selection.
5. method for refreshing as described in claim 1, which is characterized in that after the erasing instruction of Yu Zhihang variable number, execute
The method for refreshing, and when using the second refresh operation frequency, wiping is executed to the sector of selection before refresh operation
Referred to except the number of instruction is less than using executing erasing to the sector of selection before refresh operation when the first refresh operation frequency
The number of order.
6. method for refreshing as claimed in claim 5, which is characterized in that use the first refresh operation frequency or described second
Refresh operation frequency refreshes all non-selected sectors.
7. method for refreshing as claimed in claim 5, which is characterized in that the second refresh operation frequency refreshes unselected
Sector number be greater than the first refresh operation frequency refresh non-selected sector number.
8. method for refreshing as claimed in claim 7 further includes the address for the non-selected sector that record has refreshed, and uses
The first refresh operation frequency or the second refresh operation frequency refresh the non-selected sector that do not refreshed.
9. a kind of memory device of adjustable refresh operation frequency characterized by comprising
One memory array, including multiple sectors, are set to semiconductor well region；
One decoder, receives an address signal, and the decoder selects the multiple sector wherein according to the address signal
One, and an at least erasing pulse and its corresponding erasing voltage level are provided to the sector selected；
One erased conditions logger records erasing pulse number and/or erasing voltage level in each erasing instruction；And
One buffer, one first refresh operation frequency of storage and one second refresh operation frequency, and first refresh operation frequency
Rate is less than the second refresh operation frequency；
Wherein, when the erasing pulse number or the erasing voltage level are more than or equal to a predetermined value, described second is used
Refresh operation frequency refreshes non-selected sector；
Wherein, it when the erasing pulse number or the erasing voltage level are less than the predetermined value, is brushed using described first
New operating frequency refreshes the non-selected sector.
10. memory device as claimed in claim 9, which is characterized in that the memory device is set to a flash memory.
11. memory device as claimed in claim 9, which is characterized in that the second refresh operation frequency refresh not by
The number of the sector of selection is greater than the number for the non-selected sector that the first refresh operation frequency refreshes.
12. memory device as claimed in claim 9, which is characterized in that when using the second refresh operation frequency, in
The number of the sector execution erasing instruction of selection is less than before refresh operation when using the first refresh operation frequency in refreshing
The number of erasing instruction is executed before operation to the sector of selection.
13. memory device as claimed in claim 12, which is characterized in that use the first refresh operation frequency or described
Second refresh operation frequency refreshes all non-selected sectors.
14. memory device as claimed in claim 12, which is characterized in that the second refresh operation frequency refresh not by
The number of the sector of selection is greater than the number for the non-selected sector that the first refresh operation frequency refreshes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610009723.7A CN106952662B (en) | 2016-01-07 | 2016-01-07 | The memory device of memory device method for refreshing and adjustable refresh operation frequency |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610009723.7A CN106952662B (en) | 2016-01-07 | 2016-01-07 | The memory device of memory device method for refreshing and adjustable refresh operation frequency |
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| Publication Number | Publication Date |
|---|---|
| CN106952662A CN106952662A (en) | 2017-07-14 |
| CN106952662B true CN106952662B (en) | 2019-10-01 |
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| CN114974343B (en) * | 2021-02-24 | 2024-09-03 | 华邦电子股份有限公司 | Semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell |
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