CN106933064A - Realize the photoetching process of smaller line width - Google Patents
Realize the photoetching process of smaller line width Download PDFInfo
- Publication number
- CN106933064A CN106933064A CN201710190157.9A CN201710190157A CN106933064A CN 106933064 A CN106933064 A CN 106933064A CN 201710190157 A CN201710190157 A CN 201710190157A CN 106933064 A CN106933064 A CN 106933064A
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- China
- Prior art keywords
- line width
- exposure
- photoetching process
- silicon nitride
- nitride layer
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
Abstract
The invention discloses a kind of photoetching process for realizing smaller line width, including：Substrate is provided, and in substrate surface silicon oxide layer deposited and silicon nitride layer；Photoresist is coated on silicon nitride layer surface；The silicon oxide layer surface is exposed using the first litho machine and forms exposure figure；The exposure figure is etched, and removes photoresist；Using the level to level alignment technology of the second litho machine, and alignment precision side-play amount is set according to required line width；According to the alignment precision side-play amount in silicon oxide layer and silicon nitride layer surface coating photoresist；Second exposure is carried out to the exposure figure, new exposure figure is formed；The new exposure figure of etching, and remove photoresist；Silicon oxide layer and silicon nitride layer on removal substrate, form polysilicon graphics.The present invention can obtain the figure of smaller line width, and then reduce production cost on the premise of not service precision litho machine higher.
Description
Technical field
The present invention relates to IC manufacturing field, more particularly to a kind of photoetching process for realizing smaller line width.
Background technology
The development of integrated circuit technique is exactly the continuous challenge to physics limit, for photoetching process, litho machine
Develop from G-line (G Lithographies), 365nm I-line (I Lithographies), 248nm DUV (deep-UV lithography), to 193nm ArF
Excimer lithography and immersion lithography, then to EUV (extreme ultraviolet photolithographic), lead the continuous diminution of feature sizes.The thing followed is
Rising steadily for litho machine cost, causes photoetching R＆D costs to significantly improve.
For the process lifetime for how extending litho machine, smaller line width can be formed, be the challenge to photoetching process.
As a rule, the resolution limit of deep-UV lithography machine is in 0.11um.If characteristic size exists needed for integrated circuit technology
Below 0.11um, will use ArF (193nm) litho machine for photoetching, and this means that being substantially increased for cost, for
How to extend the process lifetime of litho machine, smaller line width can be formed, be the challenge to photoetching process.Therefore, how
On the premise of control cost, smaller line width figure is obtained, be those skilled in the art's technical problem urgently to be resolved hurrily.
The content of the invention
The present invention provides a kind of photoetching process for realizing smaller line width, and smaller line is obtained with the premise of cost is controlled
Figure wide.
In order to solve the above technical problems, the present invention provides a kind of photoetching process for realizing smaller line width, including：
Substrate is provided, and in substrate surface silicon oxide layer deposited and silicon nitride layer；
Photoresist is coated on silicon nitride layer surface；
The silicon nitride layer surface is exposed using the first litho machine and forms exposure figure；
The exposure figure is etched, and removes photoresist；
Using the level to level alignment technology of the second litho machine, and alignment precision side-play amount is set according to required line width；
According to the alignment precision side-play amount in silicon oxide layer and silicon nitride layer surface coating photoresist；
Second exposure is carried out to the exposure figure, new exposure figure is formed；
The new exposure figure of etching, and remove photoresist；
Silicon oxide layer and silicon nitride layer on removal substrate, form polysilicon graphics.
Preferably, using diffusion technique in substrate surface silicon oxide layer deposited and silicon nitride layer.
Preferably, the diffusion technique is carried out in oxidized diffusion stove.
Preferably, using chemical vapour deposition technique in substrate surface silicon oxide layer deposited and silicon nitride layer.
Preferably, first litho machine uses I Lithographies machine or deep-submicron litho machine, second litho machine
Using deep-submicron litho machine.
Preferably, the deep-submicron litho machine is deep-UV lithography machine.
Preferably, removing photoresist using wet method resist remover.
Preferably, being performed etching to exposure figure using plasma etching machine.
Preferably, the alignment precision side-play amount is set in second litho machine in advance, alignment precision skew
Amount is equal with the line width of polysilicon graphics.
Preferably, the thickness of the silicon oxide layer and silicon nitride layer can be adjusted according to process requirements.
Compared with prior art, the present invention utilizes the level to level alignment technology and alignment precision side-play amount of litho machine, to wafer
Re-expose is carried out, and then smaller line width figure, Jin Erke can be obtained on the premise of higher precision litho machine is not used
To reduce production cost.Secondly, photoetching process of the invention is applied to the every field such as research and development, teaching, and can effectively save more
The use of high accuracy litho machine, reduces cost.The present invention suitable for various sizes lithographic equipment, such as 8 inches, 12 inches, 18
Inch and more large-sized silicon chip manufacturing equipment.
Brief description of the drawings
Fig. 1 is the structural representation after wafer coating photoresist in the present invention；
Fig. 2 is wafer structural representation for the first time after exposure etching in the present invention；
Fig. 3 is the structural representation that wafer is coated after photoresist for second in the present invention；
Fig. 4 is the structural representation that wafer is exposed after etching for second in the present invention；
Fig. 5 is the structural representation after wafer removal photoresist in the present invention；
Fig. 6 is to obtain the crystal circle structure schematic diagram after smaller line width figure in the present invention.
Shown in figure：10- substrates, 20- silicon oxide layers, 30- silicon nitride layers, 40- photoresists.
Specific embodiment
To enable the above objects, features and advantages of the present invention more obvious understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.It should be noted that, accompanying drawing of the present invention is in the form of simplification and using non-essence
Accurate ratio, is only used to conveniently, lucidly aid in illustrating the purpose of the embodiment of the present invention.
The present invention provides a kind of photoetching process for realizing smaller line width, including：
As shown in Figure 1, there is provided substrate 10, and on the surface of substrate 10 deposit to form silicon oxide layer 20 and silicon nitride layer 30；Tool
Body can deposit the silica 20 and silicon nitride layer 30 by the way of diffusion technique or chemical vapor deposition.Certainly, expand
Day labor skill needs to be carried out in oxidized diffusion stove.It should be noted that the thickness of silicon oxide layer 20 and silicon nitride layer 30 can be with root
Factually border process requirements are adjusted, specifically can be by changing the technological parameter of diffusion technique or chemical vapor deposition come real
It is existing.
With continued reference to Fig. 1, then, photoresist 40 is coated on the surface of silicon nitride layer 30；
The surface of the silicon nitride layer 30 is carried out using the first litho machine expose and form exposure figure for the first time；
As shown in Fig. 2 plasma etching machine etches the exposure figure, removal partial nitridation silicon layer 30, then, using wet
Method resist remover removes the photoresist 40 of the excess surface of silicon nitride layer 30；
Fig. 3 is refer to, then, using the level to level alignment technology of the second litho machine, and alignment essence is set according to required line width
Degree side-play amount, and according to the alignment precision side-play amount in silicon oxide layer 20 and the surface of silicon nitride layer 30 coating photoresist 40；Specifically
Ground, the alignment precision side-play amount is the line width width of the polysilicon graphics for ultimately forming, and the alignment precision side-play amount
Can be set in advance in second litho machine, when process requirements have change, it is also possible to the alignment essence in the second litho machine
Degree side-play amount is modified.
Then, as shown in figure 4, the second litho machine carries out second exposure to the exposure figure, new exposure diagram is formed
Shape.
As shown in figure 5, plasma etching machine etches new exposure figure, wet method resist remover removes unnecessary photoresist；
Then, as shown in fig. 6, removing the silicon oxide layer 20 and silicon nitride layer 30 on substrate 10, final polysilicon is formed
Figure, the line width width of the polysilicon graphics is equal to the alignment precision side-play amount set in the second litho machine.
From above-mentioned steps, in photoetching process of the invention, second figure of exposure has relative to first time exposure
Certain side-play amount, and the alignment precision side-play amount can be the line width width of subsequent diagram, in other words, the present invention is by right
Wafer is double exposed so that the line width width of the exposure figure for ultimately forming is not limited by the resolution limit of litho machine,
Can utilize the litho machine of larger resolution ratio to obtain smaller line width figure, reduce production cost while extending litho machine
Process lifetime.
Embodiment 1
First, second litho machine in the present embodiment uses I Lithography machines, and its resolution pole is limited to 365nm, by adopting
With above-mentioned photoetching process of the invention, figure of the line width width less than 35 μm can be obtained, its specific steps includes：
Referring to figs. 1 to Fig. 6, there is provided wafer, the wafer is followed successively by substrate 10, silicon oxide layer 20 and silicon nitride layer from bottom to top
30；
In crystal column surface coating photoresist 40, first time exposure is carried out to above-mentioned wafer using I Lithographies machine, form corresponding
Exposure figure；
Above-mentioned wafer is performed etching according to the exposure figure, removes the partial silicon nitride of above-mentioned wafer upper surface；It
After carry out wet method degumming process and remove remaining photoresist 40；
To crystal column surface coating photoresist 40 and second photo-etching machine exposal is carried out, it is necessary to explanation is, now enter again
Row exposure, using the default alignment precision side-play amount of I Lithography machines so that exposure has second figure of exposure for the first time relatively
Certain side-play amount, the alignment precision side-play amount in the present embodiment is preset as 0.16 μm according to demand, and the default alignment is smart
The side-play amount of degree is just ultimately formed the line width width of figure.
Second etching is carried out to above-mentioned wafer, the silicon oxide layer 20 and silicon nitride layer 30 on the surface of substrate 10 is removed, and then
Less than the 0.35 μm polysilicon graphics of (the present embodiment is 0.16 μm) can be obtained.
Embodiment 2
First, second litho machine in the present embodiment uses deep-submicron litho machine, specific deep-UV lithography litho machine,
By using above-mentioned photoetching process of the invention, figure of the line width width less than 0.11 μm can be obtained, its specific steps includes：
Referring still to Fig. 1 to Fig. 6, first, in the surface silicon oxide layer deposited 20 of substrate 10 and silicon nitride layer 30, wherein, oxygen
The thickness of SiClx layer 20 and silicon nitride layer 30 needs to be adjusted according to technique；
By deep-UV lithography machine, exposure forms 0.18 μm of exposure figure of line width for the first time；
Then, the exposure figure of 0.18 μm of line width is performed etching with plasma etching industrial, and removes photoresist 40
It is remaining；
Then, using the level to level alignment technology of deep-UV lithography machine, it is 0.09 μm that alignment precision side-play amount is set in advance, and
Second exposure is carried out, 0.18 μm of new exposure figure of line width is formed.
Plasma etching machine is reused to perform etching the exposure figure of 0.18 μm of new line width；
Remaining photoresist 40 is removed photoresist；
Silicon oxide layer 20 and silicon nitride layer 30 are removed, the figure less than less than 0.11 μm (the present embodiment is 0.09 μm) is formed
Shape.
Certainly, the alignment precision side-play amount in above-mentioned steps can be changed according to demand, in other words, be finally given
Figure line width can also be changed as needed.The present embodiment carries out re-expose by using deep-submicron litho machine
Method, can yield less than less than 0.11 μm of line width figure, it is adaptable to research and develop, teach in the case where ArF litho machines are not used
The demand during technique of etc., significantly reduces R＆D costs.
Obviously, those skilled in the art can carry out various changes and modification without deviating from spirit of the invention to invention
And scope.So, if these modifications of the invention and modification belong to the claims in the present invention and its equivalent technologies scope it
Interior, then the present invention is also intended to including including these changes and modification.
Claims (10)
1. a kind of photoetching process for realizing smaller line width, it is characterised in that including：
Substrate is provided, and in substrate surface silicon oxide layer deposited and silicon nitride layer；
Photoresist is coated on silicon nitride layer surface；
The silicon nitride layer surface is exposed using the first litho machine and forms exposure figure；
The exposure figure is etched, and removes photoresist；
Using the level to level alignment technology of the second litho machine, and alignment precision side-play amount is set according to required line width；
According to the alignment precision side-play amount in silicon oxide layer and silicon nitride layer surface coating photoresist；
Second exposure is carried out to the exposure figure, new exposure figure is formed；
The new exposure figure of etching, and remove photoresist；
Silicon oxide layer and silicon nitride layer on removal substrate, form polysilicon graphics.
2. the photoetching process of smaller line width is realized as claimed in claim 1, it is characterised in that using diffusion technique in substrate table
Face silicon oxide layer deposited and silicon nitride layer.
3. the photoetching process of smaller line width is realized as claimed in claim 2, it is characterised in that the diffusion technique expands in oxidation
Carried out in scattered stove.
4. the photoetching process of smaller line width is realized as claimed in claim 1, it is characterised in that existed using chemical vapour deposition technique
Substrate surface silicon oxide layer deposited and silicon nitride layer.
5. the photoetching process of smaller line width is realized as claimed in claim 1, it is characterised in that first litho machine uses I
Lithography machine or deep-submicron litho machine, second litho machine use I Lithographies machine or deep-submicron litho machine.
6. the as claimed in claim 5 photoetching process for realizing smaller line width, it is characterised in that the deep-submicron litho machine is
Deep-UV lithography machine.
7. the photoetching process of smaller line width is realized as claimed in claim 1, it is characterised in that using wet method resist remover removal light
Photoresist.
8. the photoetching process of smaller line width is realized as claimed in claim 1, it is characterised in that using plasma etching machine to exposing
Light figure is performed etching.
9. the photoetching process of smaller line width is realized as claimed in claim 1, it is characterised in that the alignment precision side-play amount is carried
Before be set in second litho machine, the alignment precision side-play amount is equal with the line width of polysilicon graphics.
10. the photoetching process of smaller line width is realized as claimed in claim 1, it is characterised in that the silicon oxide layer and nitridation
The thickness of silicon layer can be adjusted according to process requirements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710190157.9A CN106933064B (en) | 2017-03-27 | 2017-03-27 | Realize the photoetching process of smaller line width |
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| CN201710190157.9A CN106933064B (en) | 2017-03-27 | 2017-03-27 | Realize the photoetching process of smaller line width |
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| CN106933064A true CN106933064A (en) | 2017-07-07 |
| CN106933064B CN106933064B (en) | 2018-11-09 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231796A (en) * | 2018-01-03 | 2018-06-29 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
| CN115793413A (en) * | 2022-12-22 | 2023-03-14 | 上海铭锟半导体有限公司 | Super-resolution pattern realization method and device based on alignment difference and double photoetching |
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| US5532114A (en) * | 1994-02-07 | 1996-07-02 | Hyundai Electronics Industries Co., Ltd. | Method of forming a photoresist pattern in a semiconductor device |
| JPH10209039A (en) * | 1997-01-27 | 1998-08-07 | Nikon Corp | Method and apparatus for projection exposure |
| US20040021841A1 (en) * | 2002-08-01 | 2004-02-05 | Kenichiro Mori | Exposure method and apparatus |
| CN101171549A (en) * | 2005-05-10 | 2008-04-30 | 朗姆研究公司 | Reticle alignment and overlay for multiple reticle process |
| CN102403200A (en) * | 2011-11-29 | 2012-04-04 | 无锡中微晶园电子有限公司 | Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine |
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2017
- 2017-03-27 CN CN201710190157.9A patent/CN106933064B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5532114A (en) * | 1994-02-07 | 1996-07-02 | Hyundai Electronics Industries Co., Ltd. | Method of forming a photoresist pattern in a semiconductor device |
| JPH10209039A (en) * | 1997-01-27 | 1998-08-07 | Nikon Corp | Method and apparatus for projection exposure |
| US20040021841A1 (en) * | 2002-08-01 | 2004-02-05 | Kenichiro Mori | Exposure method and apparatus |
| CN101171549A (en) * | 2005-05-10 | 2008-04-30 | 朗姆研究公司 | Reticle alignment and overlay for multiple reticle process |
| CN102403200A (en) * | 2011-11-29 | 2012-04-04 | 无锡中微晶园电子有限公司 | Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231796A (en) * | 2018-01-03 | 2018-06-29 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
| CN115793413A (en) * | 2022-12-22 | 2023-03-14 | 上海铭锟半导体有限公司 | Super-resolution pattern realization method and device based on alignment difference and double photoetching |
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| CN106933064B (en) | 2018-11-09 |
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